High-voltage light-emitting diode chip, chip transfer structure and electronic equipment

Abstract

The utility model provides a high-voltage light-emitting diode chip, a chip transfer structure and electronic equipment, and relates to the technical field of semiconductor devices. The high-voltage light-emitting diode chip comprises a dielectric layer; the first light-emitting epitaxial layer to the Nth light-emitting epitaxial layer and the first light-emitting epitaxial layer to the Nth light-emitting epitaxial layer are all located on one side of the dielectric layer. The first insulating layer covers the exposed surfaces of the first semiconductor layer, the light-emitting layer and the second semiconductor layer; and the first bonding pad, the first connecting wire to the (N-1) th connecting wire and the second bonding pad are arranged on the substrate. According to the technical scheme provided by the invention, the light-emitting epitaxial layer of the high-voltage light-emitting diode chip is located on the dielectric layer, so that a substrate structure such as sapphire in an existing chip is omitted, the problem that the substrate structure limits the size of the chip is avoided, and the high-voltage light-emitting diode chip is simple in structure and smaller in size; the design flexibility and yield of the high-voltage light-emitting diode chip are improved, and the high-voltage light-emitting diode chip is more in line with the market development demand.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a high-voltage light-emitting diode chip, a chip transfer structure, and an electronic device. Background Technology

[0002] Light-emitting diodes (LEDs) are commonly used light-emitting devices with advantages such as low voltage, low power consumption, small size, long lifespan, and high safety, making them widely used in lighting and display fields. High-voltage LEDs are produced by dividing a large chip into multiple small light-emitting units during chip fabrication, then connecting these units in series via electrodes. This results in a high-power LED with low current and high voltage. High-voltage LED chips reduce driving costs and wire bonding work in packaging plants, making them a promising LED product. However, existing high-voltage LED chips have a relatively complex structure and large size, requiring further device improvements. Utility Model Content

[0003] In view of this, this application provides a high-voltage light-emitting diode chip, a chip transfer structure, and an electronic device, which effectively solves the technical problems existing in the prior art. The high-voltage light-emitting diode chip has a simple structure and smaller size, which improves the design flexibility and production yield of the high-voltage light-emitting diode chip and is more in line with market development needs.

[0004] To achieve the above objectives, the technical solution provided in this application is as follows:

[0005] A high-voltage light-emitting diode chip, the high-voltage light-emitting diode chip comprising:

[0006] Dielectric layer;

[0007] From the first light-emitting epitaxial layer to the Nth light-emitting epitaxial layer, all of them are located on one side of the dielectric layer. Each light-emitting epitaxial layer includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer that are located on the dielectric layer and stacked in sequence. N is an integer greater than 1.

[0008] A first insulating layer covers the exposed surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, and the first insulating layer includes a first cutout area exposing the first semiconductor layer and a second cutout area exposing the second semiconductor layer.

[0009] A first pad, a first connecting wire to a (N-1)th connecting wire and a second pad, wherein the first pad is located at the first cutout area of ​​the first light-emitting epitaxial layer and is electrically connected to the first semiconductor layer of the first light-emitting epitaxial layer; the second pad is located at the second cutout area of ​​the Nth light-emitting epitaxial layer and is electrically connected to the second semiconductor layer of the Nth light-emitting epitaxial layer; the two ends of the i-th connecting wire are located at the second cutout area of ​​the i-th light-emitting epitaxial layer and the first cutout area of ​​the (i+1)th light-emitting epitaxial layer, respectively, and the i-th connecting wire is electrically connected to the second semiconductor layer of the i-th light-emitting epitaxial layer and the first semiconductor layer of the (i+1)th light-emitting epitaxial layer, where i is a positive integer less than N.

[0010] Optionally, the high-voltage light-emitting diode chip further includes:

[0011] A second insulating layer, which at least covers the i-th connecting wire.

[0012] Optionally, the thickness of the second insulating layer is no greater than 1.5 micrometers.

[0013] Optionally, the contact surface between the dielectric layer and the first semiconductor layer is a roughened surface.

[0014] Optionally, the thickness of the dielectric layer is not less than 1 micrometer.

[0015] Optionally, the surfaces of the first and second pads facing away from the dielectric layer are higher in a first direction than the surfaces of other components of the high voltage light-emitting diode chip facing away from the dielectric layer.

[0016] The first direction is the direction from the dielectric layer to the light-emitting epitaxial layer.

[0017] Based on the same inventive concept, this application also provides a chip transfer structure, the chip transfer structure comprising:

[0018] At least two of the aforementioned high-voltage light-emitting diode chips;

[0019] A temporary substrate, wherein the high-voltage light-emitting diode chip is fixedly connected to the same side of the temporary substrate.

[0020] Optionally, the dielectric layer of the high-voltage light-emitting diode chip faces the temporary substrate.

[0021] The chip transfer structure includes an insulating bonding layer located between the high-voltage light-emitting diode chip and the temporary substrate.

[0022] Optionally, the first and second pads of the high-voltage light-emitting diode chip face the temporary substrate.

[0023] The chip transfer structure includes an insulating bonding layer located between the high-voltage light-emitting diode chip and the temporary substrate.

[0024] Based on the same inventive concept, this application also provides an electronic device, which includes the above-mentioned high-voltage light-emitting diode chip.

[0025] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:

[0026] This application provides a high-voltage light-emitting diode chip, a chip transfer structure, and an electronic device. The high-voltage light-emitting diode chip includes: a dielectric layer; a first light-emitting epitaxial layer to an Nth light-emitting epitaxial layer, all of which are located on one side of the dielectric layer, and each light-emitting epitaxial layer includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially on the dielectric layer, where N is an integer greater than 1; a first insulating layer, which covers the exposed surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, and includes a first cutout area exposing the first semiconductor layer and a second cutout area exposing the second semiconductor layer; a first pad, a first... Connecting wires to the (N-1)th connecting wire and the second pad, the first pad being located at the first cutout area of ​​the first light-emitting epitaxial layer and electrically connected to the first semiconductor layer of the first light-emitting epitaxial layer; the second pad being located at the second cutout area of ​​the Nth light-emitting epitaxial layer and electrically connected to the second semiconductor layer of the Nth light-emitting epitaxial layer; the two ends of the i-th connecting wire being located at the second cutout area of ​​the i-th light-emitting epitaxial layer and the first cutout area of ​​the (i+1)-th light-emitting epitaxial layer, respectively, the i-th connecting wire being electrically connected to the second semiconductor layer of the i-th light-emitting epitaxial layer and the first semiconductor layer of the (i+1)-th light-emitting epitaxial layer, where i is a positive integer less than N.

[0027] As can be seen from the above, the technical solution provided in this application has an epitaxial layer for the high-voltage light-emitting diode chip located on the dielectric layer, thereby eliminating the need for substrate structures such as sapphire in existing chips. This avoids the problem of substrate structures limiting the size of the chip, making the high-voltage light-emitting diode chip simpler in structure and smaller in size. It also improves the design flexibility and yield of the high-voltage light-emitting diode chip, and is more in line with market development needs. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a high-voltage light-emitting diode chip provided in an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of another high-voltage light-emitting diode chip provided in an embodiment of this application;

[0031] Figure 3 A schematic diagram of the structure of another high-voltage light-emitting diode chip provided in the embodiments of this application;

[0032] Figure 4 A schematic diagram of the structure of another high-voltage light-emitting diode chip provided in the embodiments of this application;

[0033] Figure 5 This is a schematic diagram of a chip transfer structure provided in an embodiment of this application;

[0034] Figure 6 This is a schematic diagram of another chip transfer structure provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] As described in the background section, light-emitting diodes (LEDs) are commonly used light-emitting devices with advantages such as low voltage, low power consumption, small size, long lifespan, and high safety, making them widely used in lighting and display fields. High-voltage LEDs are produced by dividing a large chip into multiple small light-emitting units during chip fabrication, and then connecting these units in series via electrodes, thus creating a high-power LED with low current and high voltage. High-voltage LED chips reduce driving costs and wire bonding work in packaging plants, making them a promising LED product. However, existing high-voltage LED chips have a relatively complex structure and large size, requiring further device improvements.

[0037] Based on this, the embodiments of this application provide a high-voltage light-emitting diode chip, a chip transfer structure, and an electronic device, which effectively solves the technical problems existing in the prior art. The high-voltage light-emitting diode chip has a simple structure and smaller size, which improves the design flexibility and production yield of the high-voltage light-emitting diode chip and is more in line with market development needs.

[0038] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 6 The technical solutions provided in the embodiments of this application will be described in detail.

[0039] refer to Figure 1 The above is a schematic diagram of the structure of a high-voltage light-emitting diode chip provided in an embodiment of this application. The high-voltage light-emitting diode chip provided in this embodiment of the application includes: a dielectric layer 100 and a first light-emitting epitaxial layer 201 to an Nth light-emitting epitaxial layer. Therefore, the first light-emitting epitaxial layer 201 to the Nth light-emitting epitaxial layer are all located on the same side of the dielectric layer 100. The intervals between different light-emitting epitaxial layers are distributed on the surface of the same side of the dielectric layer 100. Any light-emitting epitaxial layer 200 includes a first semiconductor layer 210, a light-emitting layer 220 and a second semiconductor layer 230 located on the dielectric layer 100 and stacked in sequence. The first semiconductor layer 210, the light-emitting layer 220 and the second semiconductor layer 230 are stacked in sequence along a first direction Y. The first direction Y is the direction from the dielectric layer 100 to the light-emitting epitaxial layer 200, and N is an integer greater than 1. The high-voltage light-emitting diode chip also includes a first insulating layer 310, which covers the exposed surfaces of the first semiconductor layer 210, the light-emitting layer 220 and the second semiconductor layer 230. The first insulating layer 310 includes a first cutout area exposing the first semiconductor layer 210 and a second cutout area exposing the second semiconductor layer 230. The high-voltage light-emitting diode chip further includes a first pad 410, a first connecting wire 431 to the (N-1)th connecting wire, and a second pad 420. The first pad 410 is located at the first cutout area of ​​the first light-emitting epitaxial layer 201, and the first pad 410 is electrically connected to the first semiconductor layer 210 of the first light-emitting epitaxial layer 201. The second pad 420 is located at the second cutout area of ​​the Nth light-emitting epitaxial layer, and the second pad 420 is electrically connected to the second semiconductor layer 230 of the Nth light-emitting epitaxial layer. The two ends of the i-th connecting wire are located at the second cutout area of ​​the i-th light-emitting epitaxial layer and the first cutout area of ​​the (i+1)th light-emitting epitaxial layer, respectively. The i-th connecting wire electrically connects the second semiconductor layer 230 of the i-th light-emitting epitaxial layer and the first semiconductor layer 210 of the (i+1)th light-emitting epitaxial layer. The i-th connecting wire is used to connect the i-th light-emitting epitaxial layer and the (i+1)th light-emitting epitaxial layer in series, where i is a positive integer less than N.

[0040] Continue as Figure 1 As shown, taking N=2 as an example, a more detailed explanation of the high-voltage light-emitting diode (LED) chip is provided. The high-voltage LED chip includes a first light-emitting epitaxial layer 201 and a second light-emitting epitaxial layer 202, and includes a connecting wire, namely the first connecting wire 431. The two ends of the first connecting wire 431 are located at the second cutout area of ​​the first light-emitting epitaxial layer 201 and the first cutout area of ​​the second light-emitting epitaxial layer 202, respectively. The first connecting wire 431 electrically connects the second semiconductor layer 230 of the first light-emitting epitaxial layer 201 and the first semiconductor layer 210 of the second light-emitting epitaxial layer 202, connecting them in series. A first pad 410 is located at the first cutout area of ​​the first light-emitting epitaxial layer 201 and is electrically connected to the first semiconductor layer 210 of the first light-emitting epitaxial layer 201; a second pad 420 is located at the second cutout area of ​​the second light-emitting epitaxial layer 202 and is electrically connected to the second semiconductor layer 230 of the second light-emitting epitaxial layer 202. In some embodiments, the superimposed structure of the first semiconductor layer 210, the light-emitting layer 220 and the second semiconductor layer 230 provided in this application embodiment may have a step region, wherein a portion of the surface of the first semiconductor layer 210 facing away from the dielectric layer 100 is exposed at the step region, and the first hollow area is located at the step region.

[0041] It should be noted that this application uses N=2 as an example to illustrate the high-voltage light-emitting diode chip. In some other embodiments, N can be other numbers, and this application does not impose specific limitations on this; the specific selection should be based on the actual application. Since it is difficult to thin the substrate to below 50 micrometers, this application embodiment can use evaporation or CVD processes to fabricate the epitaxial layer and replace the substrate with a dielectric layer, thereby fabricating the high-voltage light-emitting diode chip into a micrometer-scale chip structure. Therefore, the technical solution provided by this application embodiment places the light-emitting epitaxial layer 200 of the high-voltage light-emitting diode chip on the dielectric layer 100, thus eliminating the need for sapphire or other substrate structures in existing chips. This achieves a free-standing, substrate-free micrometer-scale high-voltage light-emitting diode chip structure, avoiding the problem of substrate structures limiting chip size. This results in a simpler and smaller high-voltage light-emitting diode chip structure, improving the design flexibility and yield of the high-voltage light-emitting diode chip, and better meeting market development needs.

[0042] In some embodiments, the dielectric layer 100 provided in this application can be a structural layer of inorganic material. Optionally, the material of the dielectric layer 100 provided in this application can be oxides or nitrides such as TiOx, SiOx, SiNx, Al2O3, and AlN, and this application does not impose specific limitations on this. Furthermore, the thickness of the dielectric layer 100 provided in this application can be designed to be not less than 1 micrometer, thereby improving chip yield and process flexibility in user packaging, reducing yield loss during user packaging bonding, and meeting diverse user design requirements. Also, the first insulating layer 310 provided in this application can also be a structural layer of inorganic material. Optionally, the material of the first insulating layer 310 provided in this application can be oxides or nitrides such as TiOx, SiOx, SiNx, Al2O3, and AlN, and this application does not impose specific limitations on this. Furthermore, the thickness of the first insulating layer 310 provided in this application can be designed to be not greater than 1.5 micrometers to reduce the size of the high-voltage light-emitting diode chip, thereby improving the design flexibility of the high-voltage light-emitting diode chip.

[0043] like Figure 2 The diagram shown is a structural schematic of another high-voltage light-emitting diode chip provided in this application embodiment. The high-voltage light-emitting diode chip provided in this application embodiment further includes a second insulating layer 320, which at least covers the i-th connecting wire. Specifically, as shown... Figure 2 When a medium-to-high voltage LED chip includes a first light-emitting epitaxial layer 201 and a second light-emitting epitaxial layer 202, the second insulating layer 320 at least covers the exposed surface of the first connecting wire 431. The second insulating layer 320 covers the connecting wire, thereby protecting it and reducing the probability of damage to the connecting wire leading to LED chip failure. Furthermore, the second insulating layer 320 also prevents the connecting wire from being subjected to external electrical stimulation, avoiding electrical connection problems between the connecting wire and external circuitry, thus improving the reliability of the high-voltage LED chip.

[0044] In some embodiments, the second insulating layer 320 provided in this application can also be a structural layer of inorganic material. Optionally, the material of the second insulating layer 320 provided in this application can be oxides or nitrides such as TiOx, SiOx, SiNx, Al2O3, and AlN, and this application does not impose specific limitations on this. Furthermore, the thickness of the second insulating layer 320 provided in this application can be designed to be no greater than 1.5 micrometers to reduce the size of the high-voltage light-emitting diode chip, thereby improving the design flexibility of the high-voltage light-emitting diode chip. It should be noted that the materials of the first insulating layer 310 and the second insulating layer 320 provided in this application can be the same material, or the materials of the first insulating layer 310 and the second insulating layer 320 can be different materials, and this application does not impose specific limitations on this.

[0045] like Figure 3 The diagram shown is a structural schematic of another high-voltage light-emitting diode (LED) chip provided in this application embodiment. In this embodiment, the contact surface between the dielectric layer 100 and the first semiconductor layer 210 is a roughened surface. It can be seen that by designing the contact surface between the dielectric layer 100 and the first semiconductor layer 210 as a roughened surface, the light extraction efficiency of the high-voltage LED chip can be improved, further enhancing its performance.

[0046] like Figure 4The diagram shows a structural schematic of another high-voltage light-emitting diode chip provided in this application embodiment. In this application embodiment, the surfaces of the first pad 410 and the second pad 420 on the side away from the dielectric layer 100 are higher than the surfaces of other components of the high-voltage light-emitting diode chip on the side away from the dielectric layer 100 in the first direction Y. The first direction Y is the direction from the dielectric layer 100 to the light-emitting epitaxial layer 200. Taking a high-voltage light-emitting diode (LED) chip including a second insulating layer 320 as an example, the second insulating layer 320 is the outer structural layer of the LED chip on the side away from the dielectric layer 100. The surfaces of the first pad 410 and the second pad 420 on the side away from the dielectric layer 100 are in the same plane and are higher than the surface of the second insulating layer 320 on the side away from the dielectric layer 100 in the first direction Y. There is a height difference H between the surfaces of the first pad 410 and the second pad 420 on the side away from the dielectric layer 100 and the surface of the second insulating layer 320 on the side away from the dielectric layer 100. This improves the situation where the thickness (i.e., the height) is too small and the wires are easily broken when the pads need to cross the chip steps and other structures. The height difference facilitates the connection lines of the high-voltage chip series light-emitting epitaxial layer and also facilitates the electrical connection of the pads with other circuit board structures. This improves the flexibility of the high-voltage LED chip packaging process and reduces the yield loss of high-voltage LED chip packaging bonding. In some embodiments, the first pad 410 and the second pad 420 provided in this application can be metal pads, and this application does not impose specific limitations on this.

[0047] In some embodiments, the high-voltage light-emitting diode chip provided in this application may include only one of the following three features: (1) a second insulating layer 320; (2) a roughened contact surface between the dielectric layer 100 and the first semiconductor layer 210; (3) the surface of the pad facing away from the dielectric layer 100 is higher in the first direction Y than the surface of other components of the high-voltage light-emitting diode chip facing away from the dielectric layer 100. Alternatively, the high-voltage light-emitting diode chip provided in this application may include a combination of at least two of the following three features: (1) a second insulating layer 320; (2) a roughened contact surface between the dielectric layer 100 and the first semiconductor layer 210; (3) the surface of the pad facing away from the dielectric layer 100 is higher in the first direction Y than the surface of other components of the high-voltage light-emitting diode chip facing away from the dielectric layer 100. This application does not impose specific limitations on this, and specific design is required according to actual application.

[0048] Based on the same inventive concept, embodiments of this application also provide a chip transfer structure. See details below. Figure 5The diagram shows a schematic of a chip transfer structure provided in an embodiment of this application. The chip transfer structure includes at least two high-voltage light-emitting diode (LED) chips 10 as described in any of the above embodiments, and a temporary substrate 20. The LED chips 10 are fixedly connected to the same side of the temporary substrate 20, and the LED chips 10 are spaced apart. All the LED chips 10 provided in this application are fixedly connected to the same side of the temporary substrate 20, thus facilitating the mass transfer of the LED chips 10. As can be seen from the above, the technical solution provided in this application allows the LED chips 10 to have a micrometer-scale chip structure, and the light-emitting epitaxial layer 200 of the LED chip 10 is located on the dielectric layer 100. This eliminates the need for substrate structures such as sapphire in existing chips, realizing a free-standing, substrate-free micrometer-scale LED chip 10 structure. This avoids the problem of substrate structures limiting chip size, resulting in a simpler and smaller LED chip structure, improving the design flexibility and yield of the LED chip 10, and better meeting market development needs. Furthermore, the high-voltage light-emitting diode chip 10 provided in this application embodiment, in conjunction with a temporary substrate and laser mass transfer technology, is used to prepare a corresponding chip transfer structure, thereby enabling mass transfer of chips and providing users with more diverse choices to meet the market's customized development needs.

[0049] Continue as Figure 5 As shown, the dielectric layer 210 of the high-voltage light-emitting diode chip 10 provided in this application embodiment faces the temporary substrate 10; wherein, the chip transfer structure includes an insulating bonding layer 30 located between the high-voltage light-emitting diode chip 10 and the temporary substrate 20, the insulating bonding layer 30 being used to fix and bond the high-voltage light-emitting diode chip 10 to the temporary substrate 20, thereby realizing a pad-up type (i.e., pads on top) chip transfer structure.

[0050] Or such as Figure 6The diagram shows another chip transfer structure provided in this application embodiment. The first pad 410 and the second pad 420 of the high-voltage LED chip 10 provided in this application embodiment face the temporary substrate 10. The chip transfer structure includes an insulating bonding layer 30 located between the high-voltage LED chip 10 and the temporary substrate 20. The insulating bonding layer 30 is used to fix and bond the high-voltage LED chip 10 to the temporary substrate 20, thereby realizing a pad-down type (i.e., pads on the bottom) chip transfer structure. It can be seen that the chip transfer structure provided in this application embodiment realizes both pad-up and pad-down type structures. By diversifying the design of the chip transfer structure, the flexibility and convenience of the transfer structure are improved.

[0051] In some embodiments, the temporary substrate 20 provided in this application may be made of light-transmitting materials such as Al2O3 or SiO2. Furthermore, the insulating bonding layer 30 provided in this application may be made of organic or inorganic bonding materials, depending on the specific application; this application does not impose any specific limitations on this selection.

[0052] Based on the same inventive concept, this application also provides an electronic device, which includes the high-voltage light-emitting diode chip provided in any of the above embodiments.

[0053] In summary, this application provides a high-voltage light-emitting diode chip, a chip transfer structure, and an electronic device. The high-voltage light-emitting diode chip includes: a dielectric layer; a first light-emitting epitaxial layer to an Nth light-emitting epitaxial layer, all of which are located on one side of the dielectric layer, and each light-emitting epitaxial layer includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially on the dielectric layer, where N is an integer greater than 1; a first insulating layer, which covers the exposed surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, and includes a first cutout area exposing the first semiconductor layer and a second cutout area exposing the second semiconductor layer; a first solder joint; and a first bonding layer. The first pad is located at the first cutout area of ​​the first light-emitting epitaxial layer and is electrically connected to the first semiconductor layer of the first light-emitting epitaxial layer. The second pad is located at the second cutout area of ​​the Nth light-emitting epitaxial layer and is electrically connected to the second semiconductor layer of the Nth light-emitting epitaxial layer. The two ends of the i-th connecting wire are located at the second cutout area of ​​the i-th light-emitting epitaxial layer and the first cutout area of ​​the (i+1)-th light-emitting epitaxial layer, respectively. The i-th connecting wire is electrically connected to the second semiconductor layer of the i-th light-emitting epitaxial layer and the first semiconductor layer of the (i+1)-th light-emitting epitaxial layer, where i is a positive integer less than N.

[0054] As can be seen from the above, the technical solution provided in this application embodiment has the light-emitting epitaxial layer of the high-voltage light-emitting diode chip located on the dielectric layer, thereby eliminating the need for substrate structures such as sapphire in existing chips. This avoids the problem of substrate structures limiting the size of the chip, making the high-voltage light-emitting diode chip simpler in structure and smaller in size, improving the design flexibility and production yield of the high-voltage light-emitting diode chip, and better meeting the needs of market development.

[0055] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0057] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0058] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0059] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0060] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A high-voltage light-emitting diode chip, characterized in that, The high-voltage light-emitting diode chip includes: Dielectric layer; From the first light-emitting epitaxial layer to the Nth light-emitting epitaxial layer, all of them are located on one side of the dielectric layer. Each light-emitting epitaxial layer includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer that are located on the dielectric layer and stacked in sequence. N is an integer greater than 1. A first insulating layer covers the exposed surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, and the first insulating layer includes a first cutout area exposing the first semiconductor layer and a second cutout area exposing the second semiconductor layer. A first pad, a first connecting wire to a (N-1)th connecting wire and a second pad, wherein the first pad is located at the first cutout area of ​​the first light-emitting epitaxial layer and is electrically connected to the first semiconductor layer of the first light-emitting epitaxial layer; the second pad is located at the second cutout area of ​​the Nth light-emitting epitaxial layer and is electrically connected to the second semiconductor layer of the Nth light-emitting epitaxial layer; the two ends of the i-th connecting wire are located at the second cutout area of ​​the i-th light-emitting epitaxial layer and the first cutout area of ​​the (i+1)th light-emitting epitaxial layer, respectively, and the i-th connecting wire is electrically connected to the second semiconductor layer of the i-th light-emitting epitaxial layer and the first semiconductor layer of the (i+1)th light-emitting epitaxial layer, where i is a positive integer less than N.

2. The high-voltage light-emitting diode chip according to claim 1, characterized in that, The high-voltage light-emitting diode chip also includes: A second insulating layer, which at least covers the i-th connecting wire.

3. The high-voltage light-emitting diode chip according to claim 2, characterized in that, The thickness of the second insulating layer is no more than 1.5 micrometers.

4. The high-voltage light-emitting diode chip according to claim 1, characterized in that, The contact surface between the dielectric layer and the first semiconductor layer is a roughened surface.

5. The high-voltage light-emitting diode chip according to claim 1, characterized in that, The thickness of the dielectric layer is not less than 1 micrometer.

6. The high-voltage light-emitting diode chip according to claim 1, characterized in that, The surfaces of the first pad and the second pad facing away from the dielectric layer are higher in a first direction than the surfaces of other components of the high voltage light-emitting diode chip facing away from the dielectric layer. The first direction is the direction from the dielectric layer to the light-emitting epitaxial layer.

7. A chip transfer structure, characterized in that, The chip transfer structure includes: At least two high-voltage light-emitting diode chips as described in any one of claims 1-6; A temporary substrate, wherein the high-voltage light-emitting diode chip is fixedly connected to the same side of the temporary substrate.

8. The chip transfer structure according to claim 7, characterized in that, The dielectric layer of the high-voltage light-emitting diode chip faces the temporary substrate. The chip transfer structure includes an insulating bonding layer located between the high-voltage light-emitting diode chip and the temporary substrate.

9. The chip transfer structure according to claim 7, characterized in that, The first and second pads of the high-voltage light-emitting diode chip face the temporary substrate. The chip transfer structure includes an insulating bonding layer located between the high-voltage light-emitting diode chip and the temporary substrate.

10. An electronic device, characterized in that, The electronic device includes the high-voltage light-emitting diode chip according to any one of claims 1-6.

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