Stacked PXIe interface backboard
By using a stacked PXIe interface backplane design with motherboard and daughterboard, the problem of large size and high cost of traditional PXIe backplanes is solved. This design allows for flexible adaptation to different slot requirements, reduces production and maintenance costs, and is suitable for portable and outdoor applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2026-04-07
AI Technical Summary
Traditional PXIe standard chassis backplanes are bulky and expensive, and cannot flexibly adapt to different peripheral slot requirements, resulting in wasted resources.
It adopts a stacked structure of motherboard and daughterboard, and realizes signal distribution and conversion through PCIe bridge chip, mapping module and serial-to-parallel shift register. Combined with ATX power supply, it reduces costs and improves space utilization.
It achieves flexible adaptation to different slot requirements, saves space and costs, is suitable for portable and outdoor scenarios, and reduces production, testing and maintenance costs.
Smart Images
Figure CN224097995U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of radio frequency microwave test technology, and more specifically, to a stacked PXIe interface backplane. Background Technology
[0002] The PXIe bus standard is derived from the PXI bus standard by adding the PCIe bus, and it is widely used in the field of test and measurement. Compared with benchtop test equipment, modular test equipment using the PXIe bus standard has the advantages of rich variety, customizability, flexibility, high data throughput, and low cost, and is widely accepted and used.
[0003] Traditional PXIe standard chassis backplates have a large number of slots, are bulky, and expensive, making them unsuitable for portable or outdoor applications. Traditional standard PXIe chassis backplates, such as... Figure 1 As shown, its architecture typically consists of system slots, peripheral slots, and an ATX power supply module. The controller on the system slot (usually occupying 3-4 slots) transmits data and control signals to each peripheral slot through a traditional standard PXIe backplane. To meet the needs of most customers (multiple peripheral slots), the entire PXIe backplane must be made very large. This forces users who only need 1, 2, or 3 slots of peripherals to spend more money on chassis with more slots, resulting in a large size and wasted resources to some extent. Utility Model Content
[0004] To address the aforementioned issues, this application provides a stacked PXIe interface backplane.
[0005] This application provides a stacked PXIe interface backplane using the following technical solution:
[0006] A stacked PXIe interface backplane includes at least one motherboard and several daughterboards. The motherboard is used to distribute PCIe bus signals and clock signals, and the daughterboards are used to convert PCIe bus signals and clock signals. The motherboard includes a power supply unit, a clock unit, a signal distribution unit, and PXIe connectors. Each daughterboard includes a PXIe connector, and all PXIe connectors include XJ3 / XJ4 interfaces. FMC connectors are provided at corresponding positions on the top and bottom layers of the motherboard and daughterboards. The signal distribution unit includes a PCIe bridge, a mapping module, and a serial-to-parallel shift register. The top and bottom FMC connectors on the same daughterboard are staggered through the mapping module. The PXIe connector slots of the motherboard and several daughterboards are cascaded through the serial-to-parallel shift register.
[0007] Furthermore, the power supply unit includes a power connector, a protection circuit, and a filtering circuit.
[0008] Furthermore, the power connector is an ATX power connector.
[0009] Furthermore, the clock unit includes a local oscillator clock circuit and a clock management chip.
[0010] Furthermore, the clock management chip is an HMC7044.
[0011] Furthermore, the serial-to-parallel shift register is a 74HC595.
[0012] In summary, this application includes at least one of the following beneficial technical effects:
[0013] This application utilizes a motherboard + daughterboard stacking approach to address the inflexibility of traditional peripheral slots. Besides being compatible with the standard PXIe, it allows for various slot configurations to be implemented according to user needs, significantly saving overall space and cost. It provides a novel solution for outdoor or portable applications using the PXIe standard interface. Due to the product's flexibility and wide range of applications, users can begin mass production in one go, thereby reducing production, testing, and maintenance costs. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the back panel of a traditional PXIe chassis.
[0015] Figure 2 This is a schematic diagram of the structure of the motherboard of this application;
[0016] Figure 3 This is a schematic diagram of the structure of the sub-board in this application;
[0017] Figure 4 This is a schematic diagram of the connection of the stacked backplate;
[0018] Figure 5 A schematic diagram of the signal mapping logic for a stacked backplane;
[0019] Figure 6 Here is the logic block diagram for 74HC595;
[0020] Figure 7 The schematic and timing diagram for 7HC595 are provided.
[0021] Figure 8 A schematic diagram of a 74HC595 daisy chain;
[0022] Figure 9 This is a schematic diagram of PCIe bridging;
[0023] Figure 10 Apply a truth table to 74HC595. Detailed Implementation
[0024] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0025] In the description of this application, it should be noted that the terms "upper," "lower," "inner," "outer," "top / bottom," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0026] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed," "equipped with," "sleeved / connected," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0027] Example 1:
[0028] The present application will be further described in detail below with reference to the accompanying drawings.
[0029] This application discloses a stacked PXIe interface backplane, including at least one motherboard and several daughterboards. The motherboard is used to distribute PCIe bus signals and clock signals, and the daughterboards are used to convert PCIe bus signals and clock signals. The motherboard includes a power supply unit, a clock unit, a signal distribution unit, and PXIe connectors. Each daughterboard includes a PXIe connector, and all PXIe connectors include XJ3 / XJ4 interfaces. FMC connectors are provided at corresponding positions on the top and bottom layers of the motherboard and daughterboards. The signal distribution unit includes a PCIe bridge, a mapping module, and a serial-to-parallel shift register. The top and bottom FMC connectors on the same daughterboard are staggered through the mapping module. The PXIe connector slots of the motherboard and several daughterboards are cascaded through the serial-to-parallel shift register.
[0030] Preferably, the power supply unit includes a power connector, a protection circuit, and a filtering circuit, wherein the power connector is an ATX power connector.
[0031] Preferably, the clock unit includes a local oscillator clock circuit and a clock management chip, wherein the clock management chip is an HMC7044.
[0032] Preferably, the serial-to-parallel shift register is a 74HC595.
[0033] The implementation principle of a stacked PXIe interface backplane in this application embodiment is as follows:
[0034] Motherboard (see) Figure 2 The main function of the PXIe daughterboard is to distribute PCIe bus signals and clock signals. Figure 3 This component primarily handles the conversion of PCIe bus and clock signals. Due to the large number of signals, the more flexible FMC connector is used for signal stacking. All daughterboards employ a unified design to facilitate subsequent mass production and reduce unit cost. See the overall structure diagram below. Figure 4 .
[0035] The complete system mainly consists of the power supply section (ATX power supply directly supplied, not shown in the figure, and will not be described in detail), the clock section, and the signal distribution section (including PCIe SW bridge and signal control).
[0036] The power supply uses an ATX power supply to directly power the entire system. 12V, 3.3V, and other power supplies pass through the ATX power connector and protection and filtering circuits before directly entering the motherboard's FMC connector and PXIe connector (e.g., ...). Figure 2 (As shown in red). The motherboard FMC connector then connects to the corresponding daughterboard bottom-level FMC connector, which in turn supplies power to the top-level FMC connector and PXIe connector (e.g., ...). Figure 3 (As shown in red), and the other sub-boards follow the same pattern.
[0037] The clock section is similar to that of a traditional standard PXIe chassis. The local oscillator clock is generated by the motherboard, then passes through the clock management chip (HMC7044) to output various required clock signals (such as PXIe_CLK100, PXIe_SYNC100, PXIe_CLK10, etc.). These signals are then transmitted to the various daughterboards (i.e., peripheral slots) via the motherboard's FMC connector.
[0038] In this design, the signal allocation part includes PCIe allocation, signal relationship mapping of each slot, and slot address implementation.
[0039] PCIe allocation is similar to that of traditional PXIe chassis architectures, using a dedicated PCIe bridge for allocation. The PCIe input from the motherboard is distributed through the bridge to multiple PCIe bus signals for communication on various daughterboards. A schematic diagram of the PCIe bridging is shown below. Figure 9 .
[0040] Because of the stacking approach, the traditional one-to-one mapping is no longer applicable in this design. To ensure complete consistency of bus interfaces of the same type, a 'misaligned' mapping method is used for interface definition on the FMC connectors. The motherboard is located at the bottom layer of the entire architecture (i.e., only one FMC is needed at the top layer). There is one FMC connector at the top layer and one at the bottom layer of the daughterboard. The bottom FMC connector transmits signals from the motherboard or the top layer of the previous daughterboard to the PXIe connector and the top FMC connector. The bus signal definition of the bottom FMC connector undergoes a 'shift' operation when connected to the top FMC. Taking a 4-slot chassis as an example (multiple slots can be expanded in the same way, mainly depending on the number of PCIe interfaces brought out by the motherboard), its signal architecture is shown in the diagram below. Figure 5 This allows all bus signals to be transmitted sequentially to each peripheral slot while ensuring that all daughterboards are identical, reducing production and labor costs.
[0041] It should be noted that, Figure 5 This misaligned mapping relationship allows for the sequential transmission of signals of the same type across different slots. The green portion represents the signal transmitted to the XJ4 connector each time, while the red text below indicates the 'real' signal network name for subsequent transmissions.
[0042] Due to the consistency of all daughterboards (corresponding peripheral slots), the GA[0:4] address signal cannot be used to determine the slot address in the traditional way of using pull-up / pull-down resistors. Since the address of each peripheral slot basically increases or decreases sequentially, it is considered to use a serial-to-parallel shift register (74HC595BQ) in a cascaded manner to confirm the GA[0:4] address signal of the PXIe chassis. The 74HC595BQ mainly consists of various flip-flops and BUFs; its logic block diagram is shown below. Figure 6 Based on the above application requirements, the circuit design is as follows: Figure 7 .
[0043] The motherboard transmits the GACLK signal directly to each daughterboard via the FMC connector, while the GADAT_IN signal, after being output from the motherboard's FMC, is transmitted to each daughterboard via a daisy chain. The daisy chain transmission block diagram is shown below. Figure 8 Combining Figure 7 The timing diagram, and the truth table results corresponding to the data information being a one-cycle pulse, are shown below. Figure 10This table allows for the accumulation of addresses for different slots on the same daughterboard.
[0044] It should be noted that, in Figure 10 The truth table in the table is derived from the manual and our actual application scenario. The table mainly introduces the situation of the three-level peripheral slots. The others are similar. Due to the special architecture of the shift register, when CLK_IN stops (i.e., does not oscillate), the subsequent data will maintain the original state. That is, when the input clock stops oscillating after the 19th cycle, GA[0:4] = 00000 on SLOT 1; GA[0:4] = 00001 on SLOT 2; GA[0:4] = 00010 on SLOT 2, thus realizing the determination of the slot and accumulation.
[0045] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. A stacked PXIe interface backplane, characterized in that, The system includes at least one motherboard and several daughterboards. The motherboard is used to distribute PCIe bus signals and clock signals, and the daughterboards are used to convert PCIe bus signals and clock signals. The motherboard includes a power supply unit, a clock unit, a signal distribution unit, and a PXIe connector. Each daughterboard includes a PXIe connector, and all PXIe connectors include XJ3 / XJ4 interfaces. FMC connectors are provided at corresponding positions on the top and bottom layers of the motherboard and the daughterboards. The signal distribution unit includes a PCIe bridge, a mapping module, and a serial-to-parallel shift register. The top and bottom FMC connectors on the same daughterboard are staggered through the mapping module. The PXIe connector slots of the motherboard and the daughterboards are cascaded through the serial-to-parallel shift register.
2. The stacked PXIe interface backplane according to claim 1, characterized in that: The power supply unit includes a power connector, a protection circuit, and a filtering circuit.
3. A stacked PXIe interface backplane according to claim 2, characterized in that: The power connector is an ATX power connector.
4. A stacked PXIe interface backplane according to claim 1, characterized in that: The clock unit includes a local oscillator clock circuit and a clock management chip.
5. A stacked PXIe interface backplane according to claim 4, characterized in that: The clock management chip is HMC7044.
6. A stacked PXIe interface backplane according to claim 1, characterized in that: The serial-to-parallel shift register is a 74HC595.