Low-voltage reset circuit
By combining a branch structure composed of PMOS and NMOS transistors with an inverter, the problems of large area, high power consumption, and inaccurate reset in low-power systems are solved. This results in a low-power, high-interference-resistant low-voltage reset circuit suitable for 1.5V power supply systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WUXI CHIP PLUS INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2025-03-28
- Publication Date
- 2026-04-10
AI Technical Summary
Existing low-voltage reset circuits have problems such as large area and power consumption, inaccurate reset voltage point, and insufficient anti-interference capability in low-power systems.
The circuit structure consists of PMOS and NMOS transistors, combined with an inverter. Low voltage detection is achieved by the change in current flowing into the PMOS transistor. Accurate low voltage reset is achieved by using the NMOS transistor branch with stable bias voltage and the inverter. The Widlar current source bias circuit and startup circuit are combined to reduce power consumption and improve accuracy.
It achieves low-voltage reset with low power consumption, simple structure and strong anti-interference capability. The reset voltage point is accurate, the power consumption is less than 0.26uW, the temperature effect is less than 10%, and it is suitable for 1.5V power supply systems.
Smart Images
Figure CN224111155U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to low pressure detection technical field, concretely relates to a low voltage reset circuit. BACKGROUND
[0002] 1.5V button cell is widely used in various low power consumption field handheld electronic equipment such as consumer electronics calculator, electronic caliper and medical equipment class thermometer because of its voltage stability, small size and strong reliability etc.
[0003] In the normal operation of the chip system of handheld electronic equipment, the power supply voltage can suddenly drop due to power supply noise or load change, which can cause short-term fluctuations in the circuit and even cause system operation errors. Therefore, in order to ensure the normal operation of the system, a low voltage reset signal is required to reset the system when the power supply voltage suddenly drops. For low power consumption systems, the low voltage reset module needs to meet the requirements of accurate detection of reset point, not sensitive to process voltage and temperature changes, strong anti-interference ability and low power consumption.
[0004] The existing low voltage reset circuit mainly has the following two structures, the first is to use the low voltage reset circuit of band gap reference and voltage comparator technology, which is less affected by voltage and temperature change, usually has accurate reset voltage point, but its area and power consumption are relatively large, so it is not suitable for low power consumption system;
[0005] The second is a low voltage reset circuit based on RC charging principle, and the reset voltage of the circuit is not as accurate as the value based on band gap reference technology. CONTENT OF THE UTILITY MODEL
[0006] In view of the deficiencies of the background art, the utility model provides a low voltage reset circuit with low area and power consumption and accurate reset voltage point.
[0007] To solve the above technical problems, the utility model provides the following technical scheme: a low voltage reset circuit, comprising a first branch formed by at least two first PMOS tubes in series, a second branch formed by at least two first NMOS tubes in series, an inverter INV1 and an inverter INV2;
[0008] The input end of the first branch is used for inputting power supply voltage, the gate of all first PMOS tubes is grounded, the output end of the first branch is electrically connected with the input end of the second branch and the input end of the inverter INV1 respectively, the output end of the inverter INV1 is electrically connected with the input end of the inverter INV2, and the output end of the inverter INV2 is used for outputting reset signal;
[0009] The output end of the second branch is grounded, and the gate of all first NMOS tubes is used for inputting bias voltage.
[0010] In some embodiments, the second branch includes three first NMOS tubes in series.
[0011] In some embodiments, the output end of the inverter INV1 is further electrically connected to the gate of a second NMOS tube, and the drain and the source of the second NMOS tube are respectively electrically connected to the drain and the source of a first NMOS tube at the tail of the second branch.
[0012] In some embodiments, the channel length of each first PMOS tube is greater than the channel width thereof, and the channel length of each first NMOS tube is greater than the channel width thereof.
[0013] In some embodiments, the utility model further includes a bias voltage generating circuit, which is used for inputting a bias voltage to the gate of the first NMOS tube.
[0014] In some embodiments, the bias voltage generating circuit includes a resistor R1, a MOS tube M4, a MOS tube M5, a MOS tube M6, a MOS tube M7 and a MOS tube M8.
[0015] The source of the MOS tube M4 is electrically connected to the source of the MOS tube M5 and the source of the MOS tube M6, and is used for inputting a power voltage.
[0016] The gate of the MOS tube M5 is electrically connected to the gate of the MOS tube M6, the drain of the MOS tube M5 and the drain of the MOS tube M7.
[0017] The drain of the MOS tube M6 is electrically connected to the drain of the MOS tube M8, the gate of the MOS tube M8, the gate of the MOS tube M7 and the drain of the MOS tube M4, and is used for outputting the bias voltage.
[0018] The source of the MOS tube M8 is grounded, the source of the MOS tube M7 is grounded through the resistor R1, and the gate of the MOS tube M4 is used for inputting a starting voltage.
[0019] In some embodiments, the MOS tube M4, the MOS tube M5 and the MOS tube M6 are all PMOS tubes, and the MOS tube M7 and the MOS tube M8 are all NMOS tubes.
[0020] In some embodiments, the utility model further includes a starting circuit, which provides a starting voltage to the gate of the MOS tube M4 for a predetermined time when a power voltage is connected.
[0021] In some embodiments, the starting circuit includes a MOS tube M1, a MOS tube M2, a MOS tube M3 and an inverter INV3.
[0022] The source of the MOS transistor M1 is used to connect to the power supply voltage. The drain of the MOS transistor M1 is electrically connected to the source of the MOS transistor M2. The drain of the MOS transistor M2 is electrically connected to the input terminal of the inverter INV3 and the drain of the MOS transistor M3, respectively. The source of the MOS transistor M3 is grounded. The output terminal of the inverter INV3 outputs the start-up voltage.
[0023] The gates of MOS transistors M1, M2, and M3 are electrically connected to the gate of MOS transistor M7, respectively.
[0024] In one embodiment, MOS transistors M1 and M2 are both PMOS transistors, and MOS transistor M3 is an NMOS transistor.
[0025] The advantages of this invention compared to the prior art are as follows: For the first and second branches of this invention, since the bias voltage of the gate input of the first NMOS transistor in the second branch remains unchanged, the current flowing through the first NMOS transistor remains unchanged. When the power supply voltage decreases, the current flowing through the first branch decreases, and the voltage input to the inverter INV1 decreases. When the voltage input to the inverter INV1 decreases, causing the output of the inverter IVN1 to reverse, the inverter INV2 outputs a low-level reset signal, thereby completing the low-voltage detection reset. The entire structure consists of a MOS transistor and an inverter, which is simple in structure and has low power consumption. Moreover, the low-voltage detection is achieved by changing the current flowing into the PMOS transistor, which is less affected by external factors and makes the detection more accurate. Attached Figure Description
[0026] Figure 1 This is a circuit diagram of the present invention as shown in the embodiments. Detailed Implementation
[0027] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.
[0028] like Figure 1 As shown, a low-voltage reset circuit includes a first branch 1 formed by two first PMOS transistors connected in series, a second branch 2 formed by three first NMOS transistors connected in series, an inverter INV1, and an inverter INV2; wherein the two first PMOS transistors are MOS transistors M9 and M10; and the three first NMOS transistors are MOS transistors M11, M12, and M13; in a certain embodiment, the number of first PMOS transistors in the first branch 1 and the number of first NMOS transistors in the second branch 2 can be set according to actual needs, and is not limited here.
[0029] Specifically, in the embodiment, the input end of the first branch 1 is used for inputting a power supply voltage, wherein the power supply voltage can be an external battery voltage, the gates of all the first PMOS tubes are grounded, the output end of the first branch 1 is electrically connected with the input end of the second branch 2 and the input end of the inverter INV1 respectively, the output end of the inverter INV1 is electrically connected with the input end of the inverter INV2, and the output end of the inverter INV2 is used for outputting a reset signal.
[0030] The output end of the second branch 2 is grounded, and the gates of all the first NMOS tubes are used for inputting a bias voltage.
[0031] In actual use, for the first branch 1 and the second branch 2 of the utility model, since the bias voltage inputted by the gates of the first NMOS tubes of the second branch 2 is constant, the current flowing through the first NMOS tubes is constant; when the power supply voltage is reduced, the current flowing through the first branch 1 is reduced, at this time, the voltage inputted to the inverter INV1 is reduced, when the voltage inputted to the inverter INV1 is reduced to make the output of the inverter IVN1 reverse, the inverter INV2 outputs a low-level reset signal, so as to complete low-voltage detection reset, the whole structure is composed of MOS tubes and inverters, the structure is simple and the power consumption is low, and the low-voltage detection is realized by the current flowing into the PMOS tube, the influence of the external environment is small, and the detection is more accurate.
[0032] Specifically, in the embodiment, the output end of the inverter INV1 is also electrically connected with the gate of the second NMOS tube M14, the drain and the source of the second NMOS tube M14 are electrically connected with the drain and the source of the MOS tube M13 in the tail of the second branch 2, respectively. Figure 1
[0033] In the embodiment, the function of the second NMOS tube M14 is described in combination with the working process of the circuit, and the specific process is as follows:
[0034] When the power supply voltage gradually decreases from the normal potential, the current after the conduction of the first branch 1 begins to gradually decrease, because after the power supply voltage is reduced, the VGS voltage of the first PMOS tube is small, and the gate potential of the first NMOS tube comes from the bias voltage irrelevant to the power supply, and the conduction current of the second branch 2 is constant;
[0035] When the power voltage continuously decreases, the current after the first branch 1 is turned on gradually becomes smaller, the voltage V4 gradually becomes smaller, and finally the voltage V5 output by the inverter INV1 flips to high level, the second NMOS tube M14 is turned on and is parallel to the MOS tube M13, the current after the second branch 2 is turned on is strengthened, the voltage V4 becomes lower, and the positive feedback effect is achieved; and due to the existence of the positive feedback, the hysteresis effect is achieved, so that the reset voltage point and the reset release voltage point are separated, and the reset release voltage point is higher than the reset voltage point, and finally the effect of more stable circuit is achieved; the voltage V5 is input to the inverter INV2, the voltage output by the inverter INV2 flips to low level, the low level is sent to the chip system control circuit, and finally the overall circuit is reset;
[0036] After the chip power voltage is reset to low voltage, the current after the first branch 1 is turned on becomes larger, until the current after the second branch 2 is turned on, the voltage V4 rises, the voltage V5 output by the inverter INV1 flips to low level, the second NMOS tube M14 becomes a cut-off state, the current after the second branch 2 is turned on is weakened, the voltage V4 becomes higher, the positive feedback effect is achieved, and the reset voltage point is effectively lower than the reset release voltage point. The voltage V5 is input to the inverter INV2, the voltage output by the inverter INV2 flips to high level and is sent to the chip system control circuit, and finally the overall circuit is reset and released to restore normal work.
[0037] In the embodiment, in order to further reduce power consumption, the channel length of each first PMOS tube is greater than the channel width thereof, and the channel length of each first NMOS tube is greater than the channel width thereof.
[0038] In the embodiment, as shown in Figure 1 The utility model further includes a bias voltage generating circuit 3 for inputting a bias voltage to the gate of the first NMOS tube.
[0039] The bias voltage generating circuit 3 includes a resistor R1, MOS tubes M4, M5, M6, M7 and M8.
[0040] The source of the MOS tube M4 is electrically connected to the source of the MOS tube M5 and the source of the MOS tube M6, for inputting a power voltage.
[0041] The gate of the MOS tube M5 is electrically connected to the gate of the MOS tube M6, the drain of the MOS tube M5 and the drain of the MOS tube M7.
[0042] The drain of the MOS tube M6 is electrically connected to the drain of the MOS tube M8, the gate of the MOS tube M8, the gate of the MOS tube M7 and the drain of the MOS tube M4, for outputting a bias voltage.
[0043] The source of MOSFET M8 is grounded; the source of MOSFET M7 is grounded through resistor R1; the gate of MOSFET M4 is used to input the startup voltage.
[0044] In addition, MOSFETs M4, M5, and M6 are all PMOS transistors, while MOSFETs M7 and M8 are both NMOS transistors.
[0045] for Figure 1 In the bias voltage generation circuit 3, MOSFETs M5 and M6 form a current mirror, and MOSFETs M7 and M8 form a current mirror.
[0046] Since the bias voltage generating circuit 4 in this embodiment is a Widlar current source bias circuit, there is a degeneracy point, so it is necessary to eliminate the degeneracy point. In this embodiment, the present invention also includes a startup circuit 4, which provides a startup voltage for a predetermined time to the gate of the MOS transistor M4 when the power supply voltage is applied, thereby eliminating the degeneracy point.
[0047] exist Figure 1 In the circuit, the startup circuit 4 includes MOSFETs M1, M2, and M3, and inverter INV3;
[0048] The source of MOSFET M1 is connected to the power supply voltage. The drain of MOSFET M1 is electrically connected to the source of MOSFET M2. The drain of MOSFET M2 is electrically connected to the input terminal of inverter INV3 and the drain of MOSFET M3 respectively. The source of MOSFET M3 is grounded. The output terminal of inverter INV3 outputs the start-up voltage.
[0049] The gates of MOSFET M1, MOSFET M2, and MOSFET M3 are electrically connected to the gate of MOSFET M7, respectively.
[0050] In addition, MOSFETs M1 and M2 are both PMOS transistors, while MOSFET M3 is an NMOS transistor.
[0051] In actual use, when power is first applied, voltage V2 is at a low potential, causing MOSFETs M1 and M2 to conduct and charge node V1. Once charged to a certain potential, the voltage V3 output by inverter INV3 becomes low, causing MOSFET M4 to conduct and raising the gate voltages of MOSFETs M7 and M8, breaking the zero current degeneracy point state. The entire bias voltage generation circuit 3 then starts working. At the same time, the gate potential of MOSFET M3 increases, turning on MOSFET M3 and rapidly pulling the voltage of node V1 down. The output voltage V3 of inverter INV3 then becomes high, turning off the power-on circuit.
[0052] In combination with actual use, the low-voltage reset circuit in the embodiment can be applied to a 1.5V power supply working system, the reset point is 0.75V, the reset release point is 0.85V, and the power consumption is 0.26uW. In the range of-30 degrees Celsius to 100 degrees Celsius, the reset voltage is less than 10% affected by temperature
[0053] According to the above disclosure, the related personnel can make various changes and modifications without deviating from the technical idea of the present application. The technical scope of the present application is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims
1. A low voltage reset circuit, characterized by, The first branch includes at least two first PMOS transistors connected in series, the second branch includes at least two first NMOS transistors connected in series, an inverter INV1 and an inverter INV2; The input end of the first branch is used for inputting a power supply voltage, the gates of all the first PMOS transistors are grounded, the output end of the first branch is electrically connected with the input end of the second branch and the input end of the inverter INV1 respectively, the output end of the inverter INV1 is electrically connected with the input end of the inverter INV2, and the output end of the inverter INV2 is used for outputting a reset signal; The output end of the second branch is grounded, and the gates of all the first NMOS transistors are used for inputting a bias voltage.
2. A low voltage reset circuit according to claim 1, wherein The second branch includes three first NMOS transistors connected in series.
3. The low voltage reset circuit of claim 1, wherein: The output end of the inverter INV1 is also electrically connected with the gate of a second NMOS transistor, and the drain and source of the second NMOS transistor are electrically connected with the drain and source of a tail first NMOS transistor in the second branch respectively.
4. The low voltage reset circuit of claim 1, wherein, The channel length of each first PMOS transistor is greater than the channel width thereof, and the channel length of each first NMOS transistor is greater than the channel width thereof.
5. A low voltage reset circuit according to any one of claims 1 to 4, characterized in that The bias voltage generating circuit is also used for inputting a bias voltage to the gate of the first NMOS transistor.
6. A low voltage reset circuit as claimed in claim 5, characterized in that The bias voltage generating circuit includes a resistor R1, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7 and a MOS transistor M8. The source of the MOS transistor M4 is electrically connected with the source of the MOS transistor M5 and the source of the MOS transistor M6 respectively, and is used for inputting a power supply voltage. The gate of the MOS transistor M5 is electrically connected with the gate of the MOS transistor M6, the drain of the MOS transistor M5 and the drain of the MOS transistor M7 respectively. The drain of the MOS transistor M6 is electrically connected with the drain of the MOS transistor M8, the gate of the MOS transistor M8, the gate of the MOS transistor M7 and the drain of the MOS transistor M4 respectively, and is used for outputting the bias voltage. The source of the MOS transistor M8 is grounded, the source of the MOS transistor M7 is grounded through the resistor R1, and the gate of the MOS transistor M4 is used for inputting a start-up voltage.
7. A low voltage reset circuit as claimed in claim 6, characterized in that The MOS transistor M4, the MOS transistor M5 and the MOS transistor M6 are all PMOS transistors, and the MOS transistor M7 and the MOS transistor M8 are all NMOS transistors.
8. A low voltage reset circuit as claimed in claim 6, characterized in that The start-up circuit provides a predetermined time start-up voltage to the gate of the MOS transistor M4 when the power supply voltage is connected.
9. A low voltage reset circuit as claimed in claim 8, characterized in that The start-up circuit includes a MOS transistor M1, a MOS transistor M2, a MOS transistor M3 and an inverter INV3. The source of the MOS transistor M1 is used for connecting the power supply voltage, the drain of the MOS transistor M1 is electrically connected with the source of the MOS transistor M2, the drain of the MOS transistor M2 is electrically connected with the input end of the inverter INV3 and the drain of the MOS transistor M3 respectively, the source of the MOS transistor M3 is grounded, and the output end of the inverter INV3 outputs the start-up voltage. The gate of the MOS transistor M1, the gate of the MOS transistor M2 and the gate of the MOS transistor M3 are electrically connected with the gate of the MOS transistor M7 respectively.
10. A low voltage reset circuit as claimed in claim 9, characterized in that The MOS transistor M1 and the MOS transistor M2 are PMOS transistors, and the MOS transistor M3 is an NMOS transistor. The MOS transistor M1 and the MOS transistor M2 are PMOS transistors, and the MOS transistor M3 is an NMOS transistor.