Substrate structure
By adjusting the design of the insulating protective layer within the die-placement area of the substrate structure, the exposed area of the patterned metal layer is reduced, thus solving the problem of poor bonding between the base adhesive and the circuit layer and improving the reliability of the packaging structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SILICONWARE PRECISION IND CO LTD
- Filing Date
- 2025-02-25
- Publication Date
- 2026-04-10
AI Technical Summary
In existing flip-chip packaging structures, the bonding force between the adhesive and the circuit layer in the die-placement area is poor, which can easily lead to delamination problems.
Reduce the area of the patterned metal layer in the opening of the insulating protective layer in the die placement area of the substrate structure. This can be achieved by designing with fine metal lines, slots, or grids, and adding insulating blocks in the openings. This ensures that the area ratio of the exposed circuit layer and the patterned metal layer is 45%-55%, thereby reducing the contact area between the adhesive and the copper.
It effectively improves the adhesion between the adhesive and the substrate, reduces the risk of delamination, and enhances the reliability of the packaging structure.
Smart Images
Figure CN224111623U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor structure, in particular to a substrate structure for carrying electronic components. BACKGROUND
[0002] With the development of electronic industry, the electronic products nowadays tend to be designed in the direction of light, thin, short and small with diversified functions, and the semiconductor packaging technology also develops different packaging patterns. In order to meet the requirements of high integration and miniaturization of semiconductor devices, the flip chip packaging structure is widely used in the industry.
[0003] FIG. 1A and FIG. 1B are respectively a cross-sectional view and a partial top view of a conventional flip chip package 1. As shown in FIG. 1A , a packaging substrate 10 has a circuit layer 100 composed of copper lines, an insulating protective layer 101 and an opening 102 exposing the circuit layer 100, wherein the packaging substrate 10 defines a die area D. A semiconductor chip 11 is combined to the circuit layer 100 in the die area D of the packaging substrate 10 through a plurality of solder bumps 12, and a underfill 13 is formed between the semiconductor chip 11 and the packaging substrate 10 to cover the plurality of solder bumps 12, wherein the circuit layer 100 includes electrical contacts (solder pads) electrically connected to the semiconductor chip and large-area metal layers (copper layers) providing power / ground functions.
[0004] However, the underfill 13 and the circuit layer 100 in the die area D have poor bonding force due to large-area contact, which easily leads to delamination problem, and thus the underfill 13 and the packaging substrate 10 are also easily separated.
[0005] Therefore, how to overcome the above problems of the prior art has become an urgent issue to be solved in the industry. CONTENT OF THE INVENTION
[0006] The present application provides a substrate structure, comprising a substrate body having a circuit layer disposed on one surface thereof and defining a die area on the surface; a patterned metal layer disposed on the surface; and an insulating protective layer disposed on the surface and having an opening corresponding to the die area and exposing part of the circuit layer and part of the patterned metal layer, wherein the area of the circuit layer and the patterned metal layer exposed by the opening accounts for 45% to 55% of the area of the opening.
[0007] The substrate body of the substrate structure as described above is a substrate with a core layer or a substrate without a core layer.
[0008] The substrate structure as aforementioned, the circuit layer comprises a plurality of electrical contact pads and a plurality of conductive traces connecting the plurality of electrical contact pads.
[0009] The substrate structure as aforementioned, the patterned metal layer is used for providing power / ground.
[0010] The substrate structure as aforementioned, the patterned metal layer comprises a plurality of metal blocks and a plurality of metal lines connecting at least two of the plurality of metal blocks.
[0011] The substrate structure as aforementioned, the patterned metal layer comprises a large-area metal layer and a plurality of slots formed in the large-area metal layer, so as to expose the plurality of slots outside the substrate body. The shape of the slots can be square, circular, oval, or irregular.
[0012] The substrate structure as aforementioned, the patterned metal layer comprises a grid metal line. The patterned metal layer further comprises a metal block connecting the grid metal line.
[0013] The substrate structure as aforementioned, the insulating protective layer further comprises a plurality of insulating blocks in the crystal placement area inside the opening. The plurality of insulating blocks are spaced apart from each other, and the shape of the insulating blocks can be circular, square, or irregular.
[0014] In summary, the substrate structure of the present application effectively reduces the ratio of exposed copper (circuit layer and patterned metal layer) by reducing the area of the patterned metal layer exposed outside the opening of the insulating protective layer (for example, the patterned metal layer is in the form of a thin metal line, a slot, a grid, or a plurality of insulating blocks are added inside the opening), so that the area of the circuit layer and the patterned metal layer exposed outside the opening accounts for about 45%-55% of the area of the opening, thereby reducing the contact area between the underfill and the copper, and improving the delamination problem. BRIEF DESCRIPTION OF DRAWINGS
[0015] FIG. 1A and FIG. 1B are respectively a cross-sectional view and a partial top view of a conventional flip-chip package structure.
[0016] FIG. 2A to FIG. 2C is a top view of a first embodiment of the substrate structure of the present application.
[0017] FIG. 3 is a top view of a second embodiment of the substrate structure of the present application.
[0018] REFERENCE NUMERALS
[0019] 1 flip-chip package
[0020] 10 package substrate
[0021] 100 circuit layer
[0022] 101 insulating protective layer
[0023] 102 opening
[0024] 11 semiconductor chip
[0025] 12 solder bump
[0026] 13 underfill
[0027] 2 substrate structure
[0028] 20 substrate body
[0029] 200 surface
[0030] 201 circuit layer
[0031] 201a electrically conductive contact pad
[0032] 201b electrically conductive trace
[0033] 21 patterned metal layer
[0034] 211 metal block
[0035] 212 metal line
[0036] 213 large-area metal layer
[0037] 214 slot
[0038] 215 grid metal line
[0039] 216 metal block
[0040] 22 insulating protective layer
[0041] 220 opening
[0042] 221 insulating block
[0043] D die attach area DETAILED DESCRIPTION
[0044] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is
[0045] It is to be understood that the structures, proportions, sizes, etc. shown in the drawings accompanying the present disclosure are merely intended to facilitate the understanding of the present disclosure and are not intended to limit the scope of the present application. Any modification, change in proportion or adjustment in size that does not affect the function and purpose of the present application should still fall within the scope of the present disclosure. Meanwhile, the terms such as "upper" and "one" used in the present disclosure are merely for the convenience of description and do not limit the scope of the present application. Any change in relative relationship or adjustment without substantial change in technical content is also considered within the scope of the present application.
[0046] Please refer to FIG. 2A to FIG. 2C The present application is a top view schematic diagram of a first embodiment of a substrate structure 2.
[0047] The substrate structure 2 of the present application, for example, is a package substrate for carrying a semiconductor chip, which includes a substrate body 20, a patterned metal layer 21 and an insulating protective layer 22.
[0048] The substrate body 20, for example, is a substrate with a core or a coreless substrate, which is provided with a circuit layer 201 on a surface 200 thereof and defines a die area D on the surface 200.
[0049] In the present embodiment, the substrate body 20 includes an insulating layer and a wiring layer (not shown) formed on the insulating layer, which may, for example, be a fan-out type redistribution layer (RDL) to take the outermost wiring layer as the circuit layer 201. The circuit layer 201 includes a plurality of electrical contact pads 201a and a plurality of conductive traces 201b connecting the plurality of electrical contact pads 201a. The die area D is used for disposing electronic components such as semiconductor chips or passive components thereon, for example, by disposing the electronic components on the electrical contact pads 201a via conductive bumps to form an electronic package.
[0050] Further, the material forming the wiring layer is copper, and the insulating layer is, for example, a dielectric material such as Polybenzoxazole (PBO), Polyimide (PI), Prepreg (PP), etc.
[0051] The patterned metal layer 21 is disposed on the surface 200 of the substrate body 20 and adjacent to the circuit layer 201, wherein the patterned metal layer 21 is designed to provide power / ground usage.
[0052] In one embodiment, as shown in FIG. 1, the patterned metal layer 21 comprises a plurality of metal blocks 211 and a plurality of metal lines (thin lines) 212 connecting at least two of the plurality of metal blocks 211. FIG. 2A
[0053] In another embodiment, as shown in FIG. 2, the patterned metal layer 21 comprises a large-area metal layer 213 and a plurality of slots 214 formed in the large-area metal layer 213. The plurality of slots 214 are exposed outside the substrate body 20. Each of the plurality of slots 214 can be square, circular, or elliptical, or can be designed in a suitable shape (e.g., irregular shape) according to actual conditions. FIG. 2B
[0054] In yet another embodiment, as shown in FIG. 3, the patterned metal layer 21 comprises a grid metal line 215. In addition, the patterned metal layer 21 further comprises a metal block 216 connecting the grid metal line 215. FIG. 2C
[0055] The insulating protective layer 22 is disposed on the surface 200 of the substrate body 20 and has at least one opening 220. In the present embodiment, the opening 220 corresponds to the die area D and exposes part of the line layer 201 and part of the patterned metal layer 21. A portion of the opening 220 is located in the die area D, and the remaining portion is located outside the die area D. The opening 220 located outside the die area D allows the underfill to effectively flow between the electronic component and the substrate body 20. In addition, the material of the insulating protective layer 22 can be, for example, a solder mask material such as green paint or ink.
[0056] The substrate structure 2 in the present embodiment mainly reduces the area of the patterned metal layer 21 exposed outside the opening 220 (full-window type) of the insulating protective layer 22, so that the area (metal material area) of the line layer 201 and the patterned metal layer 21 exposed outside the opening 220 accounts for about 45%-55% of the area of the opening 220, thereby solving the problem that the greater the exposed copper area, the worse the underfill and copper bonding when a large-area metal layer (copper layer) is exposed outside the full window of the existing substrate structure.
[0057] Referring to FIG. 3 FIG. 4 is a top view of a second embodiment of the substrate structure 2 of the present application.
[0058] The substrate structure 2 of the present embodiment is substantially the same as the substrate structure 2 of the foregoing embodiments, and comprises a substrate body 20, a patterned metal layer 21, and an insulating protective layer 22. The main difference is that the insulating protective layer 22 further comprises a plurality of insulating blocks 221 located in the die area D inside the opening 220.
[0059] The plurality of insulating blocks 221 covers part of the patterned metal layer 21 to reduce the area of the patterned metal layer 21 exposed to the opening 220. Furthermore, the plurality of insulating blocks 221 are spaced apart from each other, and can have a circular, square or irregular shape, without being limited thereto.
[0060] In summary, the substrate structure of the present application effectively reduces the ratio of exposed copper (circuit layer and patterned metal layer) by reducing the area of the patterned metal layer exposed to the opening of the insulating protective layer (e.g. by forming the patterned metal layer in the form of thin metal lines, slots, grids, or by adding a plurality of insulating blocks in the opening), so that the area of the circuit layer and the patterned metal layer exposed to the opening accounts for about 45-55% of the area of the opening, thereby reducing the contact area between the adhesive and copper, and improving the delamination problem.
[0061] The above embodiments are used to illustrate the principles and effects of the present application, and are not intended to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be subject to the claims.
Claims
1. A substrate structure, characterized by, The application relates to a substrate, comprising: a substrate body, which is provided with a circuit layer on one surface thereof and is defined with a die area on the surface; a patterned metal layer, which is arranged on the surface; and an insulating protective layer, which is arranged on the surface and has an opening corresponding to the die area and exposing part of the circuit layer and part of the patterned metal layer, wherein the area of the circuit layer and the patterned metal layer exposed by the opening accounts for 45%-55% of the area of the opening. The substrate body is a substrate with a core layer or a substrate without a core layer.
2. The substrate structure of claim 1, wherein, The circuit layer comprises a plurality of electric contact pads and a plurality of conductive traces connecting the electric contact pads.
3. The substrate structure of claim 1, wherein, The patterned metal layer is used for providing power supply / ground.
4. The substrate structure of claim 1, wherein, The patterned metal layer comprises a plurality of metal blocks and a plurality of metal lines connecting at least two of the metal blocks.
5. The substrate structure of claim 1, wherein, The patterned metal layer comprises a large-area metal layer and a plurality of slots formed in the large-area metal layer to expose the plurality of slots to the substrate body.
6. The substrate structure of claim 1, wherein, The slots can have square, circular, oval or irregular shapes.
7. The substrate structure of claim 6, wherein, The patterned metal layer comprises grid metal lines.
8. The substrate structure of claim 1, wherein, The patterned metal layer further comprises metal blocks connecting the grid metal lines.
9. The substrate structure of claim 8, wherein, The insulating protective layer further comprises a plurality of insulating blocks in the die area in the opening.
10. The substrate structure of claim 1, wherein, The plurality of insulating blocks are spaced from each other and have circular, square or irregular shapes.
11. The substrate structure of claim 10, wherein,