Memory bare chip, chip and integrated circuit
By integrating multiple interface modules into the memory die, the problem of the limited application scenarios of the memory die is solved, enabling adaptation to different bandwidth and packaging requirements, and reducing the difficulty and cost of chip manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- M2 SEMICON LTD
- Filing Date
- 2025-01-24
- Publication Date
- 2026-04-10
AI Technical Summary
The limited application scenarios of bare memory dies make it impossible to meet different bandwidth and packaging requirements, leading to increased difficulty and cost in chip manufacturing.
The memory die integrates multiple first interface modules, each with a different packaging method. This allows for the selection of an appropriate packaging method to connect the memory die and the computing die, enabling adaptation to different bandwidth and packaging requirements.
Memory dies are suitable for a variety of applications, reducing the difficulty and cost of chip manufacturing and improving flexibility and applicability.
Smart Images
Figure CN224111625U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of electronics, and more particularly, to a memory die, a chip and an integrated circuit. BACKGROUND
[0002] In order to reduce the overall size of a chip, the use of memory dies is becoming more and more widespread. At present, a common problem with memory dies is that the application scenarios are single. Therefore, there is an urgent need for a memory die that can be applied to more application scenarios. CONTENT OF THE UTILITY MODEL
[0003] The present application provides a memory die, a chip and an integrated circuit, which can be applied to more application scenarios.
[0004] In a first aspect, a memory die is provided, comprising: a memory die body; a plurality of first interface modules integrated in the memory die body, the plurality of first interface modules corresponding one-to-one to a plurality of packaging modes.
[0005] In the present application, the memory die comprises a memory die body and a plurality of first interface modules integrated in the memory die body, and the memory die can be connected to a computing die through any one of the first interface modules. The plurality of first interface modules correspond to different packaging modes, and different packaging modes correspond to different bandwidths. In the application process of the memory die, the first interface module corresponding to the appropriate packaging mode can be selected according to the packaging requirements and bandwidth requirements to connect the memory die and the computing die, so that the memory die can be applied to different bandwidth requirements and packaging requirements, thereby enabling the memory die to be applied to more application scenarios.
[0006] Furthermore, in the use process of the memory die, the first interface module with lower bandwidth can be used to connect the memory die and the computing die for scenarios with lower bandwidth requirements. Since the packaging mode corresponding to the first interface module with lower bandwidth has lower manufacturing difficulty, the use of the first interface module with lower bandwidth to connect the memory die and the computing die can reduce the manufacturing difficulty and cost of the chip.
[0007] Optionally, the memory die body comprises a base die and a plurality of memory dies; the plurality of memory dies are stacked on the base die; and the plurality of first interface modules are integrated in the base die.
[0008] Optionally, the memory die body comprises at least one memory die; when the memory die is a plurality of memory dies, the plurality of memory dies are stacked in sequence, and the plurality of first interface modules are integrated in one of the memory dies; when the memory die is one memory die, the plurality of first interface modules are integrated in the memory die.
[0009] Optionally, the plurality of packaging manners comprises at least 2D packaging and 2.5D packaging.
[0010] Optionally, a bump pitch of the first interface module corresponding to the 2D packaging is greater than or equal to 100 microns and less than or equal to 150 microns, and a bump pitch of the first interface module corresponding to the 2.5D packaging is greater than or equal to 20 microns and less than or equal to 55 microns.
[0011] In a second aspect, a chip is provided, comprising a packaging substrate and a computing die, and the memory die as described in the first aspect; the computing die and the memory die are mounted on the packaging substrate, at least one second interface module is integrated in the computing die; a first target interface module in the plurality of first interface modules is connected with a second target interface module in the at least one second interface module.
[0012] Optionally, the chip further comprises an interposer, and the chip comprises a plurality of memory dies;
[0013] The first target interface module of a first memory die in the plurality of memory dies is connected with a corresponding second target interface module in the computing die through the interposer; and the first target interface module of a second memory die in the plurality of memory dies is connected with a corresponding second target interface module in the computing die through the packaging substrate.
[0014] Optionally, the chip further comprises an interposer; the packaging manner corresponding to the first target interface module is 2.5D packaging, and the first target interface module is connected with the second target interface module through the interposer.
[0015] Optionally, the packaging manner corresponding to the first target interface module is 2D packaging, and the first target interface module is connected with the second target interface module through the packaging substrate.
[0016] In a third aspect, an integrated circuit is provided, comprising the chip as described in the second aspect. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 A constituent schematic diagram of a memory die provided by an embodiment of the present application is shown;
[0018] Figure 2 A side view of a memory die provided by an embodiment of the present application is shown;
[0019] Figure 3 A side view of another memory die provided by an embodiment of the present application is shown;
[0020] Figure 4 Another side view of a memory die is shown according to an embodiment of the application;
[0021] Figure 5 A schematic diagram of a chip is shown according to an embodiment of the application;
[0022] Figure 6 A top view of the chip is shown; Figure 5
[0023] Figure 7 A schematic diagram of another chip is shown according to an embodiment of the application;
[0024] Figure 8 A top view of the chip is shown; Figure 7
[0025] Figure 9 A schematic diagram of another chip is shown according to an embodiment of the application;
[0026] Figure 10 A top view of the chip is shown; Figure 9 DETAILED DESCRIPTION
[0027] The technical solutions in the application will be described clearly and exhaustively below with reference to the drawings. In the description of the embodiments of the application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, in the description of the embodiments of the application, "multiple" means two or more than two.
[0028] Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features.
[0029] In the field of chips, a chip including a complete functional unit or a group of related functional units and not packaged is called a die, and the die is also called a bare chip. Based on this, a memory chip including a complete functional unit of the memory and not packaged is called a memory die, and is also called a bare memory chip. The memory die is used to support the operation of a computing die such as a graphic processing unit (GPU), a central processing unit (CPU), and a system on chip (SoC).
[0030] An interface module for communicating with a computing die is usually integrated in a memory die. The bandwidth of the interface module is unique and fixed, so the memory die can only communicate at one bandwidth and cannot meet different bandwidth requirements, making the application scenarios of the memory die relatively single. For example, when the bandwidth of the interface module integrated in the memory die is 12.8 GB / s, the interface module can only be connected with an interface module with a bandwidth of 12.8 gigabytes (GB / s) in the computing die, and cannot be connected with interface modules with bandwidths of 17.06 GB / s and 38.4 GB / s, resulting in that the memory die cannot be used with computing dies having interface modules with bandwidths of 17.06 GB / s and 38.4 GB / s. For ease of distinction, the interface module in the memory die is referred to as a first interface module, and the interface module in the computing die is referred to as a second interface module.
[0031] Moreover, in order to make the memory die have a higher bandwidth (i.e., the bandwidth of the first interface module), the first interface module is generally selected to have a higher bandwidth. Generally, the higher the bandwidth of the interface module, the more advanced the corresponding packaging method. When the bandwidth of the first interface module is large and the packaging method is relatively advanced, the manufacturing cost of the chip in which the memory die is located will be significantly increased. For example, when the packaging method corresponding to the first interface module in the memory die is 2.5D packaging, the memory die cannot be packaged by 2D packaging in the chip manufacturing process, and can only be packaged by 2.5D packaging, which increases the process difficulty in the manufacturing process and increases the manufacturing cost.
[0032] Among them, 2D packaging is also called traditional packaging or standard packaging, which refers to packaging of a bare chip on the horizontal surface of a package substrate. 2.5D packaging is also called advanced packaging (Advance Package), which is a technology between 2D packaging and 3D packaging. In 2.5D packaging, the bare chips are connected through an interposer.
[0033] To solve the above technical problems, the application provides a memory die, comprising a memory die body and a plurality of first interface modules integrated in the memory die body, and the memory die can be connected with a computing die through any one of the first interface modules. The plurality of first interface modules correspond to different packaging modes respectively, and different packaging modes correspond to different bandwidths. In the application process of the memory die, the corresponding packaged first interface module can be selected to connect the computing die according to the demand, so as to package the memory die according to the corresponding packaging mode, thereby making the memory die applicable to different bandwidth requirements and packaging requirements, and thus making the memory die applicable to more application scenarios.
[0034] Referring to Figure 1 , Figure 1 A composition diagram of a memory die provided by an embodiment of the application is shown. As Figure 1 shown, the memory die comprises a memory die body 10, a first interface module 11 and a first interface module 12. The first interface module 11 and the first interface module 12 are integrated inside the memory die body 10, and the first interface module 11 and the first interface module 12 correspond to different packaging modes respectively, and different packaging modes correspond to different bandwidths, so the bandwidths of the first interface module 11 and the first interface module 12 are different.
[0035] Exemplarily, the first interface module 11 can be composed of a plurality of first physical layer (Physical, PHY) modules arranged side by side, and each first physical layer module corresponds to a 2D packaging mode, which is denoted by the symbol “D2D-SP” as Figure 1 shown. Similarly, the first interface module 12 can be composed of a plurality of second physical layer modules arranged side by side, and each second physical layer module corresponds to a 2.5D packaging mode, which is denoted by the symbol “D2D-AP” as Figure 1 shown.
[0036] Among them, the first physical layer module and the second physical layer module are interface modules for connecting two die chips. The purpose of including a plurality of first physical layer modules in the first interface module 11 is to expand the bandwidth of the first interface module 11. For example, when the bandwidth of one first physical layer module is N, and the first interface module 11 is composed of M first physical layer modules arranged side by side, the bandwidth of the first interface module 11 is N×M. Similarly, the purpose of including a plurality of second physical layer modules in the first interface module 12 is to expand the bandwidth of the first interface module 12. For example, when the bandwidth of one second physical layer module is N, and the first interface module 12 is composed of M second physical layer modules arranged side by side, the bandwidth of the first interface module 12 is N×M.
[0037] As Figure 1As shown, since the packaging mode corresponding to the first interface module 11 is 2D packaging, when the memory die body 10 is connected with the computing die through the first interface module 11, the memory die body 10 can adopt 2D packaging. Since the packaging mode corresponding to the first interface module 12 is 2.5D packaging, when the memory die body 10 is connected with the computing die through the first interface module 12, the memory die body 10 can adopt 2.5D packaging.
[0038] When the first interface module 11 and the first interface module 12 are integrated in the memory die body 10, when a high communication rate is required between the memory die and the computing die, the first interface module 12 with high bandwidth can be used to connect the memory die body 10 and the computing die, and the memory die body 10 uses 2.5D packaging. When a low communication rate is required between the memory die and the computing die, the first interface module 11 with low bandwidth can be used to connect the memory die body 10 and the computing die, and the memory die body 10 uses 2D packaging. Therefore, the memory die body 10 can be applicable to scenarios with high bandwidth requirements and scenarios with low bandwidth requirements, as well as 2D packaging scenarios and 2.5D packaging scenarios.
[0039] It should be understood that the number of first interface modules integrated in the memory die and the corresponding packaging mode can include but are not limited to the above examples.
[0040] Optionally, the memory die body includes a base die and a plurality of memory dies, the plurality of memory dies are stacked on the base die, and the plurality of first interface modules are integrated in the base die.
[0041] In an embodiment, the memory die can be a high bandwidth memory (HBM) including a plurality of memory dies and a base die. The memory die is also referred to as a dynamic random access memory (DRAM), and the base die is also referred to as a logic die. Each memory die includes a certain number of memory cells for storing data. The base die includes a control unit and a first interface module for controlling and managing each memory die, and realizing communication between the HBM and the computing die.
[0042] Referring to Figure 2 , Figure 2 A side view of a memory die provided by an embodiment of the present application is shown. As shown in FIG. 1, the memory die includes a base die 100 and a plurality of memory dies 200 stacked on the base die 100. The base die 100 includes a control unit 110 and a first interface module 120. The control unit 110 is used to control and manage each memory die 200, and the first interface module 120 is used to realize communication between the memory die and a computing die. Figure 2As shown, the memory die body 10 includes a base die 23 and a plurality of memory dies 21. Within the memory die body 10, a bump array 22 is arranged between two adjacent dies (which can be two memory dies or a memory die and a base die), and the dies are connected through a through-silicon via 24 and a bump in the bump array 22.
[0043] In combination Figure 1 As shown, the first interface module 11 and the first interface module 12 are integrated in the base die 23. In the use of the memory die, the memory die can be connected to a computing die through the first interface module 11 or connected to a computing die through the first interface module 12.
[0044] Optionally, the memory die body includes at least one memory die; when there are a plurality of memory dies, the plurality of memory dies are stacked in sequence, and the plurality of first interface modules are integrated in one of the memory dies; when there is one memory die, the plurality of first interface modules are integrated in the one memory die.
[0045] In an embodiment, the memory die can be a three-dimensional dynamic random access memory (3D DRAM) including a plurality of memory dies stacked with each other.
[0046] Referring to Figure 3 , Figure 3 A side view of another memory die provided by an embodiment of the present application is shown. As shown, Figure 3 As shown, the memory die includes a memory die body 10, and the memory die body 10 includes a plurality of memory dies 31. Within the memory die body 10, a bump array 32 is arranged between two adjacent memory dies 31, and the memory dies 31 are connected through a through-silicon via 33 and a bump in the bump array 32. Each memory die 31 has a certain number of storage units integrated therein for storing data. In combination Figure 1 As shown, the first interface module 11 and the first interface module 12 can be arranged in one of the memory dies 31 at the bottom of the memory die body 10.
[0047] In another embodiment, the memory die can be a two-dimensional dynamic random access memory (2D DRAM) including only one memory die. As shown, Figure 4 Figure 4 Another side view of a memory die is shown, the memory die includes a memory die body 10, the memory die body 10 includes a memory die 41 and a bump array 42. The memory die 41 is integrated with a certain number of memory cells for storing data, and is also integrated with a first interface module 11 and a first interface module 12.
[0048] It should be understood that the above is only an example, and the specific composition of the memory die can include but is not limited to the above examples.
[0049] Optionally, the bump pitch of the first interface module corresponding to the 2D package is greater than or equal to 100 microns and less than or equal to 150 microns, and the bump pitch of the first interface module corresponding to the 2.5D package is greater than or equal to 20 microns and less than or equal to 55 microns.
[0050] Wherein, the bump pitch refers to the pitch between two adjacent bumps of the interface module. As shown, Figure 2 The bump pitch of the first interface module 11 corresponding to the 2D package is greater than or less than 100 microns (μm) and less than or equal to 150 microns. For example, the bump pitch of the first interface module 11 can be 100 microns, 126 microns, 137 microns, 144 microns, 148 microns and 150 microns, etc. The bump pitch of the first interface module 12 corresponding to the 2.5D package is greater than or less than 20 microns and less than or equal to 55 microns. For example, the bump pitch of the first interface module 12 can be 20 microns, 26 microns, 29 microns, 31 microns, 46 microns, 51 microns, 53 microns and 55 microns, etc.
[0051] In the embodiments of the present application, the memory die includes a memory die body and a plurality of first interface modules integrated in the memory die body, and the memory die can be connected with the computing die through any one of the first interface modules. The plurality of first interface modules correspond to different packaging modes respectively, and different packaging modes correspond to different bandwidths. In the application process of the memory die, the first interface module corresponding to the corresponding packaging mode can be selected according to the packaging requirement and the bandwidth requirement to connect the memory die and the computing die, so that the memory die can be applied to different bandwidth requirements and packaging requirements, thereby the memory die can be applied to more application scenarios.
[0052] Moreover, in the use process of the memory die, the first interface module with lower bandwidth can be used to connect the memory die and the computing die in a scene with lower bandwidth requirement. Since the manufacturing difficulty of the packaging mode corresponding to the first interface module with lower bandwidth is lower, when the first interface module with lower bandwidth is used to connect the memory die and the computing die, the manufacturing difficulty and cost of the chip can be reduced.
[0053] To solve the above technical problems, the application further provides a chip, which comprises a packaging substrate and a computing die, and a memory die as shown in Figures 1-4 The computing die and the memory die are mounted on the packaging substrate, the computing die is integrated with at least one second interface module; a first target interface module in the plurality of first interface modules is connected with a second target interface module in the at least one second interface module.
[0054] In the embodiment, when the chip comprises one or more memory dies in the above examples, for each memory die, one first interface module in the memory die is connected with a corresponding second interface module in the computing die, so as to realize the connection between the computing die and the memory die. In the plurality of first interface modules of each memory die, the first interface module connected with the corresponding second interface module in the computing die is referred to as a first target interface module; in the one or more second interface modules of the computing die, the second interface module connected with the corresponding first interface module in the memory die is referred to as a second target interface module.
[0055] Optionally, the chip further comprises an interposer; the packaging mode corresponding to the first target interface module is 2.5D packaging, and the first target interface module is connected with the second target interface module through the interposer.
[0056] Referring to Figure 5 , Figure 5 A composition schematic diagram of a chip provided by an embodiment of the application is shown. As shown in Figure 5 The chip comprises a packaging substrate 54, a computing die 51 and an interposer 53, and a memory die as shown in Figure 4 The computing die 51 can be a GPU, a CPU or a SOC, etc., the interposer 53 is mounted on the packaging substrate 54, and the computing die 51 and the memory die body 41 are indirectly mounted on the packaging substrate 54 through the interposer 53.
[0057] As shown in Figure 5As shown, the bump array 42 at the bottom of the memory die body 10 is located between the interposer 53 and the memory die 41, and the bump array 52 at the bottom of the computing die 51 is located between the interposer 53 and the computing die 51. The first interface module 12 corresponds to a 2.5D packaging mode, and the first interface module 12 is a first target interface module. The computing die 51 internally integrates a second interface module 511 matched with the first interface module 12, and the second interface module 511 is a second target interface module corresponding to the first interface module 12. The first interface module 12 and the second interface module 511 are connected through the wires arranged in the interposer 53, so as to realize the communication connection between the computing die 51 and the memory die body 10. Since the first interface module 12 is suitable for 2.5D packaging, the memory die body 10 and the computing die 51 can be packaged by 2.5D packaging in the chip manufacturing process.
[0058] It should be understood that, in addition to including Figure 5 The memory die body 10, the computing die 51, the bump array 52, the bump array 55, and the bump array 56 shown can also include other components, which are not limited by the present embodiment.
[0059] Optionally, Figure 5 The chip shown can include a plurality of memory die bodies 10, and each memory die body 10 can be connected with the computing die 51 through the first interface module 12 therein. As Figure 6 As shown, Figure 6 It is shown that Figure 5 The top view of the chip shown shows that the computing die 51 and the memory die body 10 are mounted on the interposer 53, the computing die 51 is provided with a plurality of second interface modules 511 (i.e., second target interface modules), and each memory die body 10 is connected with a corresponding second interface module 511 through the first interface module 12 (i.e., the first target interface module).
[0060] Optionally, the first target interface module corresponds to a 2D packaging mode, and the first target interface module is connected with the second target interface module through a packaging substrate.
[0061] Referring to Figure 7 , Figure 7 A schematic diagram of another chip provided by the present embodiment is shown. As Figure 7 As shown, the chip includes a packaging substrate 54 and a computing die 51, and Figure 4The memory die is shown. The computing die 51 and the memory die body 10 are directly mounted on the packaging substrate 54. The bump array 42 at the bottom of the memory die body 10 is located between the packaging substrate 54 and the memory die 41, and the bump array 52 at the bottom of the computing die 51 is located between the packaging substrate 54 and the computing die 51. The packaging mode corresponding to the first interface module 11 is 2D packaging, and the first interface module 11 is a first target interface module.
[0062] The second interface module 512 matching the first interface module 12 is integrated in the computing die 51, and the second interface module 512 is a second target interface module corresponding to the first interface module 11. The first interface module 11 and the second interface module 512 are connected through the wires arranged in the packaging substrate 54, so as to realize the communication connection between the computing die 51 and the memory die body 10. Since the first interface module 11 is suitable for 2D packaging, the memory die body 10 and the computing die 51 can be packaged by 2D packaging in the chip manufacturing process.
[0063] Optionally, Figure 7 As shown in the chip, a plurality of memory dies can be included, and each memory die can be connected with the computing die 51 through the first interface module 11 therein. Figure 8 As shown, Figure 8 As shown, Figure 7 The top view of the chip is shown. As shown, Figure 8 The computing die 51 and the memory die body 10 are directly mounted on the packaging substrate 54, and the computing die 51 is provided with a plurality of second interface modules 512 (i.e. second target interface modules), and each memory die body 10 is connected with a corresponding second interface module 512 through the first interface module 11 (i.e. the first target interface module).
[0064] Optionally, the chip further includes an interposer, and the chip includes a plurality of memory dies; the first target interface module of a first memory die in the plurality of memory dies is connected with a corresponding second target interface module in the computing die through the interposer; and the first target interface module of a second memory die in the plurality of memory dies is connected with a corresponding second target interface module in the computing die through the packaging substrate.
[0065] In an embodiment, when the chip can include a plurality of memory dies, the first interface module corresponding to 2.5D packaging in a part of the plurality of memory dies can be connected with a corresponding second interface module in the computing die through the interposer, and this part of the memory dies is referred to as a first memory die. The first interface module corresponding to 2D packaging in another part of the plurality of memory dies can be connected with a corresponding second interface module in the computing die through the packaging substrate, and this part of the memory dies is referred to as a second memory die.
[0066] See Figure 9 , Figure 9 A schematic diagram of another chip provided in an embodiment of this application is shown. For example... Figure 9 As shown, the chip includes a packaging substrate 54, a computing die 51, and an interposer layer 53, as well as at least one first memory die 101 and at least one second memory die 102, wherein the first memory die 101 and the second memory die 102 are... Figure 4 The memory dies shown are as follows. Die 51 and the first memory die 101 are mounted on the interposer layer 53, and the second memory die 102 is directly mounted on the packaging substrate 54. The first interface module 11 is packaged using a 2D package method, and the first interface module 12 is packaged using a 2.5D package method. In the first memory die 101, the first target interface module is the first interface module 12; in the second memory die 102, the first target interface module is the first interface module 11.
[0067] For each first memory die 101, a matching second interface module 511 (i.e., second target interface module) is set in the die 51. The second interface module 511 is connected to the first interface module 12 in the first memory die 101. The first interface module 12 is suitable for 2.5D packaging. Therefore, in the chip manufacturing process, the first memory die 101 can be packaged using 2.5D packaging.
[0068] For each second memory die 102, a matching second interface module 512 (i.e., second target interface module) is provided in the die 51. The second interface module 512 is connected to the first interface module 11 in the second memory die 102 through the wiring in the interposer layer 53 and the packaging substrate 54. The first interface module 11 is suitable for D packaging. Therefore, in the chip manufacturing process, the first memory die 102 can be packaged using 2.5D packaging.
[0069] in, Figure 9 The chip shown may include one or more first memory dies 101 and one or more second memory dies 102.
[0070] like Figure 10 As shown, Figure 10 It shows Figure 9 A top view of the chip shown. Combined with... Figure 9As shown, the compute die 51 and the first memory dies 101 are mounted on an interposer 53, which is mounted on a package substrate 54, and the second memory dies 102 are mounted directly on the package substrate 54. On the interposer 53, the first interface modules 12 in each of the first memory dies 101 are connected to a corresponding one of the second interface modules 511 in the compute die 51 through the interposer 53. The first interface modules 11 in the second memory dies 102 are connected to the second interface modules 512 (not shown in the figure) in the compute die 51 through the wiring in the package substrate 54 and the interposer 53.
[0071] The embodiments of the present application also provide an integrated circuit, which comprises Figures 5-10 the chip shown.
[0072] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A memory die, comprising: The chip comprises: a memory die body; a plurality of first interface modules integrated in the memory die body, the plurality of first interface modules corresponding to a plurality of packaging modes one by one, the plurality of packaging modes comprising 2D packaging and 2.5D packaging, the first interface module being used for connecting a computing die and the memory die body.
2. The memory die of claim 1, wherein, The memory die body comprises a base die and a plurality of memory dies; The plurality of memory dies are stacked on the base die; The plurality of first interface modules are integrated in the base die.
3. The memory die of claim 1, wherein, The memory die body comprises at least one memory die; When the memory dies are a plurality, the plurality of memory dies are stacked in sequence, and the plurality of first interface modules are integrated in one of the memory dies; When the memory dies are one, the plurality of first interface modules are integrated in one of the memory dies.
4. The memory die of claim 1, wherein, The bump pitch of the first interface module corresponding to the 2D packaging is greater than or equal to 100 microns and less than or equal to 150 microns, and the bump pitch of the first interface module corresponding to the 2.5D packaging is greater than or equal to 20 microns and less than or equal to 55 microns.
5. A chip, characterized by The chip comprises a packaging substrate and a computing die, and a memory die as claimed in any one of claims 1-4; The computing die and the memory die are mounted on the packaging substrate, and at least one second interface module is integrated in the computing die; A first target interface module in the plurality of first interface modules is connected to a second target interface module in the at least one second interface module.
6. The chip of claim 5, wherein, The chip further comprises an interposer, and the chip comprises a plurality of memory dies; The first target interface module of a first memory die in the plurality of memory dies is connected to a corresponding second target interface module in the computing die through the interposer; The first target interface module of a second memory die in the plurality of memory dies is connected to a corresponding second target interface module in the computing die through the packaging substrate.
7. The chip of claim 5, wherein, The chip further comprises an interposer; The first target interface module corresponds to 2.5D packaging, and the first target interface module is connected to the second target interface module through the interposer.
8. The chip of claim 5, wherein, The first target interface module corresponds to 2D packaging, and the first target interface module is connected to the second target interface module through the packaging substrate.
9. An integrated circuit, characterized by The chip comprises a chip as claimed in any one of claims 5-8.