FPGA board card with PCIE interface
By designing anti-bending structures on the FPGA board, including vertical and parallel plates, additional support is provided, solving the problem of PCIe interfaces bending due to incorrect insertion angles, and ensuring interface integrity and smooth insertion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU ADVANCED UNITED DATA TECH CO LTD
- Filing Date
- 2025-05-06
- Publication Date
- 2026-04-14
AI Technical Summary
The PCIe interface of existing FPGA boards is prone to bending or damage due to incorrect insertion angle, affecting normal use.
Design a fault-resistant structure comprising a first and a second plate that are vertical and parallel to each other. The first plate is fixed to an integrated board, and the second plate is fixed to a housing to form additional support and prevent the PCIe interface from bending.
It effectively prevents the PCIe interface from bending or being damaged due to improper insertion direction, ensuring smooth card insertion and interface integrity.
Smart Images
Figure CN224123569U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to FPGA boards, and more particularly to an FPGA board with a PCIe interface. Background Technology
[0002] FPGA boards, as high-performance field-programmable gate array boards, are widely used in various electronic devices, especially in applications requiring high-speed data processing and logic control. FPGA boards typically include anti-misoperation mechanisms.
[0003] Fooling-proof guards are primarily used to prevent users from making mistakes when inserting boards. Their main function is to confirm the insertion direction, preventing incorrect insertion or damage to the interface. However, existing Fooling-proof guards on FPGA boards do not effectively prevent bending during insertion. In other words, even if the user inserts the board in the correct direction (left-right), incorrect insertion angles can still cause the PCIe interface to bend or even be damaged. The PCIe interface is a crucial channel for data exchange between the FPGA board and external devices; damage to it will directly affect the normal operation of the board. Utility Model Content
[0004] To address the aforementioned problems, this utility model discloses an FPGA board with a PCIe interface. The FPGA board includes a housing and an integrated board disposed within the housing. The integrated board has the PCIe interface, which passes through and protrudes from the housing. The FPGA board also includes a foolproof plate extending towards the PCIe interface. The foolproof plate includes a first board body and a second board body connected as a single unit. The PCIe interface is a linear board body interface. The first board body is perpendicular to the PCIe interface, and the second board body is parallel to the PCIe interface. The first board body is fixedly connected to the housing, and the second board body is fixedly connected to the integrated board.
[0005] In some exemplary technical solutions, the integrated board further has a first external port; the first external port passes through the side wall of the housing and protrudes to the outside of the housing, wherein the side wall through which the first external port passes is adjacent to the side wall through which the PCIE interface passes; the first board body is disposed on the side wall through which the first external port passes.
[0006] In some exemplary technical solutions, the outer shell is a cuboid shell with an opening on one side, and the integrated plate is disposed on the opening side; wherein, the second plate is disposed on the outside of the integrated plate.
[0007] In some exemplary technical solutions, the housing is further provided with a through hole for the PCIe interface; the PCIe interface includes a plug section and a transition section; a connecting part is provided between the first board and the second board, and the connecting part is fixedly connected to the first board and the second board respectively; wherein, the plug section and the transition section completely protrude from the through hole, and the connecting part is disposed in the space formed by the side wall of the housing with the through hole and the transition position of the transition section and the plug section.
[0008] In some exemplary technical solutions, the connecting part is a long strip structure, and the long strip structure is connected with the first plate and the second plate to form a triangular structure.
[0009] In some exemplary technical solutions, the connecting portion includes multiple elongated structures.
[0010] In some exemplary technical solutions, the connecting portion includes a first connecting portion and a second connecting portion, wherein the first connecting portion connects the first plate and the transition section; and the second connecting portion connects the first plate and the second plate.
[0011] In some exemplary technical solutions, the integrated board also has a second external interface that extends to the outside of the housing.
[0012] The beneficial effect of this utility model is that by configuring the anti-bending plate as a structure including a first plate and a second plate, with the first plate fixed to the integrated board and the second plate fixed to the housing, additional support is provided for the integrated board and the PCIe interface. Specifically, the first plate and the second plate are perpendicular, and the first plate is fixed to one side of the external port, thereby enabling the first plate to resist the bending of the PCIe interface.
[0013] When a user installs an FPGA board, if the direction of force applied is different from the insertion direction, a lateral bending force will be generated at the PCIe interface. The bending force is transmitted from the second board to the first board, and the first board will provide additional support to prevent the PCIe interface from breaking or being damaged.
[0014] Compared with the various complex structures in the prior art, the structure of this utility model is simpler and easier to process.
[0015] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures pointed out in the description, claims, and drawings. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A structural diagram of an FPGA board with a PCIe interface according to an embodiment of the present invention is shown.
[0018] Figure 2 A structural diagram of an FPGA board with a PCIe interface according to an embodiment of the present invention is shown.
[0019] Figure 3 A structural diagram of an FPGA board with a PCIe interface according to an embodiment of the present invention is shown.
[0020] Figure 4 A structural diagram of an FPGA board with a PCIe interface according to an embodiment of the present invention is shown.
[0021] In the attached image:
[0022] 1-Outer casing, 2-Integrated board;
[0023] 101-Anti-foolproof plate, 102-First external port, 103-Through hole, 104-Connecting part, 105-Second external interface;
[0024] 1011 - First plate, 1012 - Second plate;
[0025] 1041 - First connecting part, 1042 - Second connecting part;
[0026] 201-PCIE interface;
[0027] 2011 - Plug-in section, 2022 - Transition section. Detailed Implementation
[0028] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0029] First Embodiment
[0030] This example discloses an FPGA board with a PCIe interface 201. For the specific structure, please refer to [reference needed]. Figure 1-4 As shown in the diagram. The FPGA board includes a housing 1 and an integrated board 2 disposed within the housing 1. In some exemplary embodiments, the FPGA integrated board 2 includes an FPGA chip for performing various logic operations and data processing tasks, a power supply circuit, a storage circuit (including one or more of SDRAM, Flash, etc.) for storing FPGA configuration data, runtime intermediate data, and program code that may be required, and a clock circuit for providing a precise clock signal to ensure the correct operation of the FPGA's internal logic. (The structure of the integrated board 2 is not shown in the diagram.) The integrated board 2 has a PCIe interface 201, which passes through and protrudes from the housing 1.
[0031] In some specific examples, the FPGA board also includes a misalignment guard 101 extending toward the PCIe interface 201. For a more detailed understanding, refer to Figure 1. In this example, the misalignment guard 101 is located on one side of the PCIe interface 201. The misalignment guard 101 ensures that the board is correctly aligned and positioned when inserted into the host or other devices, preventing damage due to improper insertion. Users can more intuitively perceive the board's orientation and position when inserting it, thus avoiding reverse insertion or insertion into the wrong slot. As mentioned earlier, the misalignment guard 101 is primarily used for positioning and preventing directional errors, but the PCIe interface 201 may still break if force is applied at an angle.
[0032] In this example, the anti-misfit plate 101 includes a first plate 1011 and a second plate 1012 connected as an integral structure, and the PCIe interface 201 is a linear plate interface; the first plate 1011 is perpendicular to the PCIe interface 201, and the second plate 1012 is parallel to the PCIe interface 201; wherein, the first plate 1011 is fixedly connected to the outer shell 1, and the second plate 1012 is fixedly connected to the integrated board 2.
[0033] During use, users may apply force at an angle when inserting the PCIe interface 201, potentially damaging it or even causing it to break. In other words, if the user's installation orientation is inaccurate, bending forces may be generated at the point of contact with the PCIe interface 201, leading to breakage. This is the main reason for damage to the PCIe interface 201. The second board 1012 and the first board 1011 disclosed in this example provide sufficient support. During bending, the lateral bending force at the PCIe interface 201 is transferred from the second board 1012 to the first board 1011, providing additional support and preventing breakage or damage to the PCIe interface 201.
[0034] Second Embodiment
[0035] Based on the foregoing embodiments, this example can be combined with Figure 1 For further reference Figure 2 This is for illustrative purposes. The integrated board 2 also has a first external port 102, which passes through the side wall of the housing 1 and extends to the outside of the housing 1. In this example, the first external interface may include, but is not limited to, a UART interface for asynchronous communication with other devices via a serial communication interface; an SPI interface, a serial peripheral interface for high-speed, full-duplex, synchronous communication; or an I2C interface for connecting low-speed peripherals, which is a two-wire serial communication bus. One or more of these may be used, but no specific limitations are imposed in this example.
[0036] like Figure 2 As shown, the sidewall through which the first external port 102 passes is adjacent to the sidewall through which the PCIe interface 201 passes. The first plate 1011 is disposed on the sidewall through which the first external port 102 passes. The first plate 1011 is disposed on this side to prevent reverse insertion.
[0037] For some specific examples, please refer to further details. Figure 3 The structure shown depicts a rectangular shell 1 with an opening on one side, onto which the integrated plate 2 is positioned. The rectangular shell covers the integrated plate 2, and a second plate 1012 is positioned on the outside of the integrated plate 2. The second plate 1012 is fixed to the integrated plate 2, and in some specific examples, it is arranged as a rectangular plate on the integrated plate 2. The second plate 1012 is laterally fixed to the integrated plate 2, providing sufficient support for the integrated plate 2.
[0038] In use, when the user inserts the FPGA board at an angle, the bending force applied to the integrated board 2 by the fixing effect of the second board 1012 and the integrated board 2 acts on the overall structure of the second board 1012 and the first board 1011. In this example, the first board 1011 and the second board 1012 actually form an L-shaped structure. When the aforementioned bending force acts on the first board 1011, it is actually aligned with the long side direction of the first board 1011. The supporting effect of the first board 1011 can prevent the PCIe interface 201 from being broken.
[0039] Third Embodiment
[0040] Based on the foregoing embodiments, continue to refer to Figure 1To understand this example, the housing 1 also includes a through-hole 103 for the PCIe interface 201. In this example, the through-hole 103 is a rectangular hole. In some preferred embodiments, the housing 1 may also have multiple ventilation channels to facilitate heat dissipation.
[0041] In this example, refer to Figure 3 As shown, the PCIe interface 201 includes a plug-in section 2011 and a transition section 2022. The boundary between the plug-in section 2011 and the transition section 2022 can be referenced. Figure 3 The dotted lines in the diagram can be interpreted as follows: Specifically, the plug-in segment 2011 can be the "gold finger" part of the PCIe interface 201 used for connecting external devices (the term "gold finger" is a common technical term), and the transition segment 2022 is the remaining exposed part of the PCIe interface 201.
[0042] In this example, a connecting portion 104 is provided between the first plate 1011 and the second plate 1012, and the connecting portion 104 is fixedly connected to the first plate 1011 and the second plate 1012 respectively; wherein, the insertion segment 2011 and the transition segment 2022 completely protrude from the through hole 103, and the connecting portion 104 is disposed in the space formed by the side wall of the outer shell 1 having the through hole 103 and the transition position of the transition segment 2022 and the insertion segment 2011.
[0043] It should be understood that the transition segment 2022 described in this example is a special setting. The purpose is to provide space for the connecting part 104 in this embodiment, since the existing circuit board does not have a transition segment 2022 and only has the gold finger part. If the connecting part 104 extends beyond the gold finger part, interference problems will occur after insertion.
[0044] In a specific example, you can refer to Figure 3 In the structure shown, the connecting part 104 is an elongated structure, which connects with the first plate 1011 and the second plate 1012 to form a triangular structure. In this example, the triangular structure formed by the connecting part 104, the first plate 1011, and the second plate 1012 provides better support.
[0045] Fourth embodiment
[0046] Based on the foregoing embodiments, in some preferred examples, the structure can be referred to Figure 4 As shown, the connecting portion 104 includes a plurality of the elongated structures. In the aforementioned preferred example, a plurality of triangular structures are more stable.
[0047] In other examples, the connecting portion 104 includes a first connecting portion 1041 and a second connecting portion 1042, wherein the first connecting portion 1041 connects the first plate 1011 and the transition section 2022; similarly, see also [reference needed]. Figure 4 As shown, the second connecting part 1042 connects the first plate 1011 and the second plate 1012.
[0048] In this example, the structure connecting the integrated board 2 and the housing 1 respectively can significantly enhance the stability of the FPGA board. This example structure can effectively protect the PCIe interface 201 from damage when faced with incorrect force and direction during user insertion.
[0049] First, through the fixed connection between the second plate 1012 and the first connecting part 1041, when the user inserts the card, even if there is oblique force, the first connecting part 1041 will pull the second plate 1012, thereby effectively transferring the bending force to the more stable first plate 1011.
[0050] Secondly, the fixed connection between the second connecting part 1042 and the outer casing 1 provides additional support for the entire board. Since the outer casing 1 typically has higher rigidity and strength, the connection between the first plate 1011 and the outer casing 1 forms a robust support structure between the first plate 1011 and the second plate 1012. This structure prevents the PCIe interface 201 from bending or being damaged by improper external forces, and also prevents oblique insertion and removal, ensuring smooth insertion and removal of the board.
[0051] Fifth embodiment
[0052] Based on the aforementioned implementation, in this example, you can refer to Figure 1-4 To understand this, the integrated board 2 also has a second external interface 105, which extends to the outside of the housing 1. In this example, the second external interface 105 is a GPIO interface. Through the GPIO interface, the FPGA board can realize the functions of controlling external devices and acquiring data. At the same time, the second external interface 105 shown is similar to the first external port 102; the second external interface 105 also passes through the housing 1 and protrudes to the outside of the housing 1, facilitating connection with external devices.
[0053] The second external interface 105 is used to connect to external devices, enabling the FPGA board to control these devices and acquire data. Specifically, through the GPIO interface, the FPGA board can send control signals to the connected devices.
[0054] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. An FPGA board with a PCIe interface, the FPGA board comprising a housing (1) and an integrated board (2) disposed within the housing (1), the integrated board (2) having the PCIe interface (201) passing through and protruding from the housing (1); the FPGA board further comprising a foolproof plate (101) extending toward the PCIe interface (201), characterized in that: The anti-fouling plate (101) includes a first plate (1011) and a second plate (1012) connected as an integral structure, and the PCIE interface (201) is a linear plate interface; The first board body (1011) is perpendicular to the PCIe interface (201), and the second board body (1012) is parallel to the PCIe interface (201); The first plate (1011) is fixedly connected to the outer shell (1), and the second plate (1012) is fixedly connected to the integrated plate (2).
2. The FPGA board with a PCIe interface according to claim 1, characterized in that: The integrated board (2) also has a first external port (102); The first external port (102) passes through the side wall of the housing (1) and protrudes to the outside of the housing (1), wherein the side wall through which the first external port (102) passes is adjacent to the side wall through which the PCIE interface (201) passes; The first plate (1011) is provided on the side wall through which the first external port (102) passes.
3. The FPGA board with a PCIe interface according to claim 1, characterized in that: The outer shell (1) is a cuboid shell with an opening on one side, and the integrated plate (2) is provided on the opening side; The second plate (1012) is disposed on the outside of the integrated plate (2).
4. The FPGA board with a PCIe interface according to any one of claims 1-3, characterized in that: The housing (1) is also provided with a through hole (103) for the PCIE interface (201); the PCIE interface (201) includes a plug section (2011) and a transition section (2022); A connecting part (104) is provided between the first plate (1011) and the second plate (1012), and the connecting part (104) is fixedly connected to the first plate (1011) and the second plate (1012); Wherein, the insertion section (2011) and the transition section (2022) completely protrude from the through hole (103), and the connecting part (104) is provided at: The outer casing (1) has a sidewall with a through hole (103) and the space formed by the transition position of the transition section (2022) and the plug section (2011).
5. The FPGA board with a PCIe interface according to claim 4, characterized in that: The connecting part (104) is a long strip structure, and the connecting part (104) is connected with the first plate (1011) and the second plate (1012) to form a triangular structure.
6. The FPGA board with a PCIe interface according to claim 5, characterized in that: The connecting part (104) includes a plurality of the elongated structures.
7. The FPGA board with a PCIe interface according to claim 5, characterized in that: The connecting part (104) includes a first connecting part (1041) and a second connecting part (1042), wherein the first connecting part (1041) connects the first plate (1011) and the transition section (2022); The second connecting part (1042) connects the first plate (1011) and the second plate (1012).
8. The FPGA board with a PCIe interface according to claim 1, characterized in that: The integrated board (2) also has a second external interface (105) that extends to the outside of the housing (1).