Semiconductor device

Abstract

A semiconductor device includes a substrate, a fin base, a nanostructured channel structure, and a gate structure. The fin base is arranged on the substrate; the nanostructured channel structure is arranged on the fin base; a gate structure surrounds the nanostructured channel structure. The nano-structured channel structure comprises a germanium-free region, a germanium-doped region and a cover layer; the germanium-doped region surrounds the germanium-free region; the cap layer surrounds the germanium doped region. The germanium doped region includes a germanium concentration that varies along a thickness of the germanium doped region.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor devices. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher efficiency, and lower costs continues to increase. To meet these demands, the semiconductor industry is constantly miniaturizing semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and gate-all-around FETs (GAA FETs). This miniaturization increases the complexity of the semiconductor manufacturing process. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0004] In some embodiments, a semiconductor device is provided, the semiconductor device comprising a substrate; a fin substrate disposed on the substrate; a nanostructured channel structure disposed on the fin substrate, the nanostructured channel structure comprising: a germanium-free region; a germanium-doped region surrounding the germanium-free region, wherein the germanium-doped region comprises a germanium concentration varying along the thickness of the germanium-doped region; a capping layer surrounding the germanium-doped region; and a gate structure surrounding the nanostructured channel structure.

[0005] According to one embodiment of the present invention, the capping layer contacts the gate structure.

[0006] According to one embodiment of the present invention, the cover layer directly contacts the fin base.

[0007] According to one embodiment of the present invention, the capping layer is located between the germanium-doped region and the fin base.

[0008] According to one embodiment of the present invention, the capping layer directly contacts an interface oxide layer of the gate structure.

[0009] According to one embodiment of the present invention, the interface oxide layer covers the sidewall of the fin base.

[0010] According to one embodiment of the present invention, the interface oxide layer directly contacts the capping layer and the germanium-doped region.

[0011] According to one embodiment of the present invention, it further includes: an internal spacer adjacent to the gate structure.

[0012] According to one embodiment of the present invention, the internal spacer directly contacts the cover layer.

[0013] According to one embodiment of the present invention, the internal spacer is separated from the germanium-doped region. Attached Figure Description

[0014] The embodiments of this utility model can be better understood from the following detailed description and the accompanying drawings. It should be noted that, according to standard industry practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0015] Figure 1A The image shows an isometric view of a semiconductor device according to some embodiments.

[0016] Figure 1B and Figure 1C The diagram shows a cross-sectional schematic of a semiconductor device having a nanostructured channel structure, according to some embodiments.

[0017] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device having a nanostructured channel structure, based on some embodiments.

[0018] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 10A , Figure 10B The illustration is based on some embodiments, in Figure 2 A cross-sectional schematic diagram of a semiconductor device with a nanostructured channel structure, showing the various stages of the manufacturing process.

[0019] Figure 7C , Figure 8C , Figure 9B The figures illustrate, based on some embodiments, the germanium (Ge) concentration profile across the nanostructured channel structure at various stages of the manufacturing process.

[0020] Figure 9C The variation in silicon-germanium (SiGe) etching rate is shown for different germanium concentrations in the silicon-germanium layer.

[0021] The following description of illustrative embodiments will be made with reference to the accompanying drawings. In the drawings, similar reference numerals generally denote elements that are identical, functionally similar, and / or structurally similar.

[0022] The attached figures are labeled as follows:

[0023] 100: Semiconductor devices

[0024] 106: Base

[0025] 109: Fin base

[0026] 110: Source / Drain Region

[0027] 112: Gate Structure

[0028] 114: Gate spacer

[0029] 115: Internal spacers

[0030] 116: Etching stop layer

[0031] 118: Interlayer dielectric layer

[0032] 120: Shallow trench isolation zone

[0033] 122: Nanostructured Channel Layer

[0034] 122A, 122B: Semiconductor region

[0035] 124,702: Cap layer

[0036] 125: Nanostructured channel structure

[0037] 126: Interface oxide layer

[0038] 128: High dielectric constant gate dielectric layer

[0039] 130: Work function metal layer

[0040] 132: Gate metal fill layer

[0041] 200: Method

[0042] 205,210,215,220,225,230,235: Operations

[0043] 302: Polycrystalline silicon structure

[0044] 303: Dielectric layer

[0045] 304: Sacrificial nanostructured layer

[0046] 308: Nanostructured layer

[0047] 310: Superlattice structure

[0048] 502, 504, 602: Gate opening

[0049] Cth: Critical germanium concentration

[0050] d1, d2, d3: Depth

[0051] T1, T2, T3: Temperature

[0052] t1, t2, t3: Time Detailed Implementation

[0053] It is important to understand that the following content provides many different embodiments or examples to implement different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the description. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment of this disclosure, but may depend on the processing conditions and / or required nature of the components. Furthermore, in the following description, forming the first component above or on the second component includes embodiments where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components, such that the first and second components are not in direct contact. In addition, different examples in the content may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0054] To facilitate the description of the relationship between one element or component and another (or multiple elements or multiple components) in the accompanying drawings, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms are used. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device during use or operation. The device may also be positioned otherwise (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly.

[0055] References to "an embodiment," "embodiment," "exemplary embodiment," "illustrative," etc., in this specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment is not necessarily to include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0056] It should be understood that the wording or terminology in this utility model is for descriptive purposes and not for limitation, so that those skilled in the art can interpret the terminology or terminology of this specification based on the teachings.

[0057] In some embodiments, the terms "about" and "approximately" may indicate a given quantity of values ​​varying within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are merely illustrative and not intended to be limiting. The terms "about" and "approximately" may refer to a percentage of a value as interpreted by those skilled in the art based on the teachings of this invention.

[0058] Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, these structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0059] This invention provides examples of multi-critical-voltage (Vt) devices with field-effect transistors (e.g., fin field-effect transistors or fully wound-gate field-effect transistors) having improved nanostructured channel configurations. In some embodiments, the nanostructured channel structure includes a nanostructured channel layer having a silicon (Si) region and a germanium (Ge) doped region surrounding the silicon region. In some embodiments, the nanostructured channel structure may include a capping layer surrounding the germanium doped region. Introducing germanium atoms into the nanostructured channel layer improves the performance of p-type field-effect transistor (p-FET) devices by inducing higher compressive stress in the nanostructured channel layer. The higher compressive stress in the germanium-implanted nanostructured channel layer enhances carrier mobility and higher on-current in the p-type field-effect transistor device. The germanium-implanted nanostructured channel layer provides better p-type field-effect transistor critical voltage control in miniaturized advanced device structures (e.g., fin field-effect transistors or fully wound-gate field-effect transistors). This invention also provides a method for forming nanostructured channel structures for miniaturized device structures. This invention is specifically designed for devices with spacing restrictions between adjacent nanostructured channel layers, for forming germanium-doped regions and / or capping layers on the nanostructured channel layers.

[0060] Figure 1A This diagram shows an isometric view of a semiconductor device 100 according to some embodiments. In some embodiments, the semiconductor device 100 may represent a field-effect transistor (FET). For example, the FET may be a fully wound gate FET. In some embodiments, the semiconductor device 100 may represent an n-type FET (NFET) or a p-type FET. Unless otherwise stated, the discussion of the semiconductor device 100 applies to both n-type and p-type FETs. Figure 1B The display is based on some embodiments, along Figure 1A Line AA, a cross-sectional schematic diagram of semiconductor device 100. Figure 1C The display is based on some embodiments, along Figure 1A Line BB is a cross-sectional view of semiconductor device 100. For simplicity, Figure 1B and Figure 1C The display has features not shown in Figure 1A A cross-sectional view of the additional structures. Unless otherwise stated, Figures 1A to 1C The discussion of elements with the same symbol applies to each other.

[0061] Please refer to Figures 1A to 1C The semiconductor device 100 may include (i) a substrate 106, (ii) a fin substrate 109 (also referred to as a "chip substrate"), (iii) a gate structure 112 disposed on the fin substrate 109, (iv) a source / drain (S / D) region 110 disposed on the portion of the fin substrate 109 not covered by the gate structure 112, (v) a nanostructured channel structure 125, (vi) a gate spacer 114 disposed along the sidewall of the gate structure 112, (vii) a dielectric layer 303 below the gate spacer 114, (viii) an internal spacer 115 disposed along the sidewall of the source / drain region 110, (ix) a shallow trench isolation (STI) region 120, and (x) an etch stop layer disposed directly above the source / drain region 110. (116) layers (ESLs) and (xi) an interlayer dielectric (ILD) layer 118 disposed directly above the etch stop layer 116. Depending on the context, the source / drain region 110 may represent the source or drain individually or collectively. The term “nanostructured” means that a structure, layer, and / or region has a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm within the scope of this invention.

[0062] Semiconductor device 100 may be formed on substrate 106. Other field-effect transistors and / or structures (e.g., isolation structures) may be formed on substrate 106. Substrate 106 may be a semiconductor material, such as Si, Ge, SiGe, silicon-on-insulator (SOI) structures, other suitable semiconductor materials, and combinations thereof. Furthermore, substrate 106 may be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic). In some embodiments, fin base 109 may comprise a material similar to substrate 106 and may have elongated sides extending along the X-axis. In some embodiments, shallow trench isolation region 120, etch stop layer 116, and interlayer dielectric layer 118 may comprise insulating materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide nitride (SiCN), silicon oxycarbide nitride (SiOCN), silicon germanium oxide (SiGeO). x ) and other suitable insulating materials.

[0063] Each nanostructured channel structure 125 may be surrounded by a gate structure 112 and disposed on a fin base 109. In some embodiments, each nanostructured channel structure 125 may include (i) a nanostructured channel layer 122 and (ii) a capping layer 124. In some embodiments, the nanostructured channel layer 122 may include a semiconductor material, such as silicon, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), and other suitable semiconductor materials.

[0064] In some embodiments, the nanostructured channel layer 122 may include semiconductor regions 122A and 122B. In some embodiments, semiconductor region 122A may be germanium-free and may be an undoped or doped semiconductor region. In some embodiments, semiconductor region 122A may be an undoped or doped silicon region and may be referred to as a silicon region. In some embodiments, semiconductor region 122A may contain non-germanium dopants, such as boron, indium, aluminum, or gallium dopants. In some embodiments, semiconductor region 122A may be surrounded by semiconductor region 122B. In some embodiments, semiconductor region 122B may be a doped semiconductor region and may contain germanium dopants. In some embodiments, semiconductor region 122B may be a germanium-doped silicon region and may also be referred to as a silicon-germanium region. In some embodiments, the concentration of germanium atoms in semiconductor region 122B may be from about 10 atomic% to about 40 atomic%.

[0065] In some embodiments, capping layer 124 may surround nanostructured channel layer 122 and may contact semiconductor region 122B and gate structure 112. In some embodiments, capping layer 124 may comprise a germanium substrate, such as silicon germanium, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), and other suitable germanium substrates. In some embodiments, capping layer 124 may not be present in nanostructured channel structure 125, and semiconductor region 122B of nanostructured channel layer 122 may contact gate structure 112. Although semiconductor device 100 shows three nanostructured channel structures 125, semiconductor device 100 may include any number of nanostructured channel structures 125. Although nanostructured channel layer 122 is shown with a rectangular cross-section, nanostructured channel layer 122 may have other geometric cross-sections, such as circular, elliptical, triangular, or polygonal.

[0066] In some embodiments, for an n-type field-effect transistor, the source / drain region 110 may comprise an epitaxially grown semiconductor material (e.g., silicon) and an n-type dopant (e.g., phosphorus and other suitable n-type dopant). In some embodiments, for a p-type field-effect transistor, the source / drain region 110 may comprise an epitaxially grown semiconductor material (e.g., silicon and silicon-germanium) and a p-type dopant (e.g., boron and other suitable p-type dopant).

[0067] Each gate structure 112 may be a multilayer structure and may surround the nanostructured channel structure 125, wherein the gate structure 112 may be referred to as a "fully-wound gate (GAA) structure" or a "horizontal gate-all-around (HGAA) structure". The semiconductor device 100 may be referred to as a "fully-wound gate field-effect transistor". The gate portion of the gate structure 112 surrounding the nanostructured channel structure 125 may be electrically isolated from adjacent source / drain regions 110 by internal spacers 115, such as... Figure 1B As shown. The gate portion of the gate structure 112 disposed on the topmost nanostructured channel structure 125 can be electrically isolated from the adjacent source / drain region 110 through the gate spacer 114, as shown. Figure 1B As shown. The internal spacer 115 and the gate spacer 114 may contain insulating materials, such as SiO2, SiN, SiON, SiCN, SiOCN and other suitable insulating materials.

[0068] In some embodiments, each gate structure 112 may include (i) an interfacial oxide (IL) layer 126, (ii) a high-k (HK) gate dielectric layer 128, (iii) a work function metal (WFM) layer 130, and (iv) a gate metal fill layer 132. As used herein, the term "high-k (HK)" represents high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high dielectric constant means a dielectric constant greater than that of SiO2 (e.g., greater than 3.9).

[0069] The interface oxide layer 126 may be disposed on and in contact with the capping layer 124 of the nanostructured channel structure 125. In the absence of the capping layer 124, the interface oxide layer 126 may be disposed on and in contact with the semiconductor region 122B of the nanostructured channel structure 125. In some embodiments, the interface oxide layer 126 may comprise SiO2, SiGeO, etc. x or germanium oxide (GeO) x A high-dielectric-constant gate dielectric layer 128 may be disposed on and in contact with the interface oxide layer 126. In some embodiments, the high-dielectric-constant gate dielectric layer 128 may comprise a high-dielectric-constant dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium silicate (ZrSiO2), aluminum zirconium oxide (ZrAlO), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium zinc oxide (HfZnO), and yttrium oxide (Y2O3).

[0070] The work function metal layer 130 may be disposed on the high dielectric constant gate dielectric layer 128. In some embodiments, the work function metal layer 130 may comprise aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum tantalum (TaAl), aluminum tantalum carbide (TaAlC), aluminum-doped titanium, aluminum-doped titanium nitride, aluminum-doped tantalum, aluminum-doped tantalum nitride, or other aluminum-based materials suitable for n-type field-effect transistors. In some embodiments, the work function metal layer 130 may comprise titanium-based or tantalum-based nitrides or alloys that are substantially aluminum-free (e.g., without aluminum), such as titanium nitride (TiN), silicon titanium nitride (TiSN), titanium-gold (Ti-Au) alloy, titanium-copper (Ti-Cu) alloy, tantalum nitride (TaN), silicon tantalum nitride (TaSiN), tantalum-gold (Ta-Au) alloy, and tantalum-copper (Ta-Cu) alloy for p-type field-effect transistors. In some embodiments, the gate metal filling layer 132 may comprise a suitable conductive material, such as tungsten (W), titanium, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0071] Figure 2 Based on some embodiments, reference Figures 1A to 1C A flowchart of an exemplary method 200 for manufacturing the semiconductor device 100 described above. According to some embodiments, for illustrative purposes, reference will be made to... Figures 3A to 7B , Figure 8A , Figure 8B , Figure 9A , Figures 10A to 10B Description of an example manufacturing process for the semiconductor device 100 shown. Figure 2 Display operations. Figures 3A to 7B , Figure 8A , Figure 8B , Figure 9A , Figures 10A to 10B To ensure that at each stage of manufacturing, along Figure 1A Lines AA and BB are schematic cross-sectional views of semiconductor device 100. Depending on the specific application, the operations may be performed in different sequences or not at all. It should be understood that method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and only some of these other processes may be briefly described here. Figures 3A to 7B , Figure 8A , Figure 8B , Figure 9A , Figures 10A to 10B The elements that have the same reference symbols as those in Figure 1 are described above.

[0072] Please refer to Figure 2 In operation 205, a superlattice structure is formed on the fin substrate, and a polycrystalline silicon structure and source / drain regions are formed on the superlattice structure. For example, see reference... Figures 3A to 4B The superlattice structure 310 (also referred to as a nanosheet stack) can be epitaxially formed on the fin substrate 109, and the polycrystalline silicon structure 302 and source / drain regions 110 can be formed on the superlattice structure 310. The superlattice structure 310 may include alternating sacrificial nanostructured layers 304 and nanostructured layers 308. In some embodiments, the nanostructured layers 308 may contain materials similar to each other, and the sacrificial nanostructured layers 304 may contain materials similar to each other. In some embodiments, each nanostructured layer 308 may have a semiconductor material similar to or different from the substrate 106. In some embodiments, the nanostructured layers 308 may contain silicon without any significant amount of germanium (e.g., no germanium), while the sacrificial nanostructured layers 304 may contain silicon-germanium. During subsequent processing, in a gate replacement process, the polycrystalline silicon structure 302 and the sacrificial nanostructured layers 304 may be replaced by a gate structure 112.

[0073] Source / drain regions 110 are formed on the fin base 109 and on both sides of the superlattice structure 310. The source / drain regions 110 can be n-type or p-type. The formation of the source / drain regions 110 may include sequential operations (i) forming source / drain openings (not shown in the figures) through the superlattice structure 310, the source / drain openings being on the portion of the fin base 109 not below the polysilicon structure 302, such as... Figure 4A and Figure 4B As shown; and (ii) epitaxially growing n-type or p-type semiconductor materials in the source / drain openings, such as Figure 4A and Figure 4B As shown. In some embodiments, the internal spacer 115 may be formed between operation (i) and operation (ii) of the source / drain region 110 formation process, as... Figure 4A As shown. After forming the source / drain region 110, an etch stop layer 116 and an interlayer dielectric layer 118 can be formed on the source / drain region 110 to form Figure 4A and Figure 4B The structure.

[0074] Please refer to Figure 2 In operation 210, gate openings are formed around a nanostructured channel layer surrounding the superlattice structure. For example, please refer to... Figure 5A and Figure 5BThe gate openings 502 and 504 can be formed around the nanostructured layer 308. Gate opening 504 can be formed by removing the polysilicon structure 302. Dielectric layer 303 serves as an etch stop layer for removing the polysilicon structure 302 and prevents damage to the uppermost nanostructured layer 308. Gate opening 502 can be formed by removing dielectric layer 303 and sacrificial nanostructured layer 304. In some embodiments, sacrificial nanostructured layer 304 can be removed using a dry etching or wet etching process. After removing sacrificial nanostructured layer 304, nanostructured layer 308 is released, forming an opening for the gate electrode. During complete removal of sacrificial nanostructured layer 304, some wear may occur in nanostructured layer 308.

[0075] Please refer to Figure 2 In operation 215, in some embodiments, an etching process is performed on the nanostructured layer. For example, refer to... Figure 6A and Figure 6B The nanostructured layer 308 can be etched. The etching process isotropically removes several nanometers of the nanostructured layer 308 from all sides. The etching process may not trim the nanostructured layer 308 below the gate spacer 114 and below the internal spacer 115. The etching process can modify the gate opening 502 to form a larger gate opening 602 between adjacent nanostructured layers 308 to (a) accommodate capping layer deposition on the nanostructured layer 308 in subsequent operations, and (b) form a larger spacing for etching the capping layer in subsequent operations. Wet or dry etching techniques can be used in the etching process. For example, for a nanostructured layer 308 composed of silicon, a solution of ammonium hydroxide, hydrogen peroxide, and deionized (DI) water can be used during the etching process to isotropically remove approximately 2 nm to approximately 4 nm of silicon. The solution can also remove native oxides from the nanostructured layer 308.

[0076] Please refer to Figure 2 In operation 220, a capping layer is formed on the nanostructured layer. For example, refer to... Figures 7A to 7CThe capping layer 702 (e.g., a silicon-germanium capping layer) may be formed on the nanostructured layer 308. In some embodiments, the capping layer 702 may be a germanium (Ge) substrate. In some embodiments, the capping layer 702 may be a homogeneous silicon-germanium layer with a uniform distribution of germanium atoms. In some embodiments, each capping layer 702 may have a uniform concentration of germanium from 25 atomic% to about 100 atomic%. After the etching process of operation 215, the capping layer 702 may be selectively deposited on the nanostructured layer 308. In some embodiments, the capping layer 702 may be deposited using a low-pressure chemical vapor deposition (LPCVD) process. In some embodiments, the LPCVD process may be performed at a process pressure of less than about 100 torr and a temperature of less than about 600°C. In some embodiments, the LPCVD process may use a hydrogen-based or nitrogen-based carrier gas. In some embodiments, silane (SiH4) or dichlorosilane (SiH2Cl2) can be used as a silicon precursor gas, while germanane (GeH4) can be used as a germanium precursor gas, when depositing the capping layer 702. In some embodiments, hydrogen chloride (HCl) etchant gas can be co-flowed with the precursor gas to facilitate a selective deposition process for depositing the capping layer 702 around the nanostructured layer 308. Figure 7B As shown, in some embodiments, the capping layer 702 may have faceted surfaces due to the lattice mismatch between the capping layer 702 and the nanostructured layer 308. In some embodiments, the capping layer 702 and the nanostructured layer 308 may have a cross-sectional area. Figure 7B The germanium concentration profile of the line CC, such as Figure 7C As shown. In some embodiments, the capping layer 702 may have a uniform distribution of germanium atoms with a germanium percentage variation of less than about 1 atomic%, while the silicon nanostructured layer 308 may have a germanium concentration of 0, as... Figure 7C As shown. The thickness of the capping layer 702 depends on the spacing between adjacent nanostructured channel layers 122. For example, if the spacing between adjacent nanostructured channel layers 122 is in the range of about 4 nm to about 15 nm, then the capping layer 702 may have a thickness in the range of about 2 nm to about 7 nm.

[0077] Please refer to Figure 2 In operation 225, the capping layer undergoes a heat treatment process. For example, refer to... Figures 8A to 8CThe description describes a heat treatment process that can be applied to capping layer 702 to transform nanostructured layer 308 into nanostructured channel layer 122. In some embodiments, the heat treatment process may include using nitrogen or hydrogen as a carrier gas. In some embodiments, the heat treatment process may be an in-situ process immediately following the deposition of capping layer 702. In some embodiments, the temperature at which the heat treatment process is performed may be from about 350°C to about 650°C for about 200 seconds to about 600 seconds. In some embodiments, the temperature during the heat treatment process may be increased at a rate of about 3°C / second or faster.

[0078] In some embodiments, the nanostructured layer 308 may comprise silicon. Due to a thermal processing step, a portion of the nanostructured layer 308 may be converted to silicon-germanium. The thermal processing step diffuses germanium atoms from the capping layer 702 into the nanostructured layer 308, forming a semiconductor region 122B of the nanostructured channel layer 122, such as... Figure 8A and Figure 8B As shown. Therefore, the semiconductor region 122A (e.g., silicon region) of the nanostructured channel layer 122 can be surrounded by the semiconductor region 122B (e.g., silicon-germanium region) of the nanostructured channel layer 122, which is formed due to the thermal diffusion of germanium from the capping layer 702 to the nanostructured layer 308. The semiconductor region 122B can be surrounded by the heat-treated capping layer 702, such as... Figure 8A and Figure 8B As shown. In some embodiments, the entire nanostructured layer 308 can be transformed into silicon-germanium through a thermal treatment process, and both semiconductor regions 122A and 122B may have germanium atoms diffused from the capping layer 702.

[0079] like Figure 7C As shown, prior to the heat treatment process, the capping layer 702 may have a homogeneous or uniform distribution of germanium atoms, with a germanium percentage variation of less than about 1 atomic%. The heat treatment process may be a drive-in anneal process to drive germanium atoms into the nanostructured layer 308. The heat treatment process can be used as a thermally assisted diffusion process to drive germanium atoms from the capping layer 702 into the nanostructured layer 308.

[0080] In some embodiments, the heat treatment process can produce a germanium atom distribution spanning the thickness of the capping layer 702 and the nanostructured channel layer 122, such as... Figure 8C As shown, Figure 8C Show span Figure 8BThe germanium concentration profile of line DD. The heat treatment process can lead to a decrease in the concentration of germanium atoms in the capping layer 702 near the interface between the capping layer 702 and the nanostructured channel layer 122. This can lead to an increase in the concentration of germanium atoms in the nanostructured channel layer 122 near the interface between the nanostructured channel layer 122 and the capping layer 702. The distribution of germanium atoms in the thickness of the capping layer 702 and the nanostructured channel layer 122 can be controlled by controlling the temperature and duration of the heat treatment process. Higher temperatures and longer heat treatment processes can produce a higher concentration of germanium atoms in the semiconductor region 122B of the nanostructured channel layer 122. On the other hand, lower temperatures and shorter heat treatment processes can produce a lower concentration of germanium atoms in the semiconductor region 122B of the nanostructured channel layer 122. Furthermore, the germanium concentration profile formed after the heat treatment process also depends on the initial thickness of the capping layer 702.

[0081] like Figure 8C As shown, the germanium concentration profile can be adjusted by changing the temperature and duration of the heat treatment process. Figure 8C The results show that as the temperature (T) and duration (t) of the heat treatment process increase, a germanium concentration profile is formed, in which germanium diffuses to a greater depth in the nanostructured channel layer 122. The heat treatment process parameters (temperature T3, time t3) > (temperature T2, time t2) > (temperature T1, time t1). Therefore, the diffusion depth d3 of germanium at (T3, t3) is greater than the diffusion depth d2 of germanium at (T2, t2). Similarly, the diffusion depth d2 of germanium at (T2, t2) is greater than the diffusion depth d1 of germanium at (T1, t1).

[0082] In some embodiments, the heat treatment process may cause variations in the germanium concentration across the thickness of the semiconductor region 122B of the capping layer 702 and the nanostructured channel layer 122, such as... Figure 8C As shown, the germanium concentration in the outer layer of capping layer 702 can be higher than that in the inner layer of capping layer 702. The germanium concentration can be further reduced in semiconductor region 122B than in semiconductor region 122A, which is closer to the nanostructured channel layer 122. This variation in the Ge concentration across capping layer 702 and nanostructured channel layer 122 can be used to control the etching rate during subsequent selective etching processes for complete or partial removal of capping layer 702, since regions with higher germanium concentrations have higher etching rates compared to regions with lower germanium concentrations. Therefore, the etching rate of silicon-germanium can decrease as the germanium concentration in capping layer 702 decreases from the outer surface towards nanostructured channel layer 122. Compared to capping layer 702, the silicon-germanium etching process can have higher etching selectivity for semiconductor regions 122A and 122B of nanostructured channel layer 122.

[0083] Please refer to Figure 2In operation 230, an etching process is performed on the capping layer. For example, refer to... Figure 9A and Figure 9B The description describes an etching process that can be performed on capping layer 702 to partially remove capping layer 702, thereby forming capping layer 124 of nanostructured channel structure 125. In some embodiments, the etching process can completely remove capping layer 702. In some embodiments, the etching process can include a wet etching process. In some embodiments, the wet etching process can include the use of an etchant having an oxidant, a fluorine-based etchant, and an inhibitor. In some embodiments, the oxidant can be a peroxide or other oxidant that can selectively oxidize germanium and convert germanium in capping layer 702 to germanium oxide (GeO2) (soluble in water). In some embodiments, the fluorine-based etchant can include at least one of hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), or ammonium fluoride (NH4F), but is not limited thereto. In some embodiments, the inhibitor can include silanol to inhibit silicon removal and provide selectivity for silicon. In some embodiments, the wet etching process can be used to achieve a Si:SiGe etching selectivity of about 1:40.

[0084] In some embodiments, the etching process in operation 230 may include a dry etching process using a fluorine-based gas. In some embodiments, the fluorine-based gas may include fluorine (F2), HF, fluoroform (CHF3), or methylfluoride (CH3F). These fluorine-based gases can react with silicon to form silane tetrafluoride (SiF4) and with germanium to form germanium tetrafluoride (GeF4). The etching selectivity between silicon and germanium can be based on the bond energy differences between Si-Si, Si-Ge, and Ge-Ge bonds. Because Si-Si bonds are stronger than Si-Ge and Ge-Ge bonds, the dry etching process can selectively etch silicon and germanium compared to the silicon in the nanostructured channel layer 122. To further enhance the etching selectivity between silicon and germanium, a lower process temperature can be used.

[0085] Figure 9B The germanium concentration profile is shown across line EE 9A after the etched capping layer 702 forms capping layer 124. (See image.) Figure 9B As shown, the etching process can be terminated after the critical germanium concentration Cth across line EE is detected. Figure 9BAs shown, at the end of the etching process, the nanostructured channel structure 125 may have a semiconductor region 122A (silicon region) and a semiconductor region 122B (germanium-doped region) of the nanostructured channel layer 122, as well as a heat-treated capping layer 124. At higher temperatures (T) and durations (t) of the heat treatment process, since germanium can diffuse to a greater depth d3, the nanostructured channel structure 125 may have a thinner semiconductor region 122A (silicon region) compared to the thickness of the semiconductor region 122A (silicon region) at lower temperatures (T) and durations (t).

[0086] Figure 9C This shows the change in silicon-germanium etching rate relative to the germanium concentration in the capping layer 702. For example... Figure 9C As shown, the endpoint of a dry or wet etching process for etching the silicon-germanium capping layer 702 can be marked by the germanium concentration in the capping layer at which the silicon-germanium etching rate is approximately zero. The germanium concentration in the capping layer 702 at which the etching rate is approximately zero can be referred to as the critical germanium concentration Cth. The critical germanium concentration Cth can be varied by changing the wet or dry etching parameters, which include the mixing ratio of components including the etchant, the process temperature, and the pH value. The critical germanium concentration Cth can be the percentage of germanium in the outermost region of the capping layer 702 in contact with the etchant, at which the etching rate is approximately zero. For example, if the etching process has a critical value of 25 atomic% germanium, then the outermost capping layer 702 may have 25 atomic% germanium at the endpoint of the etching process. The etching process can be adjusted to have different critical germanium concentrations Cth. For example, if the etching process can be adjusted to have a critical value of approximately 28 atomic% germanium, then the outermost region of the capping layer 702 may have approximately 28 atomic% germanium at the endpoint of the etching process. Therefore, the parameters of the etching process can determine the germanium concentration in the outermost region of the capping layer 702. In some embodiments, at the end of the etching process, for an initial capping layer 702 thickness in the range of about 1 nm to about 3 nm, the combined thickness of semiconductor region 122A (silicon region) and semiconductor region 122B (germanium-doped region) can be in the range of about 5 nm to about 10 nm. In some embodiments, the thickness of semiconductor region 122A (silicon region) can be equal to the thickness of semiconductor region 122B (germanium-doped region).

[0087] Please refer to Figure 2 In operation 235, a gate structure is formed in the gate opening. For example, refer to... Figure 10A and Figure 10B The gate structure 112 may be formed in the gate openings 504 and 602 surrounding the nanostructured channel structure 125. The formation of the gate structure 112 may include the following sequential operations: (i) forming an interface oxide layer 126 on the nanostructured channel structure 125 (e.g., ...). Figure 10A and Figure 10B(as shown), or without the capping layer 124, forming an interface oxide layer 126 on the nanostructured channel layer 122, (ii) depositing a high-dielectric-constant gate dielectric layer 128 on the interface oxide layer 126, as shown. Figure 10A and Figure 10B As shown, (iii) a work function metal layer 130 is deposited on the high dielectric constant gate dielectric layer 128, as follows: Figure 10A and Figure 10B As shown, (iv) a gate metal filling layer 132 is deposited on the work function metal layer 130, as follows: Figure 10A and Figure 10B As shown, and (v) a chemical mechanical polishing (CMP) process is performed to make the top surfaces of the high dielectric constant gate dielectric layer 128, the work function metal layer 130, and the gate metal fill layer 132 coplanar with each other.

[0088] In some embodiments, the interface oxide layer 126 may be formed on the exposed surface of the capping layer 124 of the nanostructured channel structure 125 in the gate openings 502 and 504, or (if there is no capping layer 124) on the exposed surface of the semiconductor region 122B of the nanostructured channel layer 122 in the gate openings 502 and 504. In some embodiments, the interface oxide layer 126 may be formed by exposing the capping layer 124 or the semiconductor region 122B to an oxidizing environment. The oxidizing environment may include a combination of ozone (O3), ammonium hydroxide, hydrogen peroxide and water (SC1 solution) and / or a mixture of hydrochloric acid, hydrogen peroxide and water (SC2 solution).

[0089] In some embodiments, the deposition of the high-dielectric-constant gate dielectric layer 128 may include depositing a high-dielectric-constant gate dielectric material on the interface oxide layer 126. In some embodiments, the high-dielectric-constant gate dielectric layer 128 may be formed by an atomic layer deposition process using hafnium chloride (HfCl4) as a precursor in a temperature range of about 250°C to about 350°C. In some embodiments, an annealing process may be performed after the formation of the high-dielectric-constant gate dielectric layer 128 to improve the electrical characteristics and / or reliability of the interface oxide layer 126 and / or the high-dielectric-constant gate dielectric layer 128.

[0090] In some embodiments, the deposition of the gate metal fill layer 132 may include depositing a fluorine-free metal layer (e.g., a fluorine-free tungsten (FFW) layer) in the gate openings 502 and 504. The deposition of the fluorine-free metal layer may involve depositing the fluorine-free metal layer using an atomic layer deposition process at a temperature ranging from about 400°C to about 500°C, using tungsten pentachloride (WCl5) or tungsten hexachloride (WCl6) and H2 as precursors. In some embodiments, the fluorine-free metal layer may be deposited in an atomic layer deposition process of about 160 cycles to about 320 cycles, one cycle of which may include the following consecutive cycles: (i) a first precursor gas (e.g., WCl5 or WCl6) gas flow, (ii) a first gas flushing process, (iii) a second precursor gas (e.g., H2) gas flow, and (iv) a second gas flushing process.

[0091] This invention provides an example of a multi-critical voltage (Vt) device having a field-effect transistor (e.g., semiconductor device 100) with an improved nanostructured channel configuration. In some embodiments, the nanostructured channel structure (e.g., nanostructured channel structure 125) includes a nanostructured channel layer (e.g., nanostructured channel layer 122) having a silicon (Si) region (e.g., semiconductor region 122A) and a germanium (Ge) doped region (e.g., semiconductor region 122B) surrounding the silicon region. In some embodiments, the nanostructured channel structure may include a capping layer (e.g., capping layer 124) surrounding the germanium doped region. The introduction of germanium atoms into the nanostructured channel layer improves the performance of the p-type field-effect transistor (PFET) device by inducing higher compressive stress in the nanostructured channel layer. The higher compressive stress in the germanium-implanted nanostructured channel layer enhances carrier mobility and higher on-current in the p-type field-effect transistor device. Germanium-implanted nanostructured channel layers provide superior p-type field-effect transistor threshold voltage control in miniaturized advanced device structures (e.g., fin field-effect transistors or fully wound gate field-effect transistors). This invention also provides a method for forming nanostructured channel structures for miniaturized device structures (e.g., method 200). This method is particularly targeted at forming germanium-doped regions and / or capping layers on nanostructured channel layers for devices with spacing constraints between adjacent nanostructured channel layers.

[0092] In some embodiments, the method includes forming a superlattice structure comprising a first nanostructured layer and a second nanostructured layer on a fin substrate; forming a polycrystalline silicon structure on the superlattice structure; removing the second nanostructured layer to form a first gate opening; removing the polycrystalline silicon structure to form a second gate opening; forming a capping layer on the first nanostructured layer; modifying the first nanostructured layer to form a nanostructured channel layer comprising an undoped semiconductor region and a doped semiconductor region surrounding the undoped semiconductor region; selectively etching the exterior of the capping layer using an etching process having etch selectivity based on the germanium (Ge) concentration in the capping layer; and forming a gate structure surrounding the nanostructured channel layer in the first gate opening and the second gate opening. The outermost region of the doped semiconductor region has a higher concentration of dopant than the innermost region of the doped semiconductor region.

[0093] In some other embodiments, the step of modifying the first nanostructured layer includes doping an outer region of the first nanostructured layer with germanium atoms from the capping layer to form a doped semiconductor region.

[0094] In some other embodiments, the method described above also includes etching a portion of the doped semiconductor region.

[0095] In some other embodiments, the step of forming the capping layer includes epitaxially growing a silicon-germanium layer on the first nanostructured layer.

[0096] In some other embodiments, the method further includes etching the exterior of the cap layer using an etchant comprising an oxidant, a fluorine-based etchant, and a silicon inhibitor.

[0097] In some other embodiments, the method described above also includes etching a capping layer to expose the surface of the doped semiconductor region.

[0098] In some other embodiments, the method described above further includes etching a capping layer to form a modification capping layer surrounding the doped semiconductor region.

[0099] In some embodiments, the method includes forming a capping layer on a nanostructured layer; annealing the capping layer to form a nanostructured channel layer comprising germanium-free regions and germanium-doped regions; selectively etching the exterior of the capping layer having a germanium concentration higher than a critical germanium concentration to form a modified capping layer on the nanostructured channel layer; and forming a fully wound gate structure on the modified capping layer. The concentration of germanium atoms in the germanium-doped regions varies along the thickness of the germanium-doped regions.

[0100] In some other embodiments, the step of annealing the capping layer includes annealing the nanostructured layer at a temperature of about 550°C to about 650°C.

[0101] In some other embodiments, the method further includes forming a nanostructured channel layer of predetermined thickness by controlling at least one of: the duration and temperature of annealing; and the composition, pH, or temperature of a silicon-germanium etchant during selective etching of the exterior of the capping layer.

[0102] In some other embodiments, the step of controlling the composition of the silicon-germanium etchant includes controlling the mixing ratio of the oxidant, fluorine-based etchant, and inhibitor.

[0103] In some other embodiments, the step of forming the fully wound gate structure includes the top surface of an oxide-modified capping layer.

[0104] In some other embodiments, the step of forming the fully wound gate structure includes the top surface of the germanium oxide doped region.

[0105] In some other embodiments, the step of selectively etching the capping layer includes removing multiple facets of the capping layer.

[0106] In some embodiments, the semiconductor device includes a substrate; a fin substrate disposed on the substrate; a nanostructured channel structure disposed on the fin substrate; and a gate structure surrounding the nanostructured channel structure. The nanostructured channel structure includes a germanium-free region; a germanium-doped region surrounding the germanium-free region; and a capping layer surrounding the germanium-doped region. The germanium-doped region includes a germanium concentration varying along the thickness of the germanium-doped region.

[0107] In some other embodiments, the capping layer comprises a silicon-germanium layer.

[0108] In some other embodiments, the germanium-free region comprises a germanium-free silicon region.

[0109] In some other embodiments, the germanium concentration in the germanium-doped region is lower than the germanium concentration in the capping layer.

[0110] In some other embodiments, a capping layer contacts the gate structure.

[0111] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various perspectives. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: One base; A fin base is disposed on the base; A nanostructured channel structure is disposed on the fin base, the nanostructured channel structure comprising: One germanium-free region; A germanium-doped region surrounding a germanium-free region, wherein the germanium-doped region includes a germanium concentration varying along the thickness of the germanium-doped region; and A capping layer surrounds the germanium-doped region; and A gate structure surrounds the nanostructured channel structure.

2. The semiconductor device as claimed in claim 1, characterized in that, The capping layer contacts the gate structure.

3. The semiconductor device as claimed in claim 1, characterized in that, The capping layer is in direct contact with the fin base.

4. The semiconductor device as claimed in claim 1 or 2, characterized in that, The capping layer is located between the germanium-doped region and the fin base.

5. The semiconductor device as claimed in claim 1 or 2, characterized in that, The capping layer is in direct contact with an interface oxide layer of the gate structure.

6. The semiconductor device as claimed in claim 5, characterized in that, The interface oxide layer covers the sidewalls of the fin base.

7. The semiconductor device as claimed in claim 5, characterized in that, The interface oxide layer is in direct contact with the capping layer and the germanium-doped region.

8. The semiconductor device as claimed in claim 1 or 2, characterized in that, Also includes: An internal spacer is adjacent to the gate structure.

9. The semiconductor device as claimed in claim 8, characterized in that, The internal spacer is in direct contact with the cover layer.

10. The semiconductor device as claimed in claim 8, characterized in that, The internal spacer separates the germanium-doped region.

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