Semiconductor device

Abstract

A semiconductor device includes a plurality of nanostructured transistor layers in a stacked or vertical configuration. Each nanostructure transistor layer comprises at least one n-type metal oxide semiconductor nanostructure transistor and at least one p-type metal oxide semiconductor nanostructure transistor. Nanostructure transistor layers may be fabricated such that n-type metal oxide semiconductor nanostructure transistors and p-type metal oxide semiconductor nanostructure transistors of two or more nanostructure transistor layers have one or more different characteristics, such as the number of nanostructure channels. This can optimize the performance of n-type metal oxide semiconductor nanostructured transistors and p-type nanostructured transistors of different nanostructured transistor layers for different performance parameters.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices in which the number of nanostructure channel layers in different nanostructure transistor layers varies. Background Technology

[0002] As semiconductor device manufacturing methods advance and process node sizes shrink, short-channel effects such as hot carrier degradation, barrier reduction, quantum confinement, and other effects can impact transistors. Furthermore, as transistor gate sizes shrink for smaller process nodes, source / drain electron tunneling increases, leading to increased transistor turn-off current (the current flowing through the transistor channel when the transistor is turned off). Nanostructured transistors (such as nanowires, nanosheets, nanoribbons, multi-bridge channels, and fully wound gate devices) are strong candidates for overcoming short-channel effects at smaller process nodes. Compared to other types of transistors, nanostructured transistors can effectively reduce short-channel effects and improve carrier mobility. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0004] Some embodiments described herein provide a semiconductor device. The semiconductor device is characterized by including a first nanostructure transistor layer. The first nanostructure transistor layer includes a plurality of first nanostructure channel layers extending in a first direction and disposed in a second direction, the second direction being approximately perpendicular to the first direction. The first nanostructure channel layer includes a first number of nanostructure channel layers. The first nanostructure transistor layer includes a first gate structure covering each first nanostructure channel layer. The first nanostructure transistor layer includes a first p-type source / drain region adjacent to the first nanostructure channel layer; and a first n-type source / drain region adjacent to the first nanostructure channel layer. The semiconductor device includes a second nanostructure transistor layer located on the first nanostructure transistor layer in the second direction. The second nanostructure transistor layer includes a plurality of second nanostructure channel layers extending in the first direction and disposed in the second direction, wherein the second nanostructure channel layers include a second number of nanostructure channel layers, and wherein the first number is different from the second number. The second nanostructure transistor layer includes a second gate structure covering each second nanostructure channel layer. The second nanostructure transistor layer includes a second p-type source / drain region adjacent to the second nanostructure channel layer; and a second n-type source / drain region adjacent to the second nanostructure channel layer.

[0005] According to one embodiment of the present invention, it further includes: a first interconnect structure coupled to the first nanostructure transistor layer; and a second interconnect structure coupled to the second nanostructure transistor layer.

[0006] According to one embodiment of the present invention, it further includes: a bonding dielectric layer located between the first nanostructure transistor layer and the second nanostructure transistor layer in the second direction.

[0007] According to one embodiment of the present invention, the first nanostructure transistor layer is located between the bonding dielectric layer and the first interconnect structure; and the second nanostructure transistor layer is located between the bonding dielectric layer and the second interconnect structure.

[0008] According to one embodiment of the present invention, the first interconnect structure is located between the first nanostructure transistor layer and the second nanostructure transistor layer in the second direction; and the second nanostructure transistor layer is located between the first interconnect structure and the second interconnect structure in the second direction.

[0009] Some embodiments described herein provide a semiconductor device. The semiconductor device is characterized by including a first nanostructure transistor layer. The first nanostructure transistor layer includes a plurality of first nanostructure channel layers extending in a first direction and disposed in a second direction, the second direction being approximately perpendicular to the first direction, wherein the first nanostructure channel layers include a first number of nanostructure channel layers. The first nanostructure transistor layer includes a first gate structure covering each first nanostructure channel layer. The first nanostructure transistor layer includes a first p-type source / drain region adjacent to the first nanostructure channel layer; and a first n-type source / drain region adjacent to the first nanostructure channel layer. The semiconductor device includes a second nanostructure transistor layer. The second nanostructure transistor layer includes a plurality of second nanostructure channel layers extending in a first direction and disposed in a second direction, wherein the second nanostructure channel layers include a second number of nanostructure channel layers, and the first number is different from the second number. The second nanostructure transistor layer includes a second gate structure covering each second nanostructure channel layer. The second nanostructure transistor layer includes a second p-type source / drain region adjacent to the second nanostructure channel layer; and a second n-type source / drain region adjacent to the second nanostructure channel layer. The semiconductor device includes a first interconnect structure coupled to a first nanostructure transistor layer. The semiconductor device also includes a second interconnect structure coupled to a second nanostructure transistor layer. A bonding dielectric layer is located between the first and second nanostructure transistor layers, wherein the first nanostructure transistor layer, the second nanostructure transistor layer, the first interconnect structure, the second interconnect structure, and the bonding dielectric layer are disposed in a second direction.

[0010] According to one embodiment of the present invention, it further includes: a conductive structure coupling the first interconnect structure and the second interconnect structure, wherein the conductive structure extends continuously between the first interconnect structure and the second interconnect structure.

[0011] According to one embodiment of the present invention, the conductive structure extends through the first nanostructure transistor layer, the second nanostructure transistor layer and the bonding dielectric layer.

[0012] According to one embodiment of the present invention, the conductive structure extends through the second nanostructure transistor layer and the bonding dielectric layer.

[0013] According to one embodiment of the present invention, the first number is greater than the second number. Attached Figure Description

[0014] Figure 1 The accompanying drawings illustrate, as one example, an environment in which the systems and / or methods described herein may be implemented.

[0015] Figure 2 The accompanying drawing shows, for example, the semiconductor device described herein.

[0016] Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 The attached figure shows an example of implementing the fin formation process described herein.

[0017] Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 The attached diagram illustrates an example of implementing the shallow trench isolation process described herein.

[0018] Figure 5 , Figure 6-1 , Figure 6-2 and Figure 6-3 The attached figure shows an example of implementing the dummy gate structure formation process described herein.

[0019] Figure 7A-1 , Figure 7A-2 , Figure 7A-3 , Figure 7B-1 , Figure 7B-2 , Figure 7B-3 , Figure 7C-1 , Figure 7C-2 , Figure 7C-3 , Figure 7D-1 , Figure 7D-2 and Figure 7D-3 The attached diagram illustrates, as in one example, the source / drain recess formation process and the inner spacer formation process described herein.

[0020] Figure 8-1 , Figure 8-2 and Figure 8-3 The attached diagram illustrates, as an example, the source / drain formation process described herein.

[0021] Figure 9-1 , Figure 9-2 and Figure 9-3 The attached figure shows an example of implementing the interlayer dielectric layer formation process described herein.

[0022] Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , Figure 10C-2 and Figure 10C-3 The attached figure shows an example of implementing the gate replacement process described herein.

[0023] Figures 11A to 11L As an example, the figure shows the implementation of multiple stacked nanostructured transistor layers described herein formed in a semiconductor device.

[0024] Figures 12A to 12C As an example, the conductive structure described herein is formed in a semiconductor device containing multiple stacked nanostructure transistor layers.

[0025] Figures 13A to 13F As an example, the conductive structure described herein is formed in a semiconductor device containing multiple stacked nanostructure transistor layers.

[0026] Figures 14A to 14E As an example, the figure shows the implementation of multiple stacked nanostructured transistor layers described herein formed in a semiconductor device.

[0027] Figures 15A to 15C As an example, the conductive structure described herein is formed in a semiconductor device containing multiple stacked nanostructure transistor layers.

[0028] Figure 16 The accompanying drawings are for one example of the components of one or more devices described herein.

[0029] Figure 17 As an example, a flowchart of the relevant process for forming the semiconductor device described herein is provided.

[0030] The attached figures are labeled as follows:

[0031] AA, BB, CC: Cross-section

[0032] 100: Environment

[0033] 102: Sedimentation tools

[0034] 104: Exposure Tools

[0035] 106: Developing tools

[0036] 108: Etching Tools

[0037] 110: Flattening tool

[0038] 112: Plating tools

[0039] 114: Joining tools

[0040] 116: Wafer / Die Transfer Tool

[0041] 200: Semiconductor devices

[0042] 205: Semiconductor substrate

[0043] 210: Countertop area

[0044] 215: Shallow trench isolation zone

[0045] 220: Nanostructured Channels

[0046] 225: Source / Drain Region

[0047] 225a: p-type source / drain region

[0048] 225b: n-type source / drain region

[0049] 230: Buffer

[0050] 235,325: Cap layer

[0051] 240: Gate structure

[0052] 245: Inner spacer

[0053] 250: Interlayer dielectric layer

[0054] 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500: Implementation methods

[0055] 305: Layered stacking

[0056] 310: First Floor

[0057] 315: Second Floor

[0058] 320, 515: Hard mask layer

[0059] 330: Oxide layer

[0060] 335: Nitride layer

[0061] 340: Part

[0062] 345: Fin-like structure

[0063] 345a: First group of fin-like structures

[0064] 345b: Second group of fin-like structures

[0065] 405,1140: Padding

[0066] 410, 1125, 1150, 1165: Dielectric layer

[0067] 505: Dummy Gate Structure

[0068] 510: Gate layer

[0069] 520: Spacer layer

[0070] 525,1010: Gate dielectric layer

[0071] 705: Source / Drain Recess

[0072] 710: Void

[0073] 715: Insulation layer

[0074] 805: Contact Etching Stop Layer

[0075] 1005: Opening

[0076] 1105a: First nanostructure transistor layer

[0077] 1105b: Second nanostructure transistor layer

[0078] 1110: Bonding dielectric layer

[0079] 1115a: First internal interconnect structure

[0080] 1115b: Second internal connection structure

[0081] 1120, 1160: Etching stop layer

[0082] 1130: Depression

[0083] 1135: Silicide layer

[0084] 1145: Source / Drain Contact

[0085] 1155: Source / Drain interconnect

[0086] 1170: Metallization layer

[0087] 1175: Conductive Structure

[0088] 1305: Part One

[0089] 1600: Device

[0090] 1610: Busbar

[0091] 1620: Processor

[0092] 1630: Memory

[0093] 1640: Input Components

[0094] 1650: Output Component

[0095] 1660: Communication components

[0096] 1700: Process

[0097] 1705, 1710, 1715, 1720, 1725, 1730, 1735, 1740, 1745, 1750: Steps Detailed Implementation

[0098] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity.

[0099] The following disclosure provides many different embodiments or examples to implement different features of this invention. The following disclosure illustrates specific examples of the various components and their arrangements for simplification. These specific examples are not intended to limit the embodiments of this utility model. For example, if the embodiments of this utility model describe a first structure formed on a second structure, it means that the first structure may be in direct contact with the second structure, or an additional structure may be formed between the first and second structures, so that the first and second structures are not in direct contact. Furthermore, the use of repeated reference numerals in various embodiments of this utility model for simplification or clarity does not imply that structures with the same reference numerals in various embodiments and / or arrangements have the same relative relationship.

[0100] In addition, spatial relative terms such as “below,” “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures in the accompanying drawings and other elements or structures. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0101] Semiconductor devices may include p-type metal-oxide-semiconductor (MOS) nanostructure transistors and n-type MOS nanostructure transistors. Integrating p-type MOS nanostructure transistors and n-type MOS nanostructure transistors onto the same semiconductor device enables complementary metal-oxide-semiconductor (CMOS) integrated circuits. In the semiconductor industry, CMOS integrated circuits can be used in many applications such as microprocessors (e.g., central processing units or graphics processing units), memory devices, digital logic circuits, image sensors (e.g., CMOS image sensors), radio frequency circuits, and / or other examples.

[0102] In some examples, a semiconductor device may include n-type metal-oxide-semiconductor (MOS) nanostructure transistors (NTS transistors) and p-type MOS transistors (PMTs) arranged side-by-side on the same horizontal plane on the same substrate. While this allows for the realization of complementary MOS integrated circuits (COM) within a semiconductor device, the horizontal arrangement of the NMS and PMTs may hinder advancements in semiconductor devices containing COM integrated circuits (e.g., transistor density, power consumption, and / or processing speed). For instance, the NMS and PMTs may be limited by the same design rules, meaning they can only be optimized for power efficiency or processing speed.

[0103] In some embodiments described herein, the semiconductor device includes a complementary field-effect transistor (CFPT) structure. The CFPT structure includes a plurality of complementary metal-oxide-semiconductor (CMOS) layers stacked or vertically arranged in a direction approximately perpendicular to the substrate of the semiconductor device. Each CMOS layer includes at least one n-type CMOS nanostructure transistor and at least one p-type CMOS nanostructure transistor. The performance of the n-type and p-type CMOS nanostructure transistors in each CMOS layer can be optimized for specific performance parameters. For example, the number of nanostructure channels in the n-type and p-type CMOS nanostructure transistors of the first CMOS layer may differ from the number of nanostructure channels in the second CMOS layer. A higher number of nanostructure channels in the n-type or p-type CMOS nanostructure transistors in the CMOS layer can provide a larger drive current and faster switching speed. On the other hand, n-type or p-type metal-oxide-semiconductor nanostructure transistors in complementary metal-oxide-semiconductor (CMOS) layers use fewer nanostructure channels, resulting in lower power consumption. In this approach, the power consumption, processing speed, and / or another performance parameter of different CMOS layers can be optimized.

[0104] Figure 1 As an example, the accompanying drawings illustrate an environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, environment 100 may include multiple semiconductor process tools such as deposition tools 102 to bonding tools 114 and wafer and / or die transfer tools 116. These multiple semiconductor process tools, such as deposition tools 102 to bonding tools 114, may include deposition tool 102, exposure tool 104, developing tool 106, etching tool 108, planarization tool 110, plating tool 112, bonding tool 114, and / or another semiconductor process tool. The tools included in the example of environment 100 may be found in semiconductor cleanrooms, semiconductor foundries, semiconductor fabrication plants, manufacturing plants, and / or other facilities.

[0105] The deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices for depositing various materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coater for depositing a photoresist layer onto a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition tool, such as a plasma-assisted chemical vapor deposition tool, a high-density plasma-assisted chemical vapor deposition tool, a sub-pressure chemical vapor deposition tool, a low-pressure chemical vapor deposition tool, an atomic layer deposition tool, a plasma-assisted atomic layer deposition tool, or another type of chemical vapor deposition tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition tool, such as a sputtering tool or another type of physical vapor deposition tool. In some embodiments, the deposition tool 102 includes an epitaxial tool configured to epitaxially grow layers and / or regions. In some embodiments, examples of the environment 100 include various deposition tools 102.

[0106] Exposure tool 104 is a semiconductor process tool that can be irradiated with a photoresist layer by a radiation source such as an ultraviolet light source (e.g., deep ultraviolet light source, extreme ultraviolet light source, and / or similar light source), an X-ray source, an electron beam source, and / or similar light source. Exposure tool 104 can be irradiated with a radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, patterns for forming one or more structures of a semiconductor device, patterns for etching various portions of a semiconductor device, and / or similar patterns. In some embodiments, exposure tool 104 includes a scanner, a stepper, and / or similar types of exposure tools.

[0107] The developing tool 106 is a semiconductor process tool that develops the photoresist layer exposed to the X-ray source to develop the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 can remove the unexposed portions of the photoresist layer to develop the pattern. In some embodiments, the developing tool 106 can remove the exposed portions of the photoresist layer to develop the pattern. In some embodiments, the developing tool 106 can use a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer to develop the pattern.

[0108] Etching tool 108 is a semiconductor process tool that can etch various materials from substrates, wafers, or semiconductor devices. For example, etching tool 108 may include wet etching tools, dry etching tools, and / or similar tools. In some embodiments, etching tool 108 includes a chamber for filling with an etchant, and a substrate may be placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, etching tool 108 may employ plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may use ionized gases to etch one or more portions isotropically or directionally. In some embodiments, etching tool 108 includes a plasma-based ashing stage to remove photoresist material and / or another material.

[0109] Planarization tool 110 is a semiconductor process tool that can grind or planarize various layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical polishing tool and / or another planarization tool that can grind or planarize layers or surfaces of deposited or plated materials. Planarization tool 110 can grind or planarize the surface of a semiconductor device using a combination of chemical and mechanical forces (such as chemical etching and free abrasive polishing). Planarization tool 110 may employ abrasives and corrosive chemical polishing slurries, along with a polishing pad and a retaining ring (typically larger in diameter than the semiconductor device). The polishing pad and semiconductor device may be pressed together by a dynamic polishing head and held by the retaining ring. The dynamic polishing head may rotate along different axes of rotation to remove material and flush any irregularities in the semiconductor device, making the semiconductor device smooth or planar.

[0110] The plating tool 112 is a semiconductor process tool that can plate one or more metals onto a substrate (such as a wafer, semiconductor device, and / or the like) or a portion thereof. For example, the plating tool 112 may include a copper plating apparatus, an aluminum plating apparatus, a nickel plating apparatus, a tin plating apparatus, an electroplating apparatus for compound materials or alloys (such as tin-silver, tin-lead, and / or the like), and / or an electroplating apparatus for one or more other types of conductive materials, metals, and / or similar materials.

[0111] The bonding tool 114 is a semiconductor process tool that can bond two or more wafers (or two or more semiconductor substrates, or two or more semiconductor devices) together, bond layers to a substrate, bond multiple layers together, and / or similar processes. For example, the bonding tool 114 may include a eutectic bonding tool that can form a eutectic bond between two or more wafers. In another example, the bonding tool can bond two or more layers or substrates together to form a dielectric layer-to-dielectric layer bond and / or a metal-to-metal bond.

[0112] The wafer and / or die transfer tool 116 includes mobile robots, robotic arms, light rail or railcars, overhead cranes, automated material handling systems, and / or other devices used for transferring substrates and / or semiconductor devices between semiconductor process tools such as deposition tool 102 to bonding tool 114, between process chambers of the same semiconductor tool, and / or from other locations (such as wafer racks, storage chambers, or another location) or to other locations. In some embodiments, the wafer and / or die transfer tool 116 is a programmable tool configured to transport along a specific path and / or operate automatically or semi-automatically. In some embodiments, the environment 100 includes multiple wafer and / or die transfer tools 116.

[0113] For example, the wafer and / or die transfer tool 116 may be included in a clustering tool or another tool having multiple process chambers, and may be configured to transfer substrates and / or semiconductor devices between multiple process chambers, between process chambers and buffer zones, between process chambers and interface tools (such as equipment front-end modules), between process chambers and transfer carriers (such as front-opening wafer transfer boxes), and / or similar arrangements. In some embodiments, the wafer and / or die transfer tool 116 may be included in a multi-chamber (or clustering) deposition tool 102, which may include multiple pre-cleaning process chambers (for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from the substrate and / or semiconductor devices) and multiple deposition process chambers (such as process chambers for depositing different types of materials, or process chambers for performing different types of deposition steps). In these embodiments, the wafer and / or die transfer tool 116 is configured to transfer the substrate and / or semiconductor device between the process chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partially removing the vacuum) between the process chambers in the deposition tool 102 and / or between deposition steps, as described herein.

[0114] As described herein, semiconductor process tools such as deposition tools 102 to bonding tools 114 and / or wafer and / or die transfer tools 116 can be used to perform combinations of steps to form one or more portions of a nanostructured transistor, one or more portions of a complementary metal-oxide-semiconductor layer, and / or one or more portions of the semiconductor device described herein. Semiconductor process tools such as deposition tools 102 to bonding tools 114 and / or wafer and / or die transfer tools 116 can be used to form a plurality of first nanostructured channel layers from a first nanostructured layered stack, the arrangement orientation of which is approximately perpendicular to the semiconductor substrate of the semiconductor device, wherein the plurality of first nanostructured channel layers include a first number of nanostructured channel layers; forming a first p-type source / drain region adjacent to the first nanostructured channel layer; forming a first n-type source / drain region adjacent to the plurality of first nanostructured channel layers; forming a first gate structure to cover each first nanostructured channel layer, wherein the first nanostructured channel layer, the first p-type source / drain region, the first n-type source / drain region, and the first gate structure are included in the first nanostructured transistor layer of the semiconductor device; and forming a bonding dielectric layer. On a first nanostructure transistor layer; a bonding dielectric layer is used to bond a second nanostructure layer stacked onto the first nanostructure transistor layer; a plurality of second nanostructure channel layers are formed from the second nanostructure layer stack, the arrangement direction of which is approximately perpendicular to the semiconductor substrate, wherein the second nanostructure channel layer includes a second number of nanostructure channel layers, and the second number is different from the first number; a second p-type source / drain region is formed adjacent to the second nanostructure channel layer; a second n-type source / drain region is formed adjacent to the second nanostructure channel layer; and / or a second gate structure is formed to cover each second nanostructure channel layer, wherein the second nanostructure channel layer, the second p-type source / drain region, the second n-type source / drain region, and the second gate structure are included in the second nanostructure transistor layer of the semiconductor device.

[0115] In some embodiments, semiconductor process tools such as deposition tools 102 to bonding tools 114 and / or wafer and / or die transfer tools 116 can be used for mating. Figure 3A-1 , Figure 3A-2 , Figure 3B-1 , Figure 3B-2 , Figure 4A-1 , Figure 4A-2 , Figure 4B-1 , Figure 4B-2 , Figure 5 , Figure 6-1 , Figure 6-2 , Figure 6-3 , Figure 7A-1 , Figure 7A-2 , Figure 7A-3 , Figure 7B-1 , Figure 7B-2 , Figure 7B-3 , Figure 7C-1 , Figure 7C-2 , Figure 7C-3 , Figure 7D-1 , Figure 7D-2 , Figure 7D-3 , Figure 8-1 , Figure 8-2 , Figure 8-3 , Figure 9-1 , Figure 9-2 , Figure 9-3 , Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , Figure 10C-2 , Figure 10C-3 , Figures 11A to 11L , Figures 12A to 12C , Figures 13A to 13F , Figures 14A to 14E , Figures 15A to 15C and / or Figure 17 One or more steps are described.

[0116] Figure 1 The number and configuration of devices shown are for illustrative purposes only. In practice, there may be additional devices, fewer devices, different devices, or devices with different configurations (compared to combinations). Figure 1 (The device described). Furthermore, Figure 1 The two or more devices shown can be implemented in a single device, or Figure 1 The single device shown can be implemented in multiple distributed devices. A group of devices in environment 100 (such as one or more devices) can additionally or alternatively perform one or more functions performed by another group of devices in environment 100.

[0117] Figure 2 This is an accompanying drawing of a portion of the semiconductor device 200 described herein. The portion of the semiconductor device 200 includes a nanostructured transistor layer comprising a plurality of nanostructured transistors. The nanostructured transistors of the nanostructured transistor layer include at least one p-type metal-oxide-semiconductor (MOS) nanostructured transistor and at least one n-type MOS nanostructured transistor disposed in a complementary MOS integrated circuit such as a complementary MOS inverter circuit (e.g., a complementary MOS NOT gate). Therefore, the nanostructured transistor layer of the semiconductor device 200 can be considered as a complementary MOS layer. The nanostructured transistors of the semiconductor device 200 include nanostructured transistors such as nanowire transistors, nanosheet transistors, fully wound gate transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors.

[0118] As described herein, multiple nanostructured transistor layers can be stacked or vertically arranged in the semiconductor device 200. This allows the nanostructured transistors used in different nanostructured transistor layers to achieve specific performance design goals for different performance parameters. For example, the first nanostructured transistor layer can meet energy consumption parameters, such that the energy consumption of the first nanostructured transistor layer is lower than that of the second nanostructured transistor layer. The second nanostructured transistor layer can meet switching speed parameters. In this approach, a complementary metal-oxide-semiconductor (CMOS) integrated circuit requiring a lower switching speed can be implemented in the first nanostructured transistor layer to achieve higher power efficiency (compared to a CMOS integrated circuit with a higher switching speed requirement). A CMOS integrated circuit with a higher switching speed requirement can be implemented in the second nanostructured transistor layer.

[0119] Semiconductor device 200 may include one or more Figure 2 Additional devices, structures, and / or layers not shown. For example, semiconductor device 200 may include additional layers and / or dies formed on... Figure 2 The semiconductor device 200 shown is on a layer above and / or below a portion of the semiconductor device 200. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed on an electronic device or integrated circuit (which includes semiconductor devices such as...) Figure 2 In the same layer of the semiconductor device 200 shown. Figures 3A-1 to 15C One or more of them Figure 2 The diagram shows cross-sectional views of various parts of the semiconductor device 200, corresponding to various process stages in forming the nanostructure transistors and / or nanostructure transistor layers of the semiconductor device 200.

[0120] A portion of a semiconductor device 200 can be fabricated on a semiconductor substrate 205. The semiconductor substrate 205 includes a silicon substrate, a substrate formed of a silicon-containing material, a substrate of a III-V group semiconductor compound material (such as gallium arsenide), a silicon-on-insulator substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or another semiconductor substrate. The semiconductor substrate 205 may include various layers (such as conductive or insulating layers) formed on it. The semiconductor substrate 205 may include semiconductor compounds and / or semiconductor alloys. The semiconductor substrate 205 may include various doping configurations to conform to one or more design parameters. For example, different doping profiles (such as n-type wells or p-type wells) may be formed in regions of the semiconductor substrate 205, and these regions may be designed for different device types (such as p-type metal-oxide-semiconductor nanostructure transistors and n-type metal-oxide-semiconductor nanostructure transistors). Suitable doping methods may include ion implantation and / or diffusion processes. Furthermore, the semiconductor substrate 205 may include epitaxial layers, may have stress to improve performance, and / or may have other suitable enhancement structures. Semiconductor substrate 205 may include a portion of a semiconductor wafer on which other semiconductor devices may be formed.

[0121] Mesa regions 210 may be formed in semiconductor substrate 205, extending above semiconductor substrate 205. The mesa regions 210 provide a structure that can form portions of nanostructured transistors of semiconductor device 200, such as nanostructured channels, nanostructured gate portions covering each nanostructured channel, sacrificial nanostructures, and / or other structures. In some embodiments, one or more mesa regions 210 are formed within and / or from fin structures (such as silicon fin structures), and the fin structures are formed in semiconductor substrate 205. Mesa regions 210 and semiconductor substrate 205 may include the same material and may be formed from semiconductor substrate 205. In some embodiments, mesa regions 210 are doped to form different types of nanostructured transistors, such as p-type nanostructured transistors and / or n-type nanostructured transistors. In some embodiments, mesa regions 210 include silicon or another semiconductor element material such as germanium. In some embodiments, the mesa region 210 includes semiconductor alloy materials such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or combinations thereof.

[0122] The mesa region 210 can be fabricated using suitable semiconductor process technologies, such as masking, photolithography, etching, and / or other processes. For example, the fin structure can be formed by etching a portion of the semiconductor substrate 205 to form a recess in the semiconductor substrate 205. An isolation material can then be filled into the recess, and the isolation material can be recessed or etched back to form a shallow trench isolation region 215 on the semiconductor substrate 205 between the fin structure and the mesa region. Source / drain recesses can be formed in the fin structure, resulting in the mesa region 210 being formed between the source / drain recesses. However, other fabrication techniques can also be used to form the shallow trench isolation region 215 and / or the mesa region 210.

[0123] The shallow trench isolation region 215 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, dielectric materials with low dielectric constants, and / or another suitable insulating material. The shallow trench isolation region 215 may include a multilayer structure, such as having one or more padding layers.

[0124] Semiconductor device 200 includes a plurality of nanostructured channels 220 that extend between and are electrically coupled to source / drain regions 225. The source / drain regions may refer to a single source or drain, or both, depending on the specific configuration. The nanostructured channels 220 are arranged approximately perpendicular to the semiconductor substrate 205. In other words, the nanostructured channels 220 are vertically arranged or stacked on the semiconductor substrate 205.

[0125] The nanostructure channel 220 includes silicon-based nanostructures (such as nanosheets, nanowires, or other examples) that can serve as semiconductor channels for nanostructured transistors in the semiconductor device 200. In some embodiments, the nanostructure channel 220 may include silicon-germanium or another silicon-based material. The source / drain region 225 includes silicon with one or more dopants such as p-type materials (such as boron, gallium, or other materials), n-type materials (such as phosphorus, arsenic, or other materials), and / or another type of dopant. In summary, the semiconductor device 200 may include p-type metal-oxide-semiconductor nanostructured transistors (which include p-type source / drain regions), n-type metal-oxide-semiconductor nanostructured transistors (which include n-type source / drain regions), and / or other types of nanostructured transistors.

[0126] In some embodiments, buffer 230 is located between and below the fin structure on semiconductor substrate 205 and the source / drain region 225. Buffer 230 provides isolation between the source / drain region 225 and the adjacent mesa region 210. Buffer 230 can reduce, minimize, and / or prevent electrons from passing through mesa region 210 (instead passing through nanostructured channels 220 to reduce leakage current), and / or reduce, minimize, and / or prevent dopants from entering mesa region 210 from source / drain region 225 (which can reduce short-channel effects).

[0127] Capping layer 235 may be located above and / or below source / drain region 225. Capping layer 235 may include silicon, silicon-germanium, doped silicon, doped silicon-germanium, and / or another material. Capping layer 235 may reduce dopant diffusion and protect source / drain region 225 during semiconductor process steps used in semiconductor device 200 prior to junction formation. In addition, capping layer 235 facilitates the formation of metal-semiconductor alloys (such as silicides).

[0128] At least one set of nanostructured channels 220 extends through one or more gate structures 240. The gate structure 240 may be composed of one or more metallic materials, one or more high-dielectric-constant materials, and / or one or more other types of materials. In some embodiments, a dummy gate structure (such as a polysilicon gate structure or another gate structure) is formed at the location of the gate structure 240 (before the formation of the gate structure 240), thus allowing one or more other layers and / or structures of the semiconductor device 200 to be formed prior to the formation of the gate structure 240. This reduces and / or avoids damage to the gate structure 240, which might otherwise be caused by the steps of forming one or more layers and / or structures. A gate replacement process is then performed to remove the dummy gate structure and replace it with the gate structure 240 (e.g., a gate replacement structure).

[0129] like Figure 2 As shown, portions of the gate structure 240 are formed between pairs of nanostructure channels 220 in a staggered, vertically arranged configuration. In other words, the semiconductor device 200 includes one or more vertically stacked portions of the staggered nanostructure channels 220 and the gate structure 240, as... Figure 2 As shown. In this approach, the gate structure 240 covers multiple sides of the associated nanostructure channel 220 to increase the control of the nanostructure channel 220, increase the drive current used by the nanostructure transistor of the semiconductor device 200, and reduce the short-channel effect of the nanostructure transistor of the semiconductor device 200.

[0130] Two or more nanostructured transistors in semiconductor device 200 may share some source / drain regions 225 and gate structure 240. In these embodiments, one or more source / drain regions 225 and gate structure 240 may be connected to or coupled to multiple nanostructured channels 220, such as... Figure 2 The example shown. This can be achieved by controlling multiple nanostructured channels 220 with a single gate structure 240 and a pair of source / drain regions 225.

[0131] An inner spacer 245 may be located between the source / drain region 225 and the adjacent gate structure 240. Specifically, the inner spacer 245 may be located between the source / drain region 225 and the portion of the gate structure 240 that covers multiple nanostructure channels 220. The inner spacer 245 is located at the end of the portion of the gate structure 240 that covers the multiple nanostructure channels 220. The inner spacer 245 is contained within a void, and the void is formed between the end portions of adjacent nanostructure channels 220. The inner spacer 245 can reduce parasitic capacitance and protect the source / drain region 225 from etching during the nanosheet release step of removing sacrificial nanosheets between nanostructure channels 220. The inner spacer 245 includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, and / or another dielectric material.

[0132] Semiconductor device 200 may also include an interlayer dielectric layer 250 on shallow trench isolation region 215. Interlayer dielectric layer 250 can be considered as zeroth interlayer dielectric layer. Interlayer dielectric layer 250 surrounds gate structure 240 to provide electrical isolation and / or insulation between gate structure 240, source / drain region 225 and / or other structures. Conductive structures such as contacts and / or interconnects may pass through interlayer dielectric layer 250 to source / drain region 225 and gate structure 240 to control source / drain region 225 and gate structure 240.

[0133] As mentioned above, providing Figure 2 This is used as an example. Other examples may differ. Figure 2 The example shown.

[0134] Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 The accompanying drawings illustrate, as in one example, an embodiment 300 of the fin formation process described herein. Examples of embodiment 300 include fin structures used to form nanostructured transistor layers of a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 One or more additional devices, structures, and / or layers not shown. Semiconductor device 200 may include additional layers and / or dies formed on... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 The semiconductor device 200 is located on or below a portion of the layer. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed in the same layer of the electronic device containing the semiconductor device 200.

[0135] Figure 3A-1 A perspective view of the semiconductor device 200 is shown, while Figure 3A-2 Show along Figure 3A-1 The sectional view of section AA in the image. Figure 3A-1 and Figure 3A-2 As shown, the semiconductor substrate 205 can be processed to form the semiconductor device 200. A layered stack 305 is formed on the semiconductor substrate 205. The layered stack 305 can be considered as a superlattice. In some embodiments, one or more steps related to the semiconductor substrate 205 may be performed before the layered stack 305 is formed. For example, a breakdown implantation step may be performed. A breakdown implantation step may be performed in one or more regions of the semiconductor substrate, on which nanostructured channels 220 may be formed. For example, a breakdown implantation step may be performed to reduce and / or avoid breakdown or unwanted diffusion into the semiconductor substrate 205.

[0136] The layered stack 305 includes multiple staggered layers arranged approximately perpendicular to the semiconductor substrate 205. For example, the layered stack 305 includes a first layer 310 and a second layer 315 that are vertically staggered on the semiconductor substrate 205. Figure 3A-1 and Figure 3A-2 The number of first layers 310 and second layers 315 shown is for illustrative purposes only, and other numbers of first layers 310 and second layers 315 are also within the scope of embodiments of this utility model. In some embodiments, the thicknesses of the first layers 310 and second layers 315 are different. For example, the thickness of the second layer 315 may be greater than the thickness of the first layer 310. In some embodiments, the thickness of the first layer 310 (or a group of first layers 310) may be approximately 4 nm to approximately 7 nm. In some embodiments, the thickness of the second layer 315 (or a group of second layers 315) may be approximately 8 nm to approximately 12 nm. However, other values ​​used for the thickness of the first layer 310 and the second layer 315 are also within the scope of embodiments of this utility model.

[0137] The first layer 310 includes a first material composition, while the second layer 315 includes a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. For example, the first layer 310 may include silicon-germanium, while the second layer 315 may include silicon. In some embodiments, the first and second material compositions have different oxidation rates and / or etching selectivity.

[0138] As described herein, the second layer 315 can be fabricated to form nanostructure channels 220 for subsequent fabrication of nanostructure transistors in the semiconductor device 200. The first layer 310 is a sacrificial nanostructure and will eventually be removed to define the vertical distance between adjacent nanostructure channels 220 for subsequent fabrication of the gate structure 240 in the semiconductor device 200. In summary, the first layer 310 can be considered a sacrificial layer, and the second layer 315 can be considered a channel layer.

[0139] Deposition tool 102 deposits and / or grows interlaced layers of layered stack 305 to form nanostructures (such as nanosheets) on semiconductor substrate 205. For example, deposition tool 102 may epitaxially grow interlaced layers. However, other processes may be used to form interlaced layers of layered stack 305. Methods for epitaxially growing interlaced layers of layered stack 305 may include molecular beam epitaxy, metal-organic chemical vapor deposition, and / or another suitable epitaxial growth process. In some embodiments, the epitaxially grown layers, such as the second layer 315, may comprise the same material as the semiconductor substrate 205. In some embodiments, the first layer 310 and / or the second layer 315 comprise materials different from the semiconductor substrate 205. As described above, in some embodiments, the first layer 310 comprises an epitaxially grown silicon-germanium layer, while the second layer 315 comprises an epitaxially grown silicon layer. The first layer 310 and / or the second layer 315 may be replaced with other materials such as germanium, semiconductor compound materials (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide), and / or combinations thereof. The choice of materials for the first layer 310 and / or the second layer 315 may provide different oxidation properties, different etching selectivity, and / or other different properties.

[0140] like Figure 3A-1 and Figure 3A-2As shown, the deposition tool 102 may form one or more additional layers on the layered stack 305. For example, a hard mask layer 320 may be formed on the layered stack 305, such as on the topmost second layer 315 of the layered stack 305. In another example, a capping layer 325 may be formed on the hard mask layer 320. In yet another example, another hard mask layer containing an oxide layer 330 and a nitride layer 335 may be formed on the capping layer 325. One or more hard mask layers 320, capping layers 325, and oxide layers 330 may be used to form one or more structures of the semiconductor device 200. The oxide layer 330 may serve as an adhesion layer between the layered stack 305 and the nitride layer 335, and may also serve as an etch stop layer for etching the nitride layer 335. One or more hard mask layers 320, capping layers 325, and oxide layers 330 may include silicon germanium, silicon nitride, silicon oxide, and / or another material. The capping layer 325 may include silicon and / or another material. In some embodiments, the capping layer 325 and the semiconductor substrate 205 may be made of the same material. In some embodiments, one or more additional layers may be formed by thermal growth or deposition (such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or another deposition technique).

[0141] Figure 3B-1 A perspective view of the semiconductor device 200 is shown, while Figure 3B-2 Show along Figure 3B-1 A sectional view of section AA. (e.g.) Figure 3B-1 and Figure 3B-2 As shown, the layered stack 305 and the semiconductor substrate 205 can be etched to remove portions of the layered stack 305 and the semiconductor substrate 205. The portions 340 and mesas (also considered as silicon mesas or mesas 210) of the layered stack 305 remaining after the etching step can be considered as fin structures 345 on the semiconductor substrate 205 of the semiconductor device 200. The fin structure 345 includes portions 340 of the layered stack 305 located on the mesas 210 within and / or above the semiconductor substrate 205. The fin structure 345 can be formed using any suitable semiconductor process technology. For example, the deposition tool 102, exposure tool 104, development tool 106, and / or etching tool 108 can be used with one or more photolithography processes to form the fin structure 345, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, resulting in a pattern pitch smaller than that obtained using a single direct photolithography process. For example, a sacrificial layer can be formed on a substrate and patterned using a photolithography process. A self-aligned process is then used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can later be used to pattern fin structures.

[0142] In some embodiments, a deposition tool 102 forms a photoresist layer on a hard mask layer containing an oxide layer 330 and a nitride layer 335. An exposure tool 104 exposes the photoresist layer with radiation (such as deep ultraviolet or extreme ultraviolet light), performs a post-exposure baking process (to remove residual solvent from the photoresist layer), and a developing tool 106 develops the photoresist layer to form mask units (or patterns) in the photoresist layer. In some embodiments, the method of patterning the photoresist layer to form mask units can be an electron beam lithography process. The mask units can then be used to protect portions of the semiconductor substrate 205 and the layered stack 305 during the etching step, keeping portions of the semiconductor substrate 205 and the layered stack 305 unetched to form the fin structure 345. The unprotected portions of the substrate and the unprotected portions of the layered stack 305 can be etched (e.g., by an etching tool 108) to form trenches in the semiconductor substrate 205. The etching tool may employ dry etching techniques (such as reactive ion etching), wet etching techniques, and / or combinations thereof to etch the unprotected portions of the substrate and the unprotected portions of the layered stack 305.

[0143] In some embodiments, another fin-forming technique may be used to form the fin structure 345. For example, a fin region may be defined (e.g., defined by a mask or isolation region), and a growth portion 340 may be extended outward in the form of the fin structure 345. In some embodiments, the method of forming the fin structure 345 includes a trimming process to reduce the width of the fin structure 345. The trimming process may include a wet etching process, a dry etching process, and / or other processes.

[0144] like Figure 3B-1 and Figure 3B-2 As shown, fin structures 345 can be formed for different types of nanostructure transistors used in the semiconductor device 200. Specifically, a first set of fin structures 345a can be formed for p-type nanostructure transistors (such as p-type metal-oxide-semiconductor nanostructure transistors), and a second set of fin structures 345b can be formed for n-type nanostructure transistors (such as n-type metal-oxide-semiconductor nanostructure transistors). The second set of fin structures 345b can be doped with p-type dopants (such as boron, germanium, and / or other dopants), while the first set of fin structures 345a can be doped with n-type dopants (such as phosphorus, arsenic, and / or other dopants). Subsequently, p-type source / drain regions can be additionally or alternatively formed for p-type nanostructure transistors containing the first set of fin structures 345a, and subsequently, n-type source / drain regions can be formed for n-type nanostructure transistors containing the second set of fin structures 345b.

[0145] The first set of fin structures 345a (such as a p-type metal-oxide-semiconductor fin structure) and the second set of fin structures 345b (such as an n-type metal-oxide-semiconductor fin structure) may have similar and / or different characteristics. For example, the first set of fin structures 345a may have a first height, while the second set of fin structures 345b may have a second height, wherein the first height and the second height are different. In another example, the first set of fin structures 345a may have a first width, while the second set of fin structures 345b may have a second width, wherein the first width and the second width are different. Figure 3B-1 and Figure 3B-2 In the example shown, the second width of the second set of fin structures 345b (e.g., for an n-type metal-oxide-semiconductor nanostructure transistor) is greater than the first width of the first set of fin structures 345a (e.g., for a p-type metal-oxide-semiconductor nanostructure transistor). However, other examples also fall within the scope of this embodiment.

[0146] As mentioned above, providing Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 As an example, other examples may differ from the collocation. Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 The description includes the following: Examples of implementation method 300 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 (The steps are explained).

[0147] Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 The accompanying drawing illustrates, as in one example, an embodiment 400 of the shallow trench isolation formation process described herein. An example of embodiment 400 includes forming shallow trench isolation regions 215 between fin structures 345 used in nanostructured transistor layers of a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include... Figure 4A-1 and Figure 4A-2 and / or Figure 4B-1 and Figure 4B-2 One or more additional devices, structures, and / or layers not shown. Semiconductor device 200 may include additional layers and / or dies formed on... Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and 4B-2On a layer above and / or below a portion of the semiconductor device 200 shown. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed in the same layer of the electronic device containing the semiconductor device 200. In some embodiments, it may be combined with... Figure 3A-1 , 3A-2 Following the processes described in 3B-1 and 3B-2, the steps of the example description of the combined implementation method 400 will be carried out.

[0148] Figure 4A-1 A perspective view of the semiconductor device 200 is shown, while Figure 4A-2 Show along Figure 4A-1 A sectional view of section AA. (e.g.) Figure 4A-1 and Figure 4A-2 As shown, pad 405 and dielectric layer 410 are formed on semiconductor substrate 205 and inserted into fin structures 345 (e.g., formed between fin structures 345). Deposition tool 102 can deposit pad 405 and dielectric layer 410 on semiconductor substrate 205 and in trenches between fin structures 345. Deposition tool 102 can form dielectric layer 410 such that the height of the upper surface of dielectric layer 410 is approximately the same as the height of the upper surface of nitride layer 335.

[0149] The deposition tool 102 can be modified to form a dielectric layer 410, such that the height of the dielectric layer 410 is greater than the height of the upper surface of the nitride layer 335, for example... Figure 4A-1 and Figure 4A-2 As shown. In this method, the dielectric layer 410 can be overfilled in the trenches between the fin structures 345 to ensure that the trenches are completely filled with the dielectric layer 410. A planarization or polishing step (such as a chemical mechanical polishing step) can be performed after the planarization tool 110 to planarize the dielectric layer 410. In this step, the nitride layer 335 of the hard mask layer can serve as a chemical mechanical polishing stop layer. In other words, the planarization tool 110 can planarize the dielectric layer 410 until the nitride layer 335 of the hard mask layer is exposed. In summary, the height of the upper surface of the dielectric layer 410 after this step can be approximately the same as the height of the upper surface of the nitride layer 335.

[0150] The deposition tool 102 may deposit the pad 405 using compliant deposition techniques. The deposition tool 102 may deposit the dielectric layer using chemical vapor deposition techniques (such as flowable chemical vapor deposition or another chemical vapor deposition technique), physical vapor deposition techniques, atomic layer deposition techniques, and / or another deposition technique. In some embodiments, the semiconductor device 200 may be annealed after depositing the pad 405 to improve the quality of the pad 405.

[0151] The pad 405 and the dielectric layer 410 may each comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric material, and / or another suitable insulating material. In some embodiments, the dielectric layer 410 may comprise a multilayer structure, such as having one or more pad layers.

[0152] Figure 4B-1 A perspective view of the semiconductor device 200 is shown, while Figure 4B-2 Show along Figure 4B-1 A sectional view of section AA. (e.g.) Figure 4B-1 and Figure 4B-2 As shown, a back etch step can be performed to remove portions of the pad 405 and the dielectric layer 410 to form a shallow trench isolation region 215. An etching tool 108 can etch the pad 405 and the dielectric layer 410 in the back etch step to form the shallow trench isolation region 215. The etching tool 108 can etch the pad 405 and the dielectric layer 410 against a hard mask layer (such as a hard mask layer containing an oxide layer 330 and a nitride layer 335). The etching tool 108 etches the pad 405 and the dielectric layer 410 such that the height of the shallow trench isolation region 215 is less than or approximately equal to the bottom height of the portion 340 of the layered stack 305. In summary, the portion 340 of the layered stack 305 extends above the shallow trench isolation region 215. In some embodiments, the pad 405 and the dielectric layer 410 are etched such that the height of the shallow trench isolation region 215 is less than the height of the upper surface of the mesa region 210.

[0153] In some embodiments, the etching tool 108 employs a dry etching technique to etch the pad 405 and the dielectric layer 410. Ammonia, hydrofluoric acid, and / or another etchant may be used. Plasma-based dry etching techniques can cause a reaction between the etchant and the materials of the pad 405 and the dielectric layer 410, including:

[0154] SiO2 + 4HF → SiF4 + 2H2O

[0155] The silicon oxide of the gasket 405 and dielectric layer 410 reacts with hydrofluoric acid to form a byproduct containing silicon tetrafluoride and water. Hydrofluoric acid and ammonia further decompose the silicon tetrafluoride to form ammonium fluorosilicate byproduct.

[0156] SiF4 + 2HF + 2NH3 → (NH4)2SiF6

[0157] Ammonium fluorosilicate byproducts can be removed from the process chamber of the self-etching tool 108. After the removal of ammonium fluorosilicate, it can be sublimated into silicon tetrafluoride, ammonia, and hydrofluoric acid at a post-processing temperature of approximately 100°C to approximately 250°C.

[0158] In some embodiments, the etching tool 108 etches the pad 405 and the dielectric layer 410 such that the height of the shallow trench isolation region 215 between the first set of fins 345a (e.g., for p-type metal-oxide-semiconductor nanostructure transistors) is greater than the height of the shallow trench isolation region 215 between the second set of fins 345b (e.g., for n-type metal-oxide-semiconductor nanostructure transistors). The main reason is that the width of the second set of fins 345b is greater than the width of the first set of fins 345a. Furthermore, this causes the upper surface of the shallow trench isolation region 215 between the first set of fins 345a and the second set of fins 345b to be inclined (e.g., inclined downwards from the first set of fins 345a to the second set of fins 345b, as shown). Figure 4B-1 and 4B-2 (Example shown). The van der Waals force between the etchant and the surfaces of the pad 405 and dielectric layer 410 can first physically adsorb the etchant used to etch the pad 405 and dielectric layer 410, for example, the etchant physically bonds to the pad 405 and dielectric layer 410. The dipole moment force can capture the etchant. The etchant then adheres to the dangling bonds of the pad 405 and dielectric layer 410 and begins chemisorption. The chemisorption of the etchant on the surfaces of the pad 405 and dielectric layer 410 causes the etching of the pad 405 and dielectric layer 410. The larger trench width between the second set of fin structures 345b allows for a larger surface area for chemisorption, resulting in a higher etching rate between the second set of fin structures 345b. The higher etching rate results in a shallow trench isolation region 215 between the second set of fin structures 345b having a smaller height than the shallow trench isolation region 215 between the first set of fin structures 345a.

[0159] As mentioned above, providing Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 As an example, other examples may differ from the collocation. Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 The description includes the following: Examples of implementation method 400 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 (The steps are explained).

[0160] Figure 5 The accompanying drawing illustrates, as in one example, an embodiment 500 of the dummy gate formation process described herein. An example of embodiment 500 includes forming a nanostructured transistor layer for use in a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include... Figure 5One or more additional devices, structures, and / or layers not shown. Semiconductor device 200 may include additional layers and / or dies formed on... Figure 5 The semiconductor device 200 is located on a layer above and / or below a portion of the semiconductor device 200. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed in the same layer of the electronic device containing the semiconductor device 200. In some embodiments, it may be combined with... Figures 3A-1 to 4B-2 Following the explained process, the relevant steps of the example of implementation method 500 will be performed.

[0161] Figure 5 A perspective view of the semiconductor device 200 is shown. (See figure) Figure 5 As shown, a dummy gate structure 505 (which can also be viewed as a dummy gate stack or a temporary gate structure) is formed on the fin structure 345. The dummy gate structure 505 is a sacrificial structure, which will be replaced by a replacement gate structure or a replacement gate stack (such as gate structure 240) in subsequent process stages used in the semiconductor device 200. The portion of the fin structure 345 below the dummy gate structure 505 can be viewed as a channel region. The dummy gate structure 505 can also define the source / drain regions of the fin structure 345, such as the regions of the fin structure 345 on both sides of the channel region and adjacent to both sides of the channel region.

[0162] The dummy gate structure 505 may include a gate layer 510, a hard mask layer 515 on the gate layer 510, and spacer layers 520 on both sides of the gate layer 510 and the hard mask layer 515. The dummy gate structure 505 may be formed on the gate dielectric layer 525 between the topmost second layer 315 and the dummy gate structure 505. The gate layer 510 includes polysilicon or another material. The hard mask layer 515 includes one or more layers such as oxide layers (e.g., a pad oxide layer containing silicon dioxide or another material) and nitride layers formed on the oxide layers (e.g., a pad nitride layer containing silicon nitride such as trisilicon tetranitride or another material). The spacer layer 520 includes silicon oxide, nitrogen-free silicon oxide, or another suitable material. The gate dielectric layer 525 may include silicon oxide (e.g., silicon dioxide), silicon nitride (e.g., trisilicon tetranitride), a high dielectric constant dielectric material, and / or another suitable material.

[0163] The method for forming the layered structure 505 can employ various semiconductor process technologies such as deposition (e.g., by deposition tool 102), patterning (e.g., by exposure tool 104 and developing tool 106), etching (e.g., by etching tool 108), and / or other techniques. Examples may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, electron beam evaporation, photolithography, electron beam lithography, photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), dry etching (e.g., reactive ion etching), wet etching, and / or other techniques.

[0164] In some embodiments, a gate dielectric layer 525 is compliantly deposited on the semiconductor device 200, and then the gate dielectric layer 525 is selectively removed from portions of the semiconductor device 200 (such as source / drain regions). A gate layer 510 is then deposited on the retained portions of the gate dielectric layer 525. A hard mask layer 515 is then deposited on the gate layer 510. A spacer layer 520 can be compliantly deposited in a manner similar to that of the gate dielectric layer 525, and the spacer layer 520 can be etched back to retain the spacer layer 520 on the sidewalls of the dummy gate structure 505. In some embodiments, the spacer layer 520 includes multiple spacer layers. For example, the spacer layer 520 may include a sealing spacer layer formed on the sidewalls of the dummy gate structure 505, and a substrate spacer layer formed on the sealing spacer layer. The sealing spacer layer and the substrate spacer layer may be composed of similar or different materials. In some embodiments, the substrate spacer layer is formed without the plasma surface treatment used for the sealing spacer layer. In some embodiments, the thickness of the substrate spacer layer is greater than the thickness of the sealing spacer layer. In some embodiments, the gate dielectric layer 525 can be omitted from the dummy gate structure formation process and instead formed in the gate replacement process.

[0165] Figure 5 The reference cross-sections used in the following figures are shown. Cross-section AA (which can be considered a y-section) in the xz plane crosses the fin structure 345 in the source / drain region of the semiconductor device 200. Cross-section BB (which can be considered an x-section) in the yz plane is perpendicular to cross-section AA and crosses the dummy gate structure 505 in the source / drain region of the semiconductor device 200. Cross-section CC in the xz plane is parallel to cross-section AA and perpendicular to cross-section BB, and runs along the dummy gate structure 505. The following figures will be based on these reference cross-sections for clarity. In some figures, identical reference numerals for shown components or structures may be omitted to avoid obscuring other components or structures and to facilitate clarity.

[0166] As mentioned above, providing Figure 5 As an example, other examples may differ from the collocation. Figure 5The description includes the following: Examples of implementation method 500 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 5 (The steps are explained).

[0167] Figure 6-1 , Figure 6-2 and Figure 6-3 As an example, the accompanying drawings show an embodiment 600 of the semiconductor device 200 described herein. Figure 6-1 , Figure 6-2 and Figure 6-3 The sectional views are respectively along Figure 5 The cross-sections AA, BB, and CC. For example... Figure 6-2 and 6-3 As shown in cross-sections BB and CC, the dummy gate structure 505 is formed on the fin structure 345. (As shown in the cross-sections BB and CC) Figure 6-3 As shown in the cross section CC, the portion forming the gate dielectric layer 525 and the portion forming the gate layer 510 are in a recess on the fin structure 345, and the recess is formed by removing the hard mask layer 320.

[0168] As mentioned above, providing Figure 6-1 , Figure 6-2 and Figure 6-3 As an example, other examples may differ from the collocation. Figure 6-1 , Figure 6-2 and Figure 6-3 The description includes the following: Examples of implementation method 600 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 6-1 , Figure 6-2 and Figure 6-3 (The steps are explained).

[0169] Figure 7A-1 , Figure 7A-2 , Figure 7A-3 , Figure 7B-1 , Figure 7B-2 , Figure 7B-3 , Figure 7C-1 , Figure 7C-2 , Figure 7C-3 , Figure 7D-1 , Figure 7D-2 and Figure 7D-3 The accompanying drawings illustrate, as in one example, an embodiment 700 of the source / drain recess formation process and the inner spacer formation process described herein. An example of embodiment 700 includes forming source / drain recesses and inner spacers 245 for use in a nanostructured transistor layer of a semiconductor device 200. Figures 7A-1 to 7D-3 like Figure 5 As shown in the perspective view, they respectively include Figure 5 The sectional view of section AA in the middle. Figure 5 The sectional view of section BB in the middle, and Figure 5A cross-sectional view of section CC. In some embodiments, it can be combined with... Figures 3A-1 to 6-3 Following the explained process, the relevant steps of the example of implementation method 700 will be performed.

[0170] like Figure 7A-2 As shown in section BB, a source / drain recess 705 is formed in portion 340 of the fin structure 345 during the etching step. The source / drain recess 705 is formed to provide space on both sides of the dummy gate structure 505 after the source / drain region 225 is formed. The etching tool 108 can perform the etching step, which can be considered as a strained source / drain etching step. In some embodiments, the etching step includes plasma etching, wet chemical etching, and / or another etching technique.

[0171] In some embodiments, the source / drain recess 705 also extends into a portion of the mesa region 210 of the fin structure 345. In these embodiments, the source / drain recess 705 may be patterned into well portions (such as p-type and n-type wells) of the fin structure 345. In embodiments where the semiconductor substrate 205 comprises a (100) oriented silicon material, a (111) crystal plane may be formed at the bottom of the source / drain recess 705, resulting in a V-shaped or triangular bottom profile of the source / drain recess 705. In some embodiments, wet etching using tetramethylammonium hydroxide and / or chemical dry etching using hydrogen chloride may be used to form the V-shaped profile. However, the bottom profile of the source / drain recess 705 may include other shapes, such as circular, semi-circular, or other shapes.

[0172] like Figure 7A-2 and Figure 7A-3 As shown in cross-sections BB and CC, after the etching step that forms the source / drain recesses 705, portions of the first layer 310 and the second layer 315 of the layered stack 305 can be retained beneath the dummy gate structure 505. The portion of the second layer 315 beneath the dummy gate structure 505 can form the nanostructure channel 220 of the nanostructure transistor in the semiconductor device 200. The nanostructure channel 220 extends between adjacent source / drain recesses 705.

[0173] like Figure 7B-2As shown in section BB, the first layer 310 can be etched laterally during the etching step (e.g., in a direction approximately parallel to the length of the first layer 310) to form voids 710 between portions of the nanostructure channel 220. Specifically, the etching tool 108 can laterally etch the ends of the first layer 310 beneath the dummy gate structure 505 via the source / drain recess 705 to form voids 710 between the ends of the nanostructure channel 220. In embodiments where the first layer 310 is silicon-germanium and the second layer 315 is silicon, the etching tool 108 can selectively etch the first layer 310 using a wet etchant such as a mixed solution containing hydrogen peroxide, acetic acid, and / or hydrofluoric acid, followed by cleaning with water. The mixed solution and water can be provided to the source / drain recess 705 to etch the first layer 310 from the source / drain recess 705. In some embodiments, the steps of etching with the mixed solution and cleaning with water can be repeated approximately 10 to approximately 20 times. In some embodiments, the etching time of the mixed solution can be from about 1 minute to about 2 minutes. The operating temperature of the mixed solution can be from approximately 60°C to approximately 90°C. However, other values ​​used for the parameters of the etching step are also within the scope of this embodiment.

[0174] The cavity 710 can be formed in an approximately arcuate, approximately concave, approximately triangular, approximately square, or other shape. In some embodiments, the depth of one or more cavities 710 (e.g., the dimension of the cavity extending from the source / drain recess 705 into the first layer 310) can be approximately 0.5 nm to approximately 5 nm. In some embodiments, the depth of one or more cavities 710 can be approximately 1 nm to approximately 3 nm. However, other values ​​used for the depth of the cavity 710 are also within the scope of this embodiment. In some embodiments, the length of the cavity 710 formed by the etching tool 108 (e.g., the dimension of the cavity extending from the nanostructure channel 220 under the first layer 310 to another nanostructure channel 220 on the first layer 310) can allow the cavity 710 to partially extend into the side of the nanostructure channel 220 (e.g., the width or length of the cavity 710 is greater than the thickness of the first layer 310). In this manner, the inner spacers subsequently formed in the cavity 710 can extend into the end portion of the nanostructure channel 220.

[0175] like Figure 7C-1 and Figure 7C-2As shown in cross-sections AA and BB, an insulating layer 715 can be compliantly deposited along the sidewalls and bottom of the source / drain recess 705. The insulating layer 715 may further extend along the spacer layer 520. The deposition tool 102 may employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or another deposition technique to deposit the insulating layer 715. The insulating layer 715 comprises silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, and / or another dielectric material. The material comprising the insulating layer 715 may differ from the material of the spacer layer 520.

[0176] The insulating layer 715 formed by the deposition tool 102 is thick enough to fill the voids 710 between the nanostructure channels 220. For example, the thickness of the insulating layer 715 can be approximately 1 nm to approximately 10 nm. In another example, the thickness of the insulating layer 715 can be approximately 2 nm to approximately 5 nm. However, other values ​​used for the thickness of the insulating layer 715 are also within the scope of this embodiment.

[0177] like Figure 7D-1 and Figure 7D-2 The cross-sections AA and BB shown can partially remove the insulating layer 715, so that the remaining portion of the insulating layer 715 corresponds to the inner spacer 245 in the cavity 710. The etching tool 108 can perform an etching step to partially remove the insulating layer 715.

[0178] In some embodiments, the etching step may cause the surface of the inner spacer 245 facing the source / drain recess 705 to be arc-shaped or recessed. The recess depth in the inner spacer 245 may be approximately 0.2 nm to approximately 3 nm. In another example, the recess depth in the inner spacer 245 may be approximately 0.5 nm to approximately 2 nm. In yet another example, the recess depth in the inner spacer 245 may be less than approximately 0.5 nm. In some embodiments, the surface of the inner spacer 245 facing the source / drain recess 705 is approximately flat, such that the surface of the inner spacer 245 is approximately flush with the end surface of the nanostructure channel 220.

[0179] As mentioned above, providing Figures 7A-1 to 7D-3 As an example, other examples may differ from the collocation. Figures 7A-1 to 7D-3 The description includes the following: Examples of implementation method 700 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figures 7A-1 to 7D-3 (The steps are explained).

[0180] Figure 8-1 , Figure 8-2 and Figure 8-3The accompanying drawings illustrate, as in one example, an embodiment 800 of the source / drain region formation process described herein. An example of embodiment 800 includes forming source / drain regions 225 in a nanostructured transistor layer of a source / drain recess 705 for use in a semiconductor device 200. Specifically, an example of embodiment 800 includes forming p-type source / drain regions 225a for a p-type metal-oxide-semiconductor nanostructured transistor (e.g., a p-type metal-oxide-semiconductor field-effect transistor) of the semiconductor device 200, and forming n-type source / drain regions 225b for an n-type metal-oxide-semiconductor nanostructured transistor (e.g., an n-type metal-oxide-semiconductor field-effect transistor) of the semiconductor device 200.

[0181] Figure 8-1 , Figure 8-2 and Figure 8-3 like Figure 5 As shown in the perspective view, they respectively include Figure 5 The sectional view of section AA in the middle. Figure 5 The sectional view of section BB in the middle, and Figure 5 A cross-sectional view of section CC. In some embodiments, it can be combined with... Figures 3A-1 to 7D-3 Following the explanation of the process, the relevant steps of the example of implementation method 800 will be described.

[0182] like Figure 8-1 and Figure 8-2 As shown in cross-sections AA and BB, one or more layers are filled into the source / drain recess 705 to form source / drain regions 225 within the source / drain recess 705. For example, deposition tool 102 may deposit buffer zone 230 at the bottom of the source / drain recess 705, deposition tool 102 may deposit source / drain regions 225 on buffer zone 230, and deposition tool 102 may deposit contact etch stop layer 805 on source / drain regions 225. In some embodiments, capping layer 235 (not shown) may be deposited on source / drain regions 225 prior to forming contact etch stop layer 805.

[0183] Buffer 230 may include silicon, boron-doped silicon, or another doped silicon and / or another material. Buffer 230 can reduce, minimize, and / or prevent the migration of dopants and / or leakage current from the source / drain region 225 to the adjacent mesa region 210, which could otherwise cause short-channel effects in the semiconductor device 200. In summary, buffer 230 can increase the performance and / or yield of the semiconductor device 200. In some embodiments, buffer 230 may be omitted from one or more source / drain regions 225.

[0184] The source / drain region 225 may include one or more layers of epitaxially grown material. For example, the deposition tool 102 may epitaxially grow a first layer (referred to as L1) of the source / drain region 225 on the buffer 230, and may epitaxially grow a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 225 on the first layer. The p-type source / drain region 225a may include semiconductor materials such as silicon or silicon-germanium doped with p-type dopants such as boron, such as boron-doped silicon, boron-doped silicon-germanium, and / or other examples. The p-type source / drain region 225a may additionally and / or alternatively include silicon-germanium. The n-type source / drain region 225b may include undoped silicon and / or silicon doped with n-type dopants such as phosphorus, arsenic, and / or other dopants, such as phosphorus-doped silicon, arsenic-doped silicon, and / or other examples.

[0185] In some embodiments, prior to forming the interlayer dielectric layer 250, a contact etch stop layer 805 is conformally deposited (e.g., using deposition tool 102) on the source / drain regions 225 (including p-type source / drain regions 225a and n-type source / drain regions 225b). The interlayer dielectric layer 250 is then formed on the contact etch stop layer 805. The contact etch stop layer 805 provides a mechanism to stop the etching process when forming the contacts or vias used in the source / drain regions 225. The contact etch stop layer 805 may be composed of a dielectric material with an etch selectivity different from that of adjacent layers or components. The contact etch stop layer 805 may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the contact etch stop layer 805 may include or may be silicon nitride, silicon carbonitride, carbon nitride, silicon oxynitride, silicon oxycarbide, combinations thereof, or other materials. The deposition method for the contact etch stop layer 805 can employ deposition techniques such as atomic layer deposition, chemical vapor deposition, or another deposition technique.

[0186] As mentioned above, providing Figure 8-1 , Figure 8-2 and Figure 8-3 As an example, other examples may differ from the collocation. Figure 8-1 , Figure 8-2 and Figure 8-3 The description includes the following: Examples of implementation method 800 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 8-1 , Figure 8-2 and Figure 8-3 (The steps are explained).

[0187] Figure 9-1 , Figure 9-2 and Figure 9-3 The accompanying drawings illustrate, as in one example, an embodiment 900 of the interlayer dielectric layer formation process described herein. An example of embodiment 900 includes an interlayer dielectric layer used to form a nanostructured transistor layer of a semiconductor device 200. Figure 9-1, Figure 9-2 and Figure 9-3 like Figure 5 As shown in the perspective view, they respectively include Figure 5 The sectional view of section AA in the middle. Figure 5 The sectional view of section BB in the middle, and Figure 5 A cross-sectional view of section CC. In some embodiments, it can be combined with... Figures 3A-1 to 8-3 Following the explanation of the process, the relevant steps of the example of implementation method 900 will be described.

[0188] like Figure 9-1 and Figure 9-2 As shown in cross-sections AA and BB, an interlayer dielectric layer 250 is formed on the source / drain regions 225 (including p-type source / drain regions 225a and n-type source / drain regions 225b). Specifically, the interlayer dielectric layer 250 may be formed on the contact etch stop layer 805 above the source / drain regions 225 (including p-type source / drain regions 225a and n-type source / drain regions 225b). The interlayer dielectric layer 250 fills the region between the dummy gate structures 505 (above the source / drain regions 225). The interlayer dielectric layer 250 can reduce and / or avoid damage to the source / drain regions 225 during the gate replacement process. The interlayer dielectric layer 250 can be considered as a zeroth interlayer dielectric layer or another interlayer dielectric layer.

[0189] Deposition tool 102 can be used with physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and combinations thereof. Figure 1 Another deposition technique and / or another suitable deposition technique are described to deposit the interlayer dielectric layer 250. The interlayer dielectric layer 250 may be deposited in one or more deposition steps. In some embodiments, the interlayer dielectric layer 250 may be planarized using a planarization tool 110 after deposition.

[0190] As mentioned above, providing Figure 9-1 , Figure 9-2 and Figure 9-3 The number and arrangement of the devices and steps shown are examples. In practice, additional steps and devices, fewer steps and devices, different steps and devices, and / or steps and devices in different sequences may be included (compared to a combination). Figure 9-1 , Figure 9-2 and Figure 9-3 (Description of steps and apparatus).

[0191] Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , 10C-2 and Figure 10C-3 The accompanying drawing illustrates an embodiment 1000 of a gate replacement process. An example of embodiment 1000 involves replacing a dummy gate structure 505 in a nanostructure transistor layer of a semiconductor device 200 with a gate structure 240 (e.g., a gate replacement structure).

[0192] Figures 10A-1 to 10C-3 like Figure 5 As shown in the perspective view, they respectively include Figure 5 The sectional view of section AA in the middle. Figure 5 The sectional view of section BB in the middle, and Figure 5 A cross-sectional view of section CC. In some embodiments, it can be combined with... Figures 3A-1 to 9-3 Following the steps described, the relevant steps will be explained using an example of implementation method 1000.

[0193] like Figure 10A-2 and Figure 10A-3 As shown in cross-sections BB and CC, a gate replacement step (e.g., by one or more semiconductor process tools such as deposition tool 102 to plating tool 112) is performed to remove the dummy gate structure 505 from the semiconductor device 200. Removing the dummy gate structure 505 will leave an opening 1005 (or a recess) between the interlayer dielectric layers 250 on the source / drain regions 225. The dummy gate structure 505 may be removed by one or more etching steps. This etching step may include plasma etching, wet chemical etching, and / or another etching technique.

[0194] like Figure 10B-2 and Figure 10B-3 As shown in cross-sections BB and CC, a nanostructure release step (such as a silicon-germanium release step) is performed to remove the first layer 310 (such as a silicon-germanium layer). This will form openings 1005 between the nanostructure channels 220 (such as the region surrounding the nanostructure channels 220). The nanostructure release step may include an etching step performed with an etching tool 108, which removes the first layer 310 based on the difference in etch selectivity between the material of the first layer 310 and the material of the nanostructure channels 220 (and the difference in etch selectivity between the material of the first layer 310 and the material of the inner spacer 245). The inner spacer 245 may serve as an etch stop layer in the etching step to protect the source / drain regions 225 from etching.

[0195] like Figure 10C-2 and Figure 10C-3As shown in cross-sections BB and CC, a continuous gate displacement step is performed, wherein deposition tool 102 and / or plating tool 112 can form a gate structure 240 (such as a displacement gate structure) in the opening 1005 between the source / drain regions 225. Specifically, the gate structure 240 fills the area between and around the nanostructure channel 220 (previously occupied by the first layer 310), thus the gate structure 240 covers the nanostructure channel 220 and surrounds at least three sides of the nanostructure channel 220. In some embodiments, the gate structure 240 completely covers the nanostructure channel 220 and surrounds all four sides of the nanostructure channel 220. The gate structure 240 may include a metal gate structure. Prior to forming the gate structure 240, a gate dielectric layer 1010 may be deposited on the nanostructure channel 220 and its sidewalls. The gate dielectric layer 1010 may be a high-dielectric-constant gate dielectric layer between the gate structure 240 and the nanostructure channel 220. The gate structure 240 may include additional layers such as an interface layer, a work function adjustment layer, a metal electrode structure, and / or other layers.

[0196] Atomic layer deposition (ALD) and / or another suitable deposition technique may be used to compliantly deposit the gate dielectric layer 1010 (e.g., using deposition tool 102). The gate dielectric layer 1010 may comprise one or more materials with high dielectric constants, such as materials with a dielectric constant greater than that of silicon oxide (e.g., approximately 3.9). Examples include lanthanum oxide, hafnium oxide, aluminum oxide, and / or other materials. The gate structure 240 comprises one or more metallic materials, such as ruthenium, tungsten, cobalt, copper, molybdenum, and / or other metallic materials. In some embodiments, an adhesive layer (not shown) is included between the gate dielectric layer 1010 and the gate structure 240 to promote adhesion between the gate dielectric layer 1010 and the gate structure 240. Examples of materials used for the adhesive layer may include tantalum nitride, titanium nitride, and / or another suitable adhesive layer material.

[0197] As mentioned above, providing Figures 10A-1 to 10C-3 The number and configuration of the described structures and steps are given as examples. In practice, it may include additional steps and devices, fewer steps and devices, different steps and devices, and / or steps and devices in different sequences (compared to a combination). Figures 10A-1 to 10C-3 (Description of steps and apparatus).

[0198] Figures 11A to 11I As an example, the accompanying drawings show embodiment 1100 in which the stacked nanostructure transistor layers described herein are formed in semiconductor device 200.

[0199] Figures 11A to 11I One or more such as Figure 5 As shown in the perspective view, including Figure 5 The sectional view of section BB (e.g., in the y-direction).

[0200] like Figure 11A As shown, they can be combined. Figures 3A-1 to 10C-3 The described process is used to form a first nanostructure transistor layer 1105a of a semiconductor device 200. The first nanostructure transistor layer 1105a (such as a first complementary metal-oxide-semiconductor layer) includes a plurality of first nanostructure channels 220 disposed in the z-direction and extending in the x-direction and / or y-direction. The first nanostructure transistor layer 1105a includes a first gate structure 240 to cover the plurality of first nanostructure channels 220. A gate dielectric layer 1010 may be included between the first gate structure 240 and the plurality of first nanostructure channels 220. A spacer layer 520 may be included on the sidewalls of the first gate structure 240 on the plurality of first nanostructure channels 220.

[0201] The first nanostructure transistor layer 1105a includes a plurality of first source / drain regions 225 on both sides of the plurality of nanostructure channels 220. The plurality of first source / drain regions 225 may include a plurality of p-type source / drain regions 225a (e.g., for one or more p-type metal-oxide-semiconductor nanostructure transistors) and a plurality of n-type source / drain regions 225b (e.g., for one or more n-type metal-oxide-semiconductor nanostructure transistors). A buffer zone 230 may be included below the plurality of first source / drain regions 225. An inner spacer 245 may be included between the first gate structure 240 and the plurality of first source / drain regions 225. A contact etch stop layer 805 and a first interlayer dielectric layer 250 may be included above the plurality of first source / drain regions 225.

[0202] like Figure 11B As shown, a bonding dielectric layer 1110 can be formed on the first nanostructure transistor layer 1105a. The deposition tool 102 can employ physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and other methods. Figure 1 Another deposition technique and / or another suitable deposition technique are described to deposit the bonding dielectric layer 1110. The bonding dielectric layer 1110 may be deposited in one or more deposition steps. In some embodiments, after depositing the bonding dielectric layer 1110, a planarization tool 110 may be used to planarize the bonding dielectric layer 1110. The bonding dielectric layer 1110 may include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, and / or another suitable dielectric material.

[0203] like Figure 11CAs shown, a layered stack 305 (such as a second nanostructured layered stack) is bonded to a semiconductor device 200. Specifically, a bonding dielectric layer 1110 can be used to bond the layered stack 305 to the top of the first nanostructured transistor layer 1105a. A first layer 310 and a second layer 315 of the layered stack 305 can be formed or grown on a substrate, and the first layer 310 and the second layer 315 can be removed from the substrate and then transferred to the semiconductor device 200 for bonding. A bonding tool 114 can be used to bond the layered stack 305 to the first nanostructured transistor layer 1105a using the bonding dielectric layer 1110.

[0204] like Figure 11D As shown, a second nanostructure transistor layer 1105b is formed on the first nanostructure transistor layer 1105a from the layered stack 305. In this manner, the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b are stacked or vertically arranged (in the z-direction) in the semiconductor device 200.

[0205] Can be combined Figures 3A-1 to 10C-3 The steps described are for forming a second nanostructure transistor layer 1105b. The second nanostructure transistor layer 1105b (such as a second complementary metal-oxide-semiconductor layer) includes a plurality of second nanostructure channels 220 disposed in the z-direction and extending in the x-direction and / or y-direction. The second nanostructure transistor layer 1105b includes a second gate structure 240 covering the plurality of second nanostructure channels 220. A gate dielectric layer 1010 may be included between the second gate structure 240 and the plurality of second nanostructure channels 220. A spacer layer 520 may be included on the sidewalls of the second gate structure 240 on the plurality of second nanostructure channels 220.

[0206] The second nanostructure transistor layer 1105b includes a plurality of second source / drain regions 225 located on both sides of a plurality of second nanostructure channels 220. The plurality of second source / drain regions 225 may include a plurality of p-type source / drain regions 225a (for one or more p-type metal-oxide-semiconductor nanostructure transistors) and a plurality of n-type source / drain regions 225b (for one or more n-type metal-oxide-semiconductor nanostructure transistors). A buffer zone 230 may be included beneath the plurality of second source / drain regions 225. An inner spacer 245 may be included between the second gate structure 240 and the plurality of second source / drain regions 225. A contact etch stop layer 805 and a second interlayer dielectric layer 250 may be included on the plurality of second source / drain regions 225.

[0207] like Figure 11DAs shown, the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b may include different numbers of nanostructure channels 220. This allows the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b to have different performance characteristics, such as different power consumption, different switching speeds, and / or different other characteristics. For example, the number of multiple first nanostructure channels 220 in the first nanostructure transistor layer 1105a (e.g., three stacked nanostructure channels 220) may be greater than the number of multiple second nanostructure channels 220 in the second nanostructure transistor layer 1105b (e.g., two stacked nanostructure channels 220). This allows the energy consumption of the nanostructure transistors in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructure transistor layer 1105b to be less than that of the nanostructure transistors in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructure transistor layer 1105a; and allows the switching speed of the nanostructure transistors in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructure transistor layer 1105a to be faster than that of the nanostructure transistors in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructure transistor layer 1105b.

[0208] The number of the plurality of second nanostructure channels 220 in the second nanostructure transistor layer 1105b can be changed to be greater than the number of the plurality of first nanostructure channels 220 in the first nanostructure transistor layer 1105a. Furthermore, in some embodiments, the second nanostructure transistor layer 1105b may include a single nanostructure channel 220, whose power consumption is less than that of the nanostructure transistors in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructure transistor layer 1105a; and the first nanostructure transistor layer 1105a may include a plurality of nanostructure channels 220, so that the switching speed of the nanostructure transistors in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructure transistor layer 1105a is faster than the switching speed of the nanostructure transistors in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructure transistor layer 1105b. The first nanostructure transistor layer 1105a can be modified to include a single nanostructure channel 220, which consumes less power than the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructure transistor layer 1105b; and the second nanostructure transistor layer 1105b can include multiple nanostructure channels 220, so that the switching speed of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructure transistor layer 1105b is faster than the switching speed of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructure transistor layer 1105a.

[0209] One or more other characteristics of the first nanostructure transistor layer 1105a and / or one or more other characteristics of the second nanostructure transistor layer 1105b may be additionally or alternatively fabricated to emphasize one or more performance parameters of the first nanostructure transistor layer 1105a and / or the second nanostructure transistor layer 1105b. For example, the length of the plurality of first nanostructure channels 220 of the first nanostructure transistor layer 1105a (between the plurality of first source / drain regions 225 in the y-direction) may be greater than the length of the plurality of second nanostructure channels 220 of the second nanostructure transistor layer 1105b (between the plurality of second source / drain regions 225 in the y-direction). This allows the driving voltage of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructure transistor layer 1105b to be greater than the driving voltage of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructure transistor layer 1105a; it also allows the leakage current of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructure transistor layer 1105a to be less than the leakage current of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructure transistor layer 1105b.

[0210] like Figures 11E to 11I As shown, the second interconnect structure 1115b can be formed on the second nanostructure transistor layer 1105b. The second interconnect structure 1115b includes multiple dielectric layers and multiple metallization layers, which can provide signals and / or power to the nanostructure transistors in the first nanostructure transistor layer 1105a, and / or provide signals and / or power from the nanostructure transistors.

[0211] like Figure 11E As shown, the etch stop layer 1120 and dielectric layer 1125 of the second interconnect structure 1115b can be formed on the second nanostructure transistor layer 1105b. The deposition tool 102 can employ physical vapor deposition, atomic layer deposition, chemical vapor deposition, epitaxy, oxidation, or a combination of these techniques. Figure 1 Another deposition technique and / or another suitable deposition technique are described to deposit the etch stop layer 1120 and / or the dielectric layer 1125. The etch stop layer 1120 and / or the dielectric layer 1125 may be deposited in one or more deposition steps. In some embodiments, after depositing the etch stop layer 1120 and / or the dielectric layer 1125, a planarization tool 110 may be used to planarize the etch stop layer 1120 and / or the dielectric layer 1125. The etch stop layer 1120 and the dielectric layer 1125 may each include one or more dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, and / or another dielectric material.

[0212] like Figure 11FAs shown, a recess 1130 may be formed through the dielectric layer 1125, through the etch stop layer 1120, and through the buffer zone 230 into a portion of a plurality of second source / drain regions 225. The upper surfaces of the plurality of second source / drain regions 225 are exposed in the recess 1130.

[0213] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 1125, through the etch stop layer 1120, and through the buffer 230 to form a recess 1130. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer 1125. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch through the dielectric layer 1125, through the etch stop layer 1120, and through the buffer 230 according to the pattern to form the recess 1130. In some embodiments, over-etching occurs in portions of the upper surfaces of the plurality of second source / drain regions 225 (to ensure that the etched recess 1130 completely penetrates the plurality of second source / drain regions 225). In some embodiments, the etching step includes a plasma etching step, a wet chemical etching step, and / or another etching step. In some embodiments, photoresist removal tools may be used to remove residual portions of the photoresist layer (e.g., chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the recess 1130 according to the pattern.

[0214] like Figure 11G As shown, a silicide layer 1135 is formed on a plurality of second source / drain regions 225 in a recess 1130. The silicide layer 1135 may be included in the semiconductor device 200 to reduce the contact resistance between the plurality of second source / drain regions 225 and the source / drain contacts subsequently formed in the recess 1130. A deposition tool 102 may be used to deposit a metal layer (or metal precursor) on the upper surface of the plurality of second source / drain regions 225 in the recess 1130. High-temperature annealing may then be performed to generate a reaction between the metal layer and the upper surface of the plurality of second source / drain regions 225, thereby forming the silicide layer 1135. The silicide layer 1135 may include metal silicides such as titanium silicides and / or another type of metal silicide.

[0215] like Figure 11H As shown, a pad 1140 and source / drain contacts 1145 can be formed on a plurality of second source / drain regions 225 in the recess 1130. Specifically, the pad 1140 and source / drain contacts 1145 can be formed on a silicide layer 1135 above the plurality of second source / drain regions 225. The deposition tool 102 can employ physical vapor deposition, atomic layer deposition, chemical vapor deposition, epitaxy, oxidation, or a combination of techniques. Figure 1 Another deposition technique and / or another suitable deposition technique is described to deposit the substrate 1140. The deposition tool 102 and / or plating tool 112 may employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or a combination thereof. Figure 1 Another deposition technique and / or another suitable deposition technique described above are used to deposit source / drain contacts 1145.

[0216] The pad 1140 may include an adhesive pad (for promoting adhesion between the source / drain contact 1145 and the surrounding dielectric layer), a barrier layer (for minimizing or preventing material migration from the source / drain contact 1145 into the surrounding dielectric layer), and / or another pad. Examples of pad materials include tantalum nitride, titanium nitride, and / or other materials.

[0217] The source / drain contact 1145 can be deposited in one or more deposition steps. In some embodiments, a seed layer can be deposited first, and the source / drain contact 1145 can be deposited on the seed layer. In some embodiments, after depositing the source / drain contact 1145, a planarization tool 110 can be used to planarize the source / drain contact 1145. The source / drain contact 1145 may each include one or more metallic materials such as ruthenium, tungsten, cobalt, copper, titanium, molybdenum, and / or other metallic materials. The source / drain contact 1145 may include conductive plugs, vias, conductive pillars, and / or other conductive structures.

[0218] like Figure 11I As shown, additional layers and / or structures are formed on dielectric layer 1125 and / or source / drain contacts 1145. For example, dielectric layer 1150 may be formed on dielectric layer 1125 and / or source / drain contacts 1145, and source / drain interconnects 1155 may be formed in dielectric layer 1150, so that one or more source / drain interconnects 1155 are physically coupled and / or electrically coupled to one or more source / drain contacts 1145. In another example, an etch stop layer 1160 may be formed on the dielectric layer 1150 and / or the source / drain interconnect 1155, a dielectric layer 1165 may be formed on the etch stop layer 1160, and a metallization layer 1170 may be formed in the etch stop layer 1160 and the dielectric layer 1165, so that the metallization layer 1170 is physically coupled and / or electrically coupled to one or more source / drain interconnects 1155.

[0219] The deposition tool 102 can employ physical vapor deposition, atomic layer deposition, chemical vapor deposition, epitaxy, oxidation, and other techniques. Figure 1Another deposition technique and / or another suitable deposition technique are described to deposit the dielectric layer 1150. The dielectric layer 1150 may be deposited in one or more deposition steps. In some embodiments, a planarization tool 110 may be used to planarize the dielectric layer 1150 after deposition. The dielectric layer 1150 includes one or more dielectric materials, such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, and / or another dielectric material.

[0220] A recess can be formed through the dielectric layer 1150 to expose the source / drain contacts 1145. In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer 1150 to form the recess. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer 1150. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch through the dielectric layer 1150 according to the pattern to form the recess. In some embodiments, the etching step includes a plasma etching step, a wet chemical etching step, and / or another etching step. In some embodiments, a photoresist removal tool can be used to remove residual portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the recess according to the pattern.

[0221] Source / drain interconnects 1155 can be formed on the recessed source / drain contacts 1145. The deposition tool 102 and / or plating tool 112 can be fabricated using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or a combination of these techniques. Figure 1 Another deposition technique and / or another suitable deposition technique described above are used to deposit the source / drain interconnect 1155. In some embodiments, a seed layer is deposited first, and then the source / drain interconnect 1155 is deposited on the seed layer. In some embodiments, after depositing the source / drain interconnect 1155, a planarization tool 110 may be used to planarize the source / drain interconnect 1155. The source / drain interconnect 1155 may each include one or more metallic materials such as ruthenium, tungsten, cobalt, copper, titanium, molybdenum, and / or other metallic materials. The source / drain interconnect 1155 may include conductive plugs, vias, conductive pillars, and / or other conductive structures.

[0222] The deposition tool 102 can employ physical vapor deposition, atomic layer deposition, chemical vapor deposition, epitaxy, oxidation, and other techniques. Figure 1Another deposition technique and / or another suitable deposition technique are described to deposit the etch stop layer 1160 and / or the dielectric layer 1165. The etch stop layer 1160 and / or the dielectric layer 1165 may be deposited in one or more deposition steps. In some embodiments, the etch stop layer 1160 and / or the dielectric layer 1165 may be planarized using a planarization tool 110 after deposition. The etch stop layer 1160 and the dielectric layer 1165 may each include one or more dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, and / or another dielectric material.

[0223] A recess can be formed through the dielectric layer 1165 and / or the etch stop layer 1160 to expose one or more source / drain interconnects 1155. In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer 1165 and / or the etch stop layer 1160 to form the recess. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer 1165. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch through the dielectric layer 1165 and / or the etch stop layer 1160 according to the pattern to form the recess. In some embodiments, the etching step includes a plasma etching step, a wet chemical etching step, and / or another etching step. In some embodiments, a photoresist removal tool can be used to remove residual portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming recesses based on a pattern.

[0224] The metallization layer 1170 can be formed on the source / drain interconnect 1155 in the recess. The deposition tool 102 and / or plating tool 112 can be applied using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or a combination of these techniques. Figure 1 Another deposition technique and / or another deposition technique described above are used to deposit the metallization layer 1170. In some embodiments, a seed layer is deposited first, and then the metallization layer 1170 is deposited on the seed layer. In some embodiments, the metallization layer 1170 may be planarized using a planarization tool 110 after deposition. The metallization layer 1170 may include one or more metallic materials, such as ruthenium, tungsten, cobalt, copper, titanium, molybdenum, and / or other metallic materials. The metallization layer 1170 may include conductive trenches, metal lines, and / or another conductive structure.

[0225] like Figure 11JAs shown, the semiconductor device 200 is flip-flopable, and residual portions of the semiconductor substrate 205 can be removed to expose a plurality of first source / drain regions 225 of the first nanostructure transistor layer 1105a. The semiconductor device 200 can be planarized using a planarization tool 110 in a chemical mechanical polishing step, a wafer polishing step, and / or another planarization step.

[0226] like Figure 11K As shown, the first interconnect structure 1115a can be formed on the first nanostructure transistor layer 1105a. In this configuration, the first interconnect structure 1115a and the second interconnect structure 1115b are located on opposite sides of the semiconductor device 200. The first interconnect structure 1115a includes multiple dielectric layers and multiple metallization layers, which can provide signals and / or power to the nanostructure transistors in the first nanostructure transistor layer 1105a, and / or provide signals and / or power from the nanostructure transistors. The first interconnect structure 1115a and the second interconnect structure 1115b may contain similarly configured layers and / or structures, and may be formed by similar combinations. Figures 11E to 11L The steps described are formed.

[0227] Figure 11L A perspective view of a semiconductor device 200 is shown, with many dielectric layers omitted for clarity. Figure 11L As shown, the first nanostructure transistor layer 1105a may include multiple p-type source / drain regions 225a located on both sides of the first gate structure 240, and multiple n-type source / drain regions 225b located on both sides of the first gate structure 240. The p-type source / drain regions 225a and adjacent n-type source / drain regions 225b are both adjacent to the same side of the first gate structure 240. The p-type source / drain regions 225a, the first gate structure 240, and the multiple first nanostructure channels 220 (not shown) correspond to the p-type metal-oxide-semiconductor nanostructure transistors of the first nanostructure transistor layer 1105a. The n-type source / drain regions 225b, the first gate structure 240, and the multiple first nanostructure channels 220 (not shown) correspond to the n-type metal-oxide-semiconductor nanostructure transistors of the first nanostructure transistor layer 1105a.

[0228] like Figure 11LAs shown, the second nanostructure transistor layer 1105b may include multiple p-type source / drain regions 225a located on both sides of the second gate structure 240, and multiple n-type source / drain regions 225b located on both sides of the second gate structure 240. The p-type source / drain regions 225a and adjacent n-type source / drain regions 225b are all adjacent to the same side of the second gate structure 240. The p-type source / drain regions 225a, the second gate structure 240, and the multiple second nanostructure channels 220 (not shown) correspond to the p-type metal-oxide-semiconductor nanostructure transistors of the second nanostructure transistor layer 1105b. The n-type source / drain regions 225b, the second gate structure 240, and the multiple second nanostructure channels 220 (not shown) correspond to the n-type metal-oxide-semiconductor nanostructure transistors of the second nanostructure transistor layer 1105b.

[0229] A bonding dielectric layer 1110 is included between a first nanostructure transistor layer 1105a and a second nanostructure transistor layer 1105b. The first nanostructure transistor layer 1105a is located between the bonding dielectric layer 1110 and a first interconnect structure 1115a. The second nanostructure transistor layer 1105b is located between the bonding dielectric layer 1110 and the second interconnect structure 1115b.

[0230] The first interconnect structure 1115a is perpendicularly adjacent to a first side (e.g., bottom side) of the first nanostructure transistor layer 1105a, while the bonding dielectric layer 1110 is perpendicularly adjacent to a second side (e.g., top side) of the first nanostructure transistor layer 1105a, and the first and second sides of the first nanostructure transistor layer 1105a are opposite to each other. The bonding dielectric layer 1110 is perpendicularly adjacent to a first side (e.g., bottom side) of the second nanostructure transistor layer 1105b, while the second interconnect structure 1115b is perpendicularly adjacent to a second side (e.g., top side) of the second nanostructure transistor layer 1105b, and the first and second sides of the second nanostructure transistor layer 1105b are opposite to each other. The second side (e.g., top side) of the first nanostructure transistor layer 1105a and the first side (e.g., bottom side) of the second nanostructure transistor layer 1105b face each other.

[0231] like Figure 11LAs shown, the semiconductor device 200 further includes one or more conductive structures 1175 electrically connecting the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b. Each conductive structure 1175 includes a via, a conductive pillar, a through-silicon via, a through-insulator via, and / or another elongated conductive structure extending between the metallization layer 1170 of the first interconnect structure 1115a and the metallization layer 1170 of the second interconnect structure 1115b. The conductive structure 1175 extends through the first nanostructure transistor layer 1105a, through the second nanostructure transistor layer 1105b, and through the bonding dielectric layer 1110. Each conductive structure 1175 may include one or more metallic materials such as ruthenium, tungsten, cobalt, copper, titanium, molybdenum, and / or other metallic materials.

[0232] As mentioned above, providing Figures 11A to 11L The number and configuration of steps and structures shown are one or more examples. In practice, additional steps and / or structures, fewer steps and / or structures, different steps and / or structures, and / or different configurations of steps and / or structures may be used (compared to combinations). Figures 11A to 11L (The steps and / or structure described).

[0233] Figures 12A to 12C As one example, embodiment 1200 forms the conductive structure described herein in a semiconductor device 200 containing multiple stacked nanostructure transistor layers. Specifically, examples of embodiment 1200 include forming one or more conductive structures 1175 for electrical connection. Figures 11A to 11L The first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b are shown in the configuration example of the semiconductor device 200.

[0234] like Figure 12A As shown, it can be paired with Figures 11A to 11J Following the steps described, one or more steps described in conjunction with the example of embodiment 1200 are performed to form the first nanostructure transistor layer 1105a, the second nanostructure transistor layer 1105b, and the second interconnect structure 1115b. Furthermore, one or more steps described in conjunction with embodiment 1200 may be performed after the partial formation of the first interconnect structure 1115a, such as in conjunction with... Figure 11KThe description details the steps described in the example of embodiment 1200 after the formation of the etch stop layer 1120, dielectric layer 1125, pad 1140, source / drain contact 1145, and dielectric layer 1150 of the first interconnect structure 1115a. In some embodiments, the conductive structure 1175 and the source / drain interconnect 1155 are deposited together. In some embodiments, the conductive structure 1175 is deposited before the formation of the source / drain interconnect 1155. In some embodiments, the conductive structure 1175 is deposited after the formation of the source / drain interconnect 1155. After the formation of the conductive structure 1175 and the source / drain interconnect 1155, the upper surface of the conductive structure 1175 and the upper surface of the source / drain interconnect 1155 may be approximately coplanar.

[0235] like Figure 12B As shown, a conductive structure 1175 is formed to pass through the partially formed first interconnect structure 1115a, through the first nanostructure transistor layer 1105a, through the bonding dielectric layer 1110, through the second nanostructure transistor layer 1105b, and through the second interconnect structure 1115b. In an example of embodiment 1200, a conductive structure 1175 may be formed from the first interconnect structure 1115a to the second interconnect structure 1115b, such that the conductive structure 1175 lands on the metallization layer 1170 in the second interconnect structure 1115b.

[0236] To form the conductive structure 1175, one or more recesses may be formed passing through the partially formed first interconnect structure 1115a, through the first nanostructure transistor layer 1105a, through the bonding dielectric layer 1110, through the second nanostructure transistor layer 1105b, and through the second interconnect structure 1115b. In some embodiments, the pattern in the photoresist layer is used to etch through the partially formed first interconnect structure 1115a, through the first nanostructure transistor layer 1105a, through the bonding dielectric layer 1110, through the second nanostructure transistor layer 1105b, and through the second interconnect structure 1115b to form the recesses. In these embodiments, the deposition tool 102 may be used to form the photoresist layer on the dielectric layer 1150 and / or the source / drain interconnects 1155. The exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The developing tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch, according to a pattern, through a first interconnect structure 1115a, through a first nanostructure transistor layer 1105a, through a bonding dielectric layer 1110, through a second nanostructure transistor layer 1105b, and through a second interconnect structure 1115b to form a recess. In some embodiments, the etching steps include a plasma etching step, a wet chemical etching step, and / or another etching step. In some embodiments, a photoresist removal tool can be used to remove residual portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the recess according to the pattern.

[0237] Deposition tool 102 and / or plating tool 112 may employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or a combination thereof. Figure 1 Another deposition technique and / or another suitable deposition technique is described to deposit the conductive structure 1175 in the recess. The conductive structure 1175 lands on a portion of the metallization layer 1170 of the second interconnect structure 1115b exposed in the recess. The conductive structure 1175 may be deposited in one or more deposition steps. In some embodiments, a seed layer may be deposited in the recess first, and the conductive structure may be deposited on the seed layer. In some embodiments, the conductive structure 1175 may be planarized using a planarization tool 110 after deposition.

[0238] like Figure 12C As shown, after the conductive structure 1175 is formed, an etch stop layer 1160, a dielectric layer 1165, and a metallization layer 1170 of the first interconnect structure 1115a can be formed.

[0239] As mentioned above, providing Figures 12A to 12CThe number and configuration of steps and structures shown are one or more examples. In practice, additional steps and / or structures, fewer steps and / or structures, different steps and / or structures, and / or different configurations of steps and / or structures may be used (compared to combinations). Figures 12A to 12C (The steps and / or structure described).

[0240] Figures 13A to 13F As an example, the accompanying drawings illustrate embodiment 1300, which forms the conductive structure described herein in a semiconductor device 200 containing multiple stacked nanostructure transistor layers. Specifically, an example of embodiment 1300 includes forming one or more conductive structures 1175 for electrical connection. Figures 11A to 11L The semiconductor device 200 shown has a first nanostructure transistor layer 1105a and a second nanostructure transistor layer 1105b in its configuration.

[0241] like Figure 13A As shown, it can be paired with Figures 11A to 11I Following the steps described, one or more steps described in conjunction with the example of embodiment 1300 are performed to form a portion of the first nanostructure transistor layer 1105a, the second nanostructure transistor layer 1105b, and the second interconnect structure 1115b. Specifically, one or more steps described in conjunction with the example of embodiment 1200 may be performed after forming the etch stop layer 1120, dielectric layer 1125, pad 1140, source / drain contact 1145, and dielectric layer 1150 of the second interconnect structure 1115b. In some embodiments, the conductive structure 1175 and the source / drain interconnect 1155 of the second interconnect structure 1115b may be deposited together. In some embodiments, the conductive structure 1175 may be deposited before forming the source / drain interconnect 1155 of the second interconnect structure 1115b. In some embodiments, the conductive structure 1175 may be deposited before forming the source / drain interconnect 1155 of the second interconnect structure 1115b.

[0242] like Figure 13B As shown, a first portion 1305 of the conductive structure 1175 passes through the partially formed second interconnect structure 1115b and through the second nanostructure transistor layer 1105b, so that the first portion 1305 of the conductive structure 1175 lands on the bonding contact layer 1110.

[0243] To form the first portion 1305 of the conductive structure 1175, one or more recesses may be formed through the second interconnect structure 1115b formed through the portion and through the second nanostructure transistor layer 1105b to the bonding dielectric layer 1110. In some embodiments, a pattern in the photoresist layer is used to etch through the second interconnect structure 1115b formed through the portion and through the second nanostructure transistor layer 1105b to form the recesses. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the dielectric layer 1150 and / or the source / drain interconnects 1155 of the second interconnect structure 1115b. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 may be used to etch through the second interconnect structure 1115b formed through the portion according to the pattern and through the second nanostructure transistor layer 1105b to the bonding dielectric layer 1110. In some embodiments, the etching step includes a plasma etching step, a wet chemical etching step, and / or another etching step. In some embodiments, a photoresist removal tool may be used to remove residual portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming recesses based on a pattern.

[0244] Deposition tool 102 and / or plating tool 112 may employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or a combination thereof. Figure 1 Another deposition technique and / or another suitable deposition technique described above are used to deposit a first portion 1305 of the conductive structure 1175 in the recess. The first portion 1305 of the conductive structure 1175 lands on the bonding dielectric layer 1110. The first portion 1305 of the conductive structure 1175 may be deposited in one or more deposition steps. In some embodiments, a seed layer may be deposited first in the recess, and the first portion 1305 of the conductive structure 1175 may be deposited on the seed layer. In some embodiments, the first portion 1305 of the conductive structure 1175 may be planarized using a planarization tool 110 after deposition.

[0245] like Figure 13C As shown, an etch stop layer 1160, a dielectric layer 1165, and a metallization layer 1170 of the second interconnect structure 1115b can be formed after the first portion 1305 of the conductive structure 1175 is formed. The formation method of the etch stop layer 1160, dielectric layer 1165, and metallization layer 1170 of the second interconnect structure 1115b can be similar to that of a low-profile... Figure 11I The explanations are similar.

[0246] like Figure 13DAs shown, a flip semiconductor device 200 is formed, and a portion of a first interconnect structure 1115a is formed after the first portion 1305 of the conductive structure 1175 is formed. Specifically, the first interconnect structure 1115a may include an etch stop layer 1120, a dielectric layer 1125, a pad 1140, a source / drain contact 1145, and a dielectric layer 1150.

[0247] like Figure 13E As shown, the second part of the conductive structure 1175 passes through the first interconnect structure 1115a formed in part, through the first nanostructure transistor layer 1105a, and through the bonding dielectric layer 1110, so that the second part of the conductive structure 1175 lands on the first part 1305 of the conductive structure 1175 to form the conductive structure 1175.

[0248] To form the second portion of the conductive structure 1175, one or more recesses may be formed through the first interconnect structure 1115a formed in the portion, through the first nanostructure transistor layer 1105a, and through the bonding dielectric layer 1110. In some embodiments, a pattern in the photoresist layer is used to etch through the first interconnect structure 1115a formed in the portion, through the first nanostructure transistor layer 1105a, and through the bonding dielectric layer 1110 to form a recess in the first portion of the conductive structure 1175. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the dielectric layer 1150 and / or the source / drain interconnect 1155 of the first interconnect structure 1115a. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch, according to a pattern, through the partially formed first interconnect structure 1115a, through the first nanostructure transistor layer 1105a, and through the bonding dielectric layer 1110 to form a recess. In some embodiments, the etching steps include a plasma etching step, a wet chemical etching step, and / or another etching step. In some embodiments, a photoresist removal tool can be used to remove residual portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer can be used as an alternative technique for forming the recess according to the pattern.

[0249] Deposition tool 102 and / or plating tool 112 may employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or a combination thereof. Figure 1Another technique and / or another suitable deposition technique described above is used to deposit a second portion of the conductive structure 1175 in the recess. The second portion of the conductive structure 1175 lands on the first portion 1305 of the conductive structure 1175. The second portion of the conductive structure 1175 may be deposited in one or more deposition steps. In some embodiments, a seed layer is first deposited in the recess, followed by the deposition of the second portion of the conductive structure 1175 on the seed layer. In some embodiments, after depositing the second portion of the conductive structure 1175, a planarization tool 110 may be used to planarize the second portion of the conductive structure 1175.

[0250] like Figure 13F As shown, after the second part of the conductive structure 1175 is formed, an etch stop layer 1160, a dielectric layer 1165, and a metallization layer 1170 of the first interconnect structure 1115a can be formed.

[0251] As mentioned above, providing Figures 13A to 13F The number and configuration of structures and steps shown are one or more examples. In practice, additional steps and / or structures, fewer steps and / or structures, different steps and / or structures, and / or different configurations of steps and / or structures can be used (compared to combinations). Figures 13A to 13F (The steps and / or structure described).

[0252] Figures 14A to 14E As an example, the accompanying drawings show embodiment 1400 in which the stacked nanostructure transistor layers described herein are formed in semiconductor device 200. Figures 14A to 14D One or more such as Figure 5 As shown in the perspective view, including Figure 5 A cross-sectional view of section BB (in the y direction). An example of embodiment 1400 of forming stacked nanostructure transistor layers may be similar to an example of embodiment 1100 of forming stacked nanostructure transistor layers, except that a first interconnect structure 1115a is formed on the first nanostructure transistor layer 1105a, such that the first interconnect structure 1115a is located between the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b.

[0253] like Figure 14A As shown, they can be combined. Figures 3A-1 to 10C-3 The steps described are for forming the first nanostructure transistor layer 1105a of the semiconductor device 200. This can be combined... Figures 3A-1 to 10C-3 The steps described are for forming the first nanostructured transistor layer 1105a.

[0254] like Figure 14B As shown, a first interconnect structure 1115a can be formed on the first nanostructure transistor layer 1105a (e.g., in conjunction with...). Figure 11K(The explanation method is similar).

[0255] like Figure 14C As shown, a bonding dielectric layer 1110 can be formed on the first interconnect structure 1115a (and paired with) Figure 11B The description is similar), and a layered stack 305 is used to bond the second nanostructure transistor layer 1105b to the first interconnect structure 1115a (in conjunction with the dielectric layer 1110). Figure 11C (The explanation method is similar).

[0256] like Figure 14D As shown, the second nanostructure transistor layer 1105b is formed by the self-layered stacking 305 (and paired with... Figure 11D (The explanation is similar). In this method, the second nanostructure transistor layer 1105b is formed on the first nanostructure transistor layer 1105a, the first interconnect structure 1115a, and the bonding dielectric layer 1110. They can be combined. Figures 3A-1 to 10C-3 The steps described are for forming the second nanostructure transistor layer 1105b.

[0257] like Figure 14D As shown, the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b may include different numbers of nanostructure channels 200. This allows the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b to have different performance characteristics, such as different power consumption, different switching speeds, and / or different other characteristics. For example, the number of nanostructure channels 220 in the first nanostructure transistor layer 1105a (e.g., three stacked nanostructure channels 220) is greater than the number of nanostructure channels 220 in the second nanostructure transistor layer 1105b (e.g., two stacked nanostructure channels 220). This allows the energy consumption of the nanostructured transistors in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructured transistor layer 1105b to be lower than that of the nanostructured transistors in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructured transistor layer 1105a; and also allows the switching speed of the nanostructured transistors in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructured transistor layer 1105a to be faster than that of the nanostructured transistors in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructured transistor layer 1105b. The number of the plurality of nanostructured channels 220 in the second nanostructured transistor layer 1105b can be changed to be greater than the number of the plurality of nanostructured channels 220 in the first nanostructured transistor layer 1105a.

[0258] The first nanostructure transistor layer 1105a and / or the second nanostructure transistor layer 1105b having one or more other characteristics may be fabricated additionally and / or alternatively to emphasize one or more performance parameters of the first nanostructure transistor layer 1105a and / or the second nanostructure transistor layer 1105b. For example, the length of the plurality of first nanostructure channels 220 of the first nanostructure transistor layer 1105a (e.g., in the y-direction between the plurality of first source / drain regions 225) may be greater than the length of the plurality of second nanostructure channels 220 of the second nanostructure transistor layer 1105b (e.g., in the y-direction between the plurality of second source / drain regions 225). This allows the drive current of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructure transistor layer 1105b to be greater than the drive current of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructure transistor layer 1105a; it also allows the leakage current of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the first nanostructure transistor layer 1105a to be less than the leakage current of the nanostructure transistor in the complementary metal-oxide-semiconductor integrated circuit of the second nanostructure transistor layer 1105b.

[0259] like Figure 14D As shown, the second interconnect structure 1115b can be formed on the second nanostructure transistor layer 1105b (in conjunction with...). Figures 11E to 11I (The explanation method is similar).

[0260] Figure 14E This is a perspective view of a semiconductor device 200, which omits various dielectric layers for clarity. (See figure.) Figure 14E As shown, the first nanostructure transistor layer 1105a may include multiple p-type source / drain regions 225a located on both sides of the first gate structure 240, and multiple n-type source / drain regions 225b located on both sides of the first gate structure 240. The p-type source / drain regions 225a and adjacent n-type source / drain regions 225b are both adjacent to the same side of the first gate structure 240. The p-type source / drain regions 225a, the first gate structure 240, and the multiple first nanostructure channels 220 (not shown) correspond to the p-type metal-oxide-semiconductor nanostructure transistors of the first nanostructure transistor layer 1105a. The n-type source / drain regions 225b, the first gate structure 240, and the multiple first nanostructure channels 220 (not shown) correspond to the n-type metal-oxide-semiconductor nanostructure transistors of the first nanostructure transistor layer 1105a.

[0261] like Figure 14EAs shown, the second nanostructure transistor layer 1105b may include multiple p-type source / drain regions 225a on both sides of the second gate structure 240, and multiple n-type source / drain regions 225b on both sides of the second gate structure 240. The p-type source / drain regions 225a and adjacent n-type source / drain regions 225b are both adjacent to the same side of the second gate structure 240. The p-type source / drain regions 225a, the second gate structure 240, and the multiple second nanostructure channels 220 (not shown) correspond to the p-type metal-oxide-semiconductor nanostructure transistors of the second nanostructure transistor layer 1105b. The n-type source / drain regions 225b, the second gate structure 240, and the multiple second nanostructure channels 220 (not shown) correspond to the n-type metal-oxide-semiconductor nanostructure transistors of the second nanostructure transistor layer 1105b.

[0262] A bonding dielectric layer 1110 is included between the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b. A first interconnect structure 1115a is located between the bonding dielectric layer 1110 and the first nanostructure transistor layer 1105a. A second nanostructure transistor layer 1105b is located between the bonding dielectric layer 1110 and the second interconnect structure 1115b. The bonding dielectric layer 1110 is located between the first interconnect structure 1115a and the second nanostructure transistor layer 1105b.

[0263] The first interconnect structure 1115a and the bonding dielectric layer 1110 are perpendicularly adjacent to the second side (e.g., the top side) of the first nanostructure transistor layer 1105a, while the second side of the first nanostructure transistor layer 1105a is opposite to the first side (e.g., the bottom side). The bonding dielectric layer 1110 is perpendicularly adjacent to the first side (e.g., the bottom side) of the second nanostructure transistor layer 1105b, and the second interconnect structure 1115b is perpendicularly adjacent to the second side (e.g., the top side) of the second nanostructure transistor layer 1105b, while the first side of the second nanostructure transistor layer 1105b is opposite to the second side. The second side (e.g., the top side) of the first nanostructure transistor layer 1105a and the first side (e.g., the bottom side) of the second nanostructure transistor layer 1105b face each other.

[0264] like Figure 14E As shown, the semiconductor device 200 further includes one or more conductive structures 1175 electrically connecting the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b. Each conductive structure 1175 extends between the metallization layer 1170 in the first interconnect structure 1115a and the metallization layer 1170 in the second interconnect structure 1115b. The conductive structure 1175 extends through the second nanostructure transistor layer 1105b and through the bonding dielectric layer 1110.

[0265] In the example of embodiment 1400, the conductive structure 1175 is shorter and the distance across the first interconnect structure 1115a and the second interconnect structure 1115b is shorter (compared to the conductive structure 1175 in the example of embodiment 1100). This reduces the complexity of the semiconductor process used to form the conductive structure 1175 in embodiment 1400, resulting in fewer process defects. On the other hand, before forming the first interconnect structure 1115a, the second interconnect structure 1115b, and the conductive structure 1175 (as in the example of embodiment 1100), the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b are formed. Higher process temperatures can be used when manufacturing the nanostructure transistors of the first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b, thus providing greater flexibility in material and process selection.

[0266] As mentioned above, providing Figures 14A to 14E The number and configuration of structures and steps shown are one or more examples. In practice, additional steps and / or structures, fewer steps and / or structures, different steps and / or structures, and / or different configurations of steps and / or structures can be used (compared to combinations). Figures 14A to 14E (The steps and / or structure described).

[0267] Figures 15A to 15C This is an example of embodiment 1500, which forms the conductive structure described herein in a semiconductor device 200 containing multiple stacked nanostructure transistor layers. Specifically, an example of embodiment 1500 includes forming one or more conductive structures 1175 for electrical connection. Figures 14A to 14E The first nanostructure transistor layer 1105a and the second nanostructure transistor layer 1105b are shown in the configuration example of the semiconductor device 200.

[0268] like Figure 15A As shown, in the combination Figures 14A to 14D Following the steps described, one or more steps can be performed in conjunction with the example described in Embodiment 1400 to form the first nanostructure transistor layer 1105a, the second nanostructure transistor layer 1105b, and the second interconnect structure 1115b. Furthermore, after forming a portion of the first interconnect structure 1115a, one or more steps can be performed in conjunction with the example described in Embodiment 1400, such as... Figure 14DThe description details the steps described in the example of embodiment 1400, which are performed after the steps of forming the etch stop layer 1120, dielectric layer 1125, pad 1140, source / drain contact 1145, and dielectric layer 1150 of the first interconnect structure 1115a. In some embodiments, the source / drain interconnect 1155 and the conductive structure 1175 are deposited together. In some embodiments, the conductive structure 1175 may be deposited before the source / drain interconnect 1155 is formed. In some embodiments, the conductive structure 1175 may be deposited after the source / drain interconnect 1155 is formed. After the conductive structure 1175 and the source / drain interconnect 1155 are formed, the upper surface of the conductive structure 1175 and the upper surface of the source / drain interconnect 1155 may be approximately coplanar.

[0269] like Figure 15B As shown, a conductive structure 1175 is formed to pass through the partially formed first interconnect structure 1115a, through the first nanostructure transistor layer 1105a, and through the bonding dielectric layer 1110 to the second interconnect structure 1115b. In the example of embodiment 1500, the conductive structure 1175 is formed from the first interconnect structure 1115a to the second interconnect structure 1115b, such that the conductive structure 1175 lands on the metallization layer 1170 in the second interconnect structure 1115b.

[0270] To form the conductive structure 1175, one or more recesses may be formed through the partially formed first interconnect structure 1115a, through the first nanostructure transistor layer 1105a, and through the bonding dielectric layer 1110 to the second interconnect structure 1115b. In some embodiments, the pattern in the photoresist layer is used to etch through the partially formed first interconnect structure 1115a, through the first nanostructure transistor layer 1105a, and through the bonding dielectric layer 1110 to form the recesses. In these embodiments, the deposition tool 102 may be used to form the photoresist layer on the dielectric layer 1150 and / or the source / drain interconnects 1155. The exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The developing tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch, according to a pattern, through the partially formed first interconnect structure 1115a, through the first nanostructure transistor layer 1105a, and through the bonding dielectric layer 1110 to form a recess. In some embodiments, the etching step includes a plasma etching step, a wet chemical etching step, and / or another etching step. In some embodiments, a photoresist removal tool can be used to remove residual portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the recess according to a pattern.

[0271] The deposition tool 102 and / or plating tool 112 can be used to deposit a conductive structure 1175 into the recess, and the deposition method can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or a combination thereof. Figure 1 Another deposition technique described above, and / or another suitable deposition technique. The conductive structure 1175 lands on a portion of the metallization layer 1170 of the exposed second interconnect structure 1115b in the recess. The conductive structure 1175 can be deposited by one or more deposition steps. In some embodiments, a seed layer is first deposited in the recess, and the conductive structure 1175 is deposited on the seed layer. In some embodiments, a planarization tool 110 can be used to planarize the conductive structure 1175 after deposition.

[0272] like Figure 15C As shown, after the conductive structure 1175 is formed, an etch stop layer 1160, a dielectric layer 1165, and a metallization layer 1170 of the first interconnect structure 1115a can be formed.

[0273] As mentioned above, providing Figures 15A to 15C The number and configuration of structures and steps shown are one or more examples. In practice, additional steps and / or structures, fewer steps and / or structures, different steps and / or structures, and / or different configurations of steps and / or structures can be used (compared to combinations). Figures 15A to 15C (The steps and / or structure described).

[0274] Figure 16 The accompanying drawing illustrates, in one example, the components of the apparatus 1600 described herein. In some embodiments, one or more semiconductor process tools, such as deposition tools 102 to bonding tools 114 and / or wafer / die transfer tools 116, may include one or more apparatuses 1600 and / or one or more components of apparatus 1600. Figure 16 As shown, the device 1600 may include a bus 1610, a processor 1620, a memory 1630, an input component 1640, an output component 1650, and / or a communication component 1660.

[0275] Bus 1610 includes one or more components that enable wired and / or wireless communication of components of device 1600. Bus 1610 enables... Figure 16Two or more components are coupled together, for example via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 1610 may include electrical connections (such as wiring, lines, and / or wires) and / or wireless buses. Processor 1620 may include a central processing unit, graphics processor, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another processing component. Processor 1620 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1620 includes one or more processors that can be programmed to perform one or more steps or processes described elsewhere.

[0276] Memory 1630 may include volatile and / or non-volatile memory. For example, memory 1630 may include random access memory, read-only memory, hard disk, and / or another type of memory (such as flash memory, magnetic memory, and / or optical memory). Memory 1630 may include internal memory (such as dynamic random access memory, read-only memory, or hard disk) and / or removable memory (such as removable via a Universal Serial Bus connection). Memory 1630 may be a non-transitory computer-readable medium. Memory 1630 may store data, instructions, and / or software (such as one or more software applications) related to the operation of device 1600. In some embodiments, memory 1630 includes one or more memories coupled (e.g., communication coupling) to one or more processors (such as processor 1620) via bus 1610. The communication coupling between processor 1620 and memory 1630 enables processor 1620 to read and / or process information stored in memory 1630, and / or store information in memory 1630.

[0277] Input component 1640 enables device 1600 to receive input, such as user input and / or sensed input. For example, input component 1640 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope, and / or actuator. Output component 1650 enables device 1600 to provide output, such as via a screen, speaker, and / or LED. Communication component 1660 enables device 1600 to communicate with other devices via wired and / or wireless connections. For example, communication component 1660 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0278] Apparatus 1600 may perform one or more of the steps or processes described herein. For example, a non-transitory computer-readable medium (such as memory 1630) may store a set of instructions (such as one or more instructions or codes) executed by processor 1620. Processor 1620 may execute a set of instructions to perform one or more of the steps or processes described herein. In some embodiments, one or more processors 1620 execute a set of instructions, causing one or more processors 1620 and / or apparatus 1600 to perform one or more of the steps or processes described herein. In some embodiments, hardware circuitry may replace or be combined with instructions to perform one or more of the steps or processes described herein. Processor 1620 may be additionally or alternatively configured to perform one or more of the steps or processes described herein. Therefore, the implementation methods described herein are not limited to any particular combination of hardware circuitry and software.

[0279] Figure 16 The number and arrangement of components shown are merely examples. Device 1600 may include additional components, fewer components, different components, or components with... Figure 16 The components shown are configured differently. One or more functions performed by another set of components of device 1600 may be performed by one set of components of device 1600, either additionally or alternatively.

[0280] Figure 17 As an example, a flowchart of process 1700 for forming the semiconductor device described herein is provided. In some embodiments, the process may be performed by one or more semiconductor process tools (such as one or more semiconductor process tools like deposition tool 102 to bonding tool 114). Figure 17 One or more process steps. These may additionally or alternatively be performed by one or more components of the device 1600 (e.g., processor 1620, memory 1630, input component 1640, output component 1650, and / or communication component 1660). Figure 17 One or more process steps.

[0281] like Figure 17 As shown, process 1700 may include forming a plurality of first nanostructure channel layers from a first nanostructure layered stack, the arrangement orientation of which is approximately perpendicular to the semiconductor substrate of the semiconductor device (step 1705). For example, a first nanostructure layered stack (e.g., layered stack 305) may be formed using one or more semiconductor process tools such as deposition tool 102 to bonding tool 114, including a plurality of first nanostructure channel layers (e.g., a plurality of first nanostructure channels 220), the arrangement orientation (e.g., the z-direction) of which is approximately perpendicular to the semiconductor substrate 205 of the semiconductor device 200, as described herein. In some embodiments, the plurality of first nanostructure channel layers include a first number of nanostructure channel layers.

[0282] like Figure 17As shown, process 1700 may include forming a first p-type source / drain region adjacent to a plurality of first nanostructure channel layers (step 1710). For example, one or more semiconductor process tools such as deposition tool 102 to bonding tool 114 may be used to form the first p-type source / drain region 225a adjacent to a plurality of first nanostructure channel layers, as described herein.

[0283] like Figure 17 As shown, process 1700 may include forming a first n-type source / drain region adjacent to a plurality of first nanostructure channel layers (step 1715). For example, one or more semiconductor process tools such as deposition tool 102 to bonding tool 114 may be used to form the first n-type source / drain region 225b adjacent to a plurality of first nanostructure channel layers, as described herein.

[0284] like Figure 17 As shown, process 1700 may include forming a first gate structure to cover each first nanostructure channel layer (step 1720). For example, one or more semiconductor process tools, such as deposition tool 102 to bonding tool 114, may be used to form the first gate structure 240 to cover each first nanostructure channel layer, as described herein. In some embodiments, the first nanostructure channel layer, the first p-type source / drain region 225a, the first n-type source / drain region 225b, and the first gate structure 240 are included in the first nanostructure transistor layer 1105a of the semiconductor device 200.

[0285] like Figure 17 As shown, process 1700 may include forming a bonding dielectric layer on the first nanostructure transistor layer (step 1725). For example, one or more semiconductor process tools such as deposition tool 102 to bonding tool 114 may be used to form a bonding dielectric layer 1110 on the first nanostructure transistor layer 1105a, as described herein.

[0286] like Figure 17 As shown, process 1700 may include using a bonding dielectric layer to bond a second nanostructure layered stack to a first nanostructure transistor layer (step 1730). For example, one or more semiconductor process tools, such as deposition tool 102 to bonding tool 114, may be used to bond the bonding dielectric layer 1110 to the second nanostructure layered stack (such as second layered stack 305) to the first nanostructure transistor layer 1105a, as described herein.

[0287] like Figure 17As shown, process 1700 may include forming a plurality of second nanostructure channel layers from a second nanostructure layered stack, the arrangement direction of which is approximately perpendicular to the semiconductor substrate (step 1735). For example, one or more semiconductor process tools, such as deposition tool 102 to bonding tool 114, may be used to form a plurality of second nanostructure channel layers (such as second nanostructure channel 220) from a second nanostructure layered stack, the arrangement direction (such as the z-direction) of which is approximately perpendicular to the semiconductor substrate 205, as described herein. In some embodiments, the second nanostructure channel layer includes a second number of nanostructure channel layers, which differs from the first number of nanostructure channel layers.

[0288] like Figure 17 As shown, process 1700 may include forming a second p-type source / drain region adjacent to the second nanostructure channel layer (step 1740). For example, one or more semiconductor process tools such as deposition tool 102 to bonding tool 114 may be used to form the second p-type source / drain region 225a adjacent to the second nanostructure channel layer, as described herein.

[0289] like Figure 17 As shown, process 1700 may include forming a second n-type source / drain region adjacent to the second nanostructure channel layer (step 1745). For example, one or more semiconductor process tools such as deposition tool 102 to bonding tool 114 may be used to form the second type source / drain region 225b adjacent to the second nanostructure channel layer, as described herein.

[0290] like Figure 17 As shown, process 1700 may include forming a second gate structure to cover each second nanostructure channel layer (step 1750). For example, one or more semiconductor process tools, such as deposition tool 102 to bonding tool 114, may be used to form the second gate structure 240 to cover each second nanostructure channel layer, as described herein. In some embodiments, the second nanostructure channel layer, the second p-type source / drain region 225a, the second n-type source / drain region 225b, and the second gate structure 240 are included in the second nanostructure transistor layer 1105b of the semiconductor device. The second nanostructure transistor layer 1105b and the first nanostructure transistor layer 1105a may be stacked or vertically arranged (e.g., in the z-direction) in the semiconductor device 200.

[0291] Process 1700 may include additional implementations, such as a single implementation, or any combination of one or more other processes described below and / or elsewhere.

[0292] In the first embodiment, after forming the second nanostructure transistor layer 1105b, process 1700 may form a second interconnect structure 1115b on the second nanostructure transistor layer 1105b, and after forming the second interconnect structure 1115b, a first interconnect structure 1115a may be formed on the first nanostructure transistor layer 1105a.

[0293] In the second embodiment (which can be performed alone or in combination with the first embodiment), before forming the metallization layer 1170 of the first interconnect structure 1115a, process 1700 may form a conductive structure 1175, which is coupled to the second interconnect structure 1115b and extends through the first nanostructure transistor layer 1105a, the second nanostructure transistor layer 1105b, and the bonding dielectric layer 1110. The step of forming the first interconnect structure 1115a includes forming the metallization layer 1170 of the first interconnect structure 1115a on the conductive structure 1175, thereby coupling the conductive structure 1175 to the metallization layer 1170.

[0294] In the third embodiment (which may be performed alone or in combination with one or more of the first and second embodiments), before forming the metallization layer 1170 of the second interconnect structure 1115b, process 1700 may form a first portion 1305 of the conductive structure 1175 to extend through the second nanostructure transistor layer 1105b and land on the bonding dielectric layer 1110, wherein the step of forming the second interconnect structure 1115b includes forming the metallization layer 1170 of the second interconnect structure 1115b on the first portion 1305 of the conductive structure 1175, thereby coupling the first portion 1305 of the conductive structure 1175 to the metallization layer 1170 of the second interconnect structure 1115b.

[0295] In the fourth embodiment (which may be performed alone or in combination with one or more of the first to third embodiments), after forming the second interconnect structure 1115b and before forming the metallization layer 1170 of the first interconnect structure 1115a, process 1700 may form a second portion of the conductive structure 1175, wherein the second portion of the conductive structure 1175 extends through the first nanostructure transistor layer 1105a and the bonding dielectric layer 1110 and is coupled to the first portion 1305 of the conductive structure 1175, wherein the step of forming the first interconnect structure 1115a includes forming the metallization layer 1170 of the first interconnect structure 1115a on the second portion of the conductive structure 1175, thereby coupling the second portion of the conductive structure 1175 to the metallization layer 1170 of the first interconnect structure 1115a.

[0296] In the fifth embodiment (which may be performed alone or in combination with one or more of the first to fourth embodiments), process 1700 forms a first interconnect structure 1115a on the first nanostructure transistor layer 1105a before forming the bonding dielectric layer 1110, wherein the step of forming the bonding dielectric layer 1110 includes forming the bonding dielectric layer 1110 on the first interconnect structure 1115a.

[0297] In the sixth embodiment (which may be performed alone or in combination with one or more of the first to fifth embodiments), after forming the second nanostructure transistor layer 1105b, process 1700 may form a second interconnect structure 1115b on the second nanostructure transistor layer 1105b.

[0298] Although Figure 17 Examples of the steps in display process 1700, in some embodiments of process 1700 may include additional steps, fewer steps, different steps, or configurations different from those in the display process 1700. Figure 17 The steps shown. Two or more steps of process 1700 may be performed in parallel, either additionally or alternatively.

[0299] In this approach, the semiconductor device described herein comprises multiple nanostructured transistor layers stacked or vertically arranged. Each nanostructured transistor layer includes at least one n-type metal-oxide-semiconductor (MOS) nanostructured transistor and at least one p-type MOS nanostructured transistor. The nanostructured transistor layers can be fabricated such that the n-type and p-type MOS nanostructured transistors of two or more nanostructured transistor layers possess one or more different characteristics, such as the number of nanostructured channels. This allows for optimization of the performance of the n-type and p-type MOS nanostructured transistors used in different nanostructured transistor layers for different performance parameters.

[0300] As detailed above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first nanostructure transistor layer. The first nanostructure transistor layer includes a plurality of first nanostructure channel layers extending in a first direction and disposed in a second direction, the second direction being approximately perpendicular to the first direction. The first nanostructure channel layer includes a first number of nanostructure channel layers. The first nanostructure transistor layer includes a first gate structure covering each first nanostructure channel layer. The first nanostructure transistor layer includes a first p-type source / drain region adjacent to the first nanostructure channel layer; and a first n-type source / drain region adjacent to the first nanostructure channel layer. The semiconductor device includes a second nanostructure transistor layer located on the first nanostructure transistor layer in a second direction. The second nanostructure transistor layer includes a plurality of second nanostructure channel layers extending in the first direction and disposed in the second direction, wherein the second nanostructure channel layers include a second number of nanostructure channel layers, and wherein the first number is different from the second number. The second nanostructure transistor layer includes a second gate structure covering each second nanostructure channel layer. The second nanostructure transistor layer includes a second p-type source / drain region adjacent to the second nanostructure channel layer; and a second n-type source / drain region adjacent to the second nanostructure channel layer.

[0301] In some embodiments, the semiconductor device further includes a first interconnect structure coupled to a first nanostructure transistor layer; and a second interconnect structure coupled to a second nanostructure transistor layer.

[0302] In some embodiments, the semiconductor device further includes a bonding dielectric layer located in a second direction between the first nanostructure transistor layer and the second nanostructure transistor layer.

[0303] In some embodiments, a first nanostructure transistor layer is located between a bonding dielectric layer and a first interconnect structure; and a second nanostructure transistor layer is located between a bonding dielectric layer and a second interconnect structure.

[0304] In some embodiments, the first interconnect structure is located between the first nanostructure transistor layer and the second nanostructure transistor layer in a second direction; and the second nanostructure transistor layer is located between the first interconnect structure and the second interconnect structure in a second direction.

[0305] In some embodiments, the semiconductor device further includes a bonding dielectric layer located in a second direction between the first nanostructure transistor layer and the second nanostructure transistor layer, wherein the bonding dielectric layer is located between the first interconnect structure and the second nanostructure transistor layer.

[0306] In some embodiments, the first number is greater than the second number.

[0307] As detailed above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first nanostructure transistor layer. The first nanostructure transistor layer includes a plurality of first nanostructure channel layers extending in a first direction and disposed in a second direction, the second direction being approximately perpendicular to the first direction, wherein the first nanostructure channel layers include a first number of nanostructure channel layers. The first nanostructure transistor layer includes a first gate structure covering each first nanostructure channel layer. The first nanostructure transistor layer includes a first p-type source / drain region adjacent to the first nanostructure channel layer; and a first n-type source / drain region adjacent to the first nanostructure channel layer. The semiconductor device includes a second nanostructure transistor layer. The second nanostructure transistor layer includes a plurality of second nanostructure channel layers extending in a first direction and disposed in a second direction, wherein the second nanostructure channel layers include a second number of nanostructure channel layers, and the first number is different from the second number. The second nanostructure transistor layer includes a second gate structure covering each second nanostructure channel layer. The second nanostructure transistor layer includes a second p-type source / drain region adjacent to the second nanostructure channel layer; and a second n-type source / drain region adjacent to the second nanostructure channel layer. The semiconductor device includes a first interconnect structure coupled to a first nanostructure transistor layer. The semiconductor device also includes a second interconnect structure coupled to a second nanostructure transistor layer. A bonding dielectric layer is located between the first and second nanostructure transistor layers, wherein the first nanostructure transistor layer, the second nanostructure transistor layer, the first interconnect structure, the second interconnect structure, and the bonding dielectric layer are disposed in a second direction.

[0308] In some embodiments, the semiconductor device further includes a conductive structure coupling a first interconnect structure and a second interconnect structure, wherein the conductive structure extends continuously between the first interconnect structure and the second interconnect structure.

[0309] In some embodiments, the conductive structure extends through the first nanostructure transistor layer, the second nanostructure transistor layer, and the bonding dielectric layer.

[0310] In some embodiments, the conductive structure extends through the second nanostructure transistor layer and the bonding dielectric layer.

[0311] In some embodiments, the first number is greater than the second number.

[0312] In some embodiments, the second number is greater than the first number.

[0313] As detailed above, some embodiments described herein provide methods for forming a semiconductor device. The method includes forming a plurality of first nanostructure channel layers from a first nanostructure layered stack, wherein the first nanostructure channel layers are arranged in an orientation approximately perpendicular to a semiconductor substrate of the semiconductor device, wherein the first nanostructure channel layers include a first number of nanostructure channel layers. The method includes forming a first p-type source / drain region adjacent to the first nanostructure channel layer. The method includes forming a first n-type source / drain region adjacent to the first nanostructure channel layer. The method includes forming a first gate structure to cover each first nanostructure channel layer, wherein the first nanostructure channel layer, the first p-type source / drain region, the first n-type source / drain region, and the first gate structure are included in a first nanostructure transistor layer of the semiconductor device. The method includes forming a bonding dielectric layer on the first nanostructure transistor layer. The method includes using a bonding dielectric layer to bond a second nanostructure layered stack to the first nanostructure transistor layer. The method includes forming a plurality of second nanostructure channel layers by stacking second nanostructure layers, wherein the orientation of the second nanostructure channel layers is approximately perpendicular to a semiconductor substrate, wherein the second nanostructure channel layers include a second number of nanostructure channel layers, and the second number is different from a first number. The method includes forming a second p-type source / drain region adjacent to the second nanostructure channel layers. The method includes forming a second n-type source / drain region adjacent to the second nanostructure channel layers. The method includes forming a second gate structure to cover each second nanostructure channel layer, wherein the second nanostructure channel layer, the second p-type source / drain region, the second n-type source / drain region, and the second gate structure are included in a second nanostructure transistor layer of a semiconductor device.

[0314] In some embodiments, the method further includes forming a second interconnect structure on the second nanostructure transistor layer after forming the second nanostructure transistor layer; and forming a first interconnect structure on the first nanostructure transistor layer after forming the second interconnect structure.

[0315] In some embodiments, the method further includes forming a conductive structure to couple with and extend through the first nanostructure transistor layer, the second nanostructure transistor layer, and the bonding dielectric layer before forming a metallization layer of the first interconnect structure, wherein the step of forming the first interconnect structure includes: forming a metallization layer of the first interconnect structure on the conductive structure, thereby coupling the conductive structure to the metallization layer.

[0316] In some embodiments, the method further includes forming a first portion of a conductive structure to extend through the second nanostructure transistor layer and land on a bonding dielectric layer prior to forming a metallization layer of the second interconnect structure, wherein the step of forming the second interconnect structure includes: forming a metallization layer of the second interconnect structure on the first portion of the conductive structure, thereby coupling the first portion of the conductive structure to the metallization layer of the second interconnect structure.

[0317] In some embodiments, the method further includes forming a second portion of a conductive structure after forming the second interconnect structure and before forming the metallization layer of the first interconnect structure, wherein the second portion of the conductive structure extends through the first nanostructure transistor layer and the bonding dielectric layer and is coupled to the first portion of the conductive structure, wherein the step of forming the first interconnect structure includes: forming the metallization layer of the first interconnect structure on the second portion of the conductive structure, thereby coupling the second portion of the conductive structure to the metallization layer of the first interconnect structure.

[0318] In some embodiments, the method further includes forming a first interconnect structure on a first nanostructure transistor layer prior to forming a bonding dielectric layer, wherein the step of forming the bonding dielectric layer includes forming a bonding dielectric layer on the first interconnect structure.

[0319] In some embodiments, the method further includes forming a second interconnect structure on the second nanostructure transistor layer after forming the second nanostructure transistor layer.

[0320] The terms "approximately" and "substantially" can refer to a change of less than 5% in a given quantity or range of values ​​(e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and not limiting. It should be understood that, according to embodiments of the present invention, the terms "approximately" and "substantially" can refer to a percentage of a given value.

[0321] The term "meets the critical value" as used herein, depending on the context, can mean greater than the critical value, greater than or equal to the critical value, less than the critical value, less than or equal to the critical value, equal to the critical value, not equal to the critical value, or a similar definition. The features of the above embodiments are beneficial for those skilled in the art to understand this utility model. Those skilled in the art should understand that this utility model can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this utility model, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this utility model.

Claims

1. A semiconductor device, characterized in that, include: A first nanostructure transistor layer, comprising: Multiple first nanostructured channel layers extend in a first direction and are disposed in a second direction, wherein the second direction is approximately perpendicular to the first direction. The plurality of the first nanostructure channel layers include a first number of nanostructure channel layers; A first gate structure, covering each of the plurality of first nanostructure channel layers; A first p-type source / drain region, adjacent to multiple first nanostructure channel layers; and A first n-type source / drain region, adjacent to multiple first nanostructure channel layers; and A second nanostructure transistor layer, located on the first nanostructure transistor layer in the second direction, includes: Multiple second nanostructured channel layers extend in the first direction and are disposed in the second direction. The plurality of the second nanostructure channel layers include a second number of nanostructure channel layers, and wherein the first number is different from the second number; A second gate structure, covering each of the plurality of second nanostructure channel layers; A second p-type source / drain region, adjacent to multiple second nanostructure channel layers; and A second n-type source / drain region is adjacent to multiple second nanostructure channel layers.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A first interconnect structure is coupled to the first nanostructure transistor layer; as well as A second interconnect structure is coupled to the second nanostructure transistor layer.

3. The semiconductor device as claimed in claim 2, characterized in that, Also includes: A bonding dielectric layer is located between the first nanostructure transistor layer and the second nanostructure transistor layer in the second direction.

4. The semiconductor device as claimed in claim 3, characterized in that, The first nanostructure transistor layer is located between the bonding dielectric layer and the first interconnect structure; and The second nanostructure transistor layer is located between the bonding dielectric layer and the second interconnect structure.

5. The semiconductor device as claimed in claim 2, characterized in that, The first interconnect structure is located between the first nanostructure transistor layer and the second nanostructure transistor layer in the second direction; and The second nanostructure transistor layer is located between the first interconnect structure and the second interconnect structure in the second direction.

6. A semiconductor device, characterized in that, include: A first nanostructure transistor layer, comprising: Multiple first nanostructure channel layers extend in a first direction and are disposed in a second direction, wherein the second direction is approximately perpendicular to the first direction. The plurality of the first nanostructure channel layers include a first number of nanostructure channel layers; A first gate structure, covering each of the plurality of first nanostructure channel layers; A first p-type source / drain region, adjacent to multiple first nanostructure channel layers; and A first n-type source / drain region is adjacent to multiple first nanostructure channel layers; A second nanostructure transistor layer, comprising: Multiple second nanostructured channel layers extend in the first direction and are disposed in the second direction. The plurality of the second nanostructure channel layers include a second number of nanostructure channel layers, and wherein the first number is different from the second number; A second gate structure, covering each of the plurality of second nanostructure channel layers; A second p-type source / drain region, adjacent to multiple second nanostructure channel layers; and A second n-type source / drain region is adjacent to multiple second nanostructure channel layers; A first interconnect structure is coupled to the first nanostructure transistor layer; A second interconnect structure, coupled to the second nanostructure transistor layer; and A bonding dielectric layer is located between the first nanostructure transistor layer and the second nanostructure transistor layer. The first nanostructure transistor layer, the second nanostructure transistor layer, the first interconnect structure, the second interconnect structure, and the bonding dielectric layer are disposed in the second direction.

7. The semiconductor device as claimed in claim 6, characterized in that, Also includes: A conductive structure couples the first interconnect structure to the second interconnect structure. The conductive structure extends continuously between the first interconnect structure and the second interconnect structure.

8. The semiconductor device as claimed in claim 7, characterized in that, The conductive structure extends through the first nanostructure transistor layer, the second nanostructure transistor layer, and the bonding dielectric layer.

9. The semiconductor device as claimed in claim 7, characterized in that, The conductive structure extends through the second nanostructure transistor layer and the bonding dielectric layer.

10. The semiconductor device as claimed in claim 6, characterized in that, The first number is greater than the second number.

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