Semiconductor structure

Abstract

The semiconductor structure includes nanostructure channels formed between a plurality of source / drain regions. The semiconductor structure includes a gate structure formed around the nanostructure channel. The semiconductor structure includes a spacer between the interlayer dielectric layer and the gate structure. The semiconductor structure includes an interface layer contacting the nanostructure channel and the spacer, the interface layer including silicon oxide, and the thickness of the interface layer being approximately 0.5 nm to approximately 1.0 nm.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to semiconductor structures having an interface layer of uniform thickness on channels and spacers. Background Technology

[0002] As semiconductor device manufacturing methods advance and process node sizes shrink, short-channel effects such as hot carrier degradation, barrier reduction, quantum confinement, and other effects can impact transistors. Furthermore, as transistor gate sizes shrink for smaller process nodes, source / drain electron tunneling increases, leading to increased transistor turn-off current (the current flowing through the transistor channel when the transistor is turned off). Silicon / silicon-germanium nanostructure transistors (such as nanowires, nanosheets, nanoribbons, multi-bridge channels, and fully wound gate devices) are strong candidates for overcoming short-channel effects at smaller process nodes. Compared to other types of transistors, nanostructure transistors can effectively reduce short-channel effects and improve carrier mobility. Utility Model Content

[0003] The purpose of this invention is to propose a semiconductor structure to solve at least one of the above-mentioned problems.

[0004] Some embodiments described herein provide semiconductor structures. The semiconductor structure includes nanostructured channels formed between multiple source / drain regions. The semiconductor structure includes a gate structure formed around the nanostructured channels. The semiconductor structure includes spacers located between an interlayer dielectric layer and the gate structure. The semiconductor structure includes an interface layer contacting the nanostructured channels and the spacers, the interface layer comprising silicon oxide, and the thickness of the interface layer being approximately 0.5 nm to approximately 1.0 nm.

[0005] According to one embodiment of the present invention, it further includes: an inner spacer located between the plurality of source / drain regions and the gate structure, wherein the interface layer is in contact with the inner spacer.

[0006] According to one embodiment of the present invention, the portion of the interface layer that contacts the nanostructure channel, the portion of the interface layer that contacts the spacer, and the portion of the interface layer that contacts the inner spacer have the same thickness.

[0007] According to one embodiment of the present invention, it further includes: an oxygen-rich layer located at the interface between the nanostructure channel and the inner spacer.

[0008] According to one embodiment of the present invention, the ratio of the thickness of the inner spacer to the thickness of the interface layer is 4.0 to 8.0.

[0009] According to one embodiment of the present invention, the thickness of the inner spacer is 3.5 nm to 4.5 nm.

[0010] According to one embodiment of the present invention, the interface layer is in further contact with the interface between the nanostructure channel and the spacer.

[0011] According to one embodiment of the present invention, the ratio of the thickness of the spacer to the thickness of the interface layer is 4.0 nm to 8.0 nm.

[0012] According to one embodiment of the present invention, the thickness of the spacer is 3.5 nm to 4.5 nm.

[0013] According to one embodiment of the present invention, the portion of the interface layer that contacts the nanostructure channel and the portion of the interface layer that contacts the spacer have the same thickness. Attached Figure Description

[0014] Figure 1 The accompanying drawings illustrate, as one example, an environment in which the systems and / or methods described herein may be implemented.

[0015] Figure 2 The accompanying drawing shows, for example, the semiconductor device described herein.

[0016] Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 The attached figure shows an example of implementing the fin formation process described herein.

[0017] Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 The attached diagram illustrates an example of implementing the shallow trench isolation process described herein.

[0018] Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 and Figure 5C-2 The attached figure shows an example of implementing the cover sidewall formation process described herein.

[0019] Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 and Figure 6C-2 The attached figure shows an example of implementing the hybrid fin structure formation process described herein.

[0020] Figure 7A , Figure 7B-1 , Figure 7B-2 and Figure 7B-3The attached figure shows an example of implementing the dummy gate structure formation process described herein.

[0021] Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 and Figure 8D-3 The attached diagram illustrates, as in one example, the source / drain recess formation process and the inner spacer formation process described herein.

[0022] Figure 9-1 , Figure 9-2 and Figure 9-3 The attached diagram illustrates, for example, the source / drain region formation process described herein.

[0023] Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , Figure 10C-2 , Figure 10C-3 , Figure 10D , Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 , Figure 10G-3 and 10H The attached figure shows an example of implementing the interface layer formation process described herein.

[0024] Figure 11-1 , Figure 11-2 and Figure 11-3 The attached figure shows an example of implementing the gate replacement process described herein.

[0025] Figure 12 The accompanying drawings are for one example of the components of one or more devices described herein.

[0026] Figure 13 As an example, a flowchart of the relevant process for forming the semiconductor device described herein is provided.

[0027] The attached figures are labeled as follows:

[0028] AA, BB, CC: Cross-section

[0029] 100: Environment

[0030] 102: Sedimentation tools

[0031] 104: Exposure Tools

[0032] 106: Developing tools

[0033] 108: Etching Tools

[0034] 110: Flattening tool

[0035] 112: Plating tools

[0036] 114: Chip and / or die transfer tools

[0037] 200: Semiconductor devices

[0038] 200A, 200B, 200C: Areas

[0039] 205: Semiconductor substrate

[0040] 210: Countertop area

[0041] 215: Shallow trench isolation zone

[0042] 220: Nanostructured Channels

[0043] 225: Source / Drain Region

[0044] 230: Buffer

[0045] 235, 325: Cap layer

[0046] 240: Gate structure

[0047] 245: Inner spacer

[0048] 250, 410, 610: Dielectric layer

[0049] 300, 400, 500, 600, 700, 800, 900, 1000, 1100: Implementation methods

[0050] 305: Layered stacking

[0051] 310: First Floor

[0052] 315: Second Floor

[0053] 320,715: Hard mask layer

[0054] 330: Oxide layer

[0055] 335: Nitride layer

[0056] 340: Part

[0057] 345: Fin-like structure

[0058] 345a: First group of fin-like structures

[0059] 345b: Second group of fin-like structures

[0060] 405, 605: Gaskets

[0061] 505: Coating

[0062] 510: Covering the sidewall

[0063] 615,1010b: High dielectric constant layer

[0064] 620: Hybrid fin structure

[0065] 705: Dummy Gate Structure

[0066] 710: Gate layer

[0067] 720: Spacer layer

[0068] 725: Gate dielectric layer

[0069] 805: Source / Drain Recess

[0070] 810: Void

[0071] 815: Insulation layer

[0072] 1005: Opening

[0073] 1010, 1020: Barrier layer

[0074] 1010a: Interface Layer

[0075] 1015a: Amorphous silicon

[0076] 1015a': Seed crystal layer

[0077] 1015b: Crystalline silicon

[0078] 1200: Device

[0079] 1210: Busbar

[0080] 1220: Processor

[0081] 1230: Memory

[0082] 1240: Input Component

[0083] 1250: Output component

[0084] 1260: Communication components

[0085] 1300: Process

[0086] 1310, 1320, 1330, 1340: Steps Detailed Implementation

[0087] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity.

[0088] The following disclosure provides many different embodiments or examples to implement different features of this invention. The following disclosure illustrates specific examples of the various components and their arrangements for simplification. These specific examples are not intended to limit the embodiments of this utility model. For example, if the embodiments of this utility model describe a first structure formed on a second structure, it means that the first structure may be in direct contact with the second structure, or an additional structure may be formed between the first and second structures, so that the first and second structures are not in direct contact. Furthermore, the use of repeated reference numerals in various embodiments of this utility model for simplification or clarity does not imply that structures with the same reference numerals in various embodiments and / or arrangements have the same relative relationship.

[0089] In addition, spatial relative terms such as “below,” “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures in the accompanying drawings and other elements or structures. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0090] Nanostructured transistors (such as nanowire transistors, nanosheet transistors, fully wound gate transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors) can overcome one or more of the drawbacks of fin field-effect transistors (FETs). However, nanostructured transistors face fabrication challenges that can lead to performance issues and / or device failure. For example, the thickness of the interface layer between the channel and the gate in nanostructured transistors needs to be reduced to approximately 1 nm to further improve miniaturization. One process used to grow such a thin interface layer is atomic layer deposition. However, atomic layer deposition is difficult to control and often results in some parts of the interface layer being too thick, reducing gate efficiency, and other parts being too thin, causing leakage current outside the channel.

[0091] Some embodiments described herein provide nanostructured transistors and methods for forming them. In some embodiments, the interface layer is formed using a fresh silicon capping process. For example, using diethylpropylaminosilane as a precursor, amorphous silicon can be formed on the spacers and crystalline silicon on the channels. The amorphous silicon and crystalline silicon can be oxidized to form the interface layer, which can have a relatively uniform thickness, such as approximately 0.5 nm to approximately 1.0 nm. This improves structure miniaturization and gate efficiency, and reduces leakage current outside the channels.

[0092] Figure 1 As an example, the accompanying drawings illustrate an environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, an example of environment 100 may include multiple semiconductor process tools such as deposition tools 102 to plating tools 112 and wafer and / or die transfer tools 114. These multiple semiconductor process tools, such as deposition tools 102 to plating tools 112, may include deposition tool 102, exposure tool 104, developing tool 106, etching tool 108, planarization tool 110, plating tool 112, and / or another semiconductor process tool. The tools included in the example of environment 100 may be found in semiconductor cleanrooms, semiconductor foundries, semiconductor fabrication plants, manufacturing plants, and / or other facilities.

[0093] The deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices for depositing various materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coater for depositing a photoresist layer onto a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition tool, such as a plasma-assisted chemical vapor deposition tool, a high-density plasma-assisted chemical vapor deposition tool, a sub-pressure chemical vapor deposition tool, a low-pressure chemical vapor deposition tool, an atomic layer deposition tool, a plasma-assisted atomic layer deposition tool, or another type of chemical vapor deposition tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition tool, such as a sputtering tool or another type of physical vapor deposition tool. In some embodiments, the deposition tool 102 includes an epitaxial tool configured to epitaxially grow layers and / or regions. In some embodiments, examples of the environment 100 include various deposition tools 102.

[0094] Exposure tool 104 is a semiconductor process tool that can be irradiated with a photoresist layer by a radiation source such as an ultraviolet light source (e.g., deep ultraviolet light source, extreme ultraviolet light source, and / or similar light source), an X-ray source, an electron beam source, and / or similar light source. Exposure tool 104 can be irradiated with a radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, patterns for forming one or more structures of a semiconductor device, patterns for etching various portions of a semiconductor device, and / or similar patterns. In some embodiments, exposure tool 104 includes a scanner, a stepper, and / or similar types of exposure tools.

[0095] The developing tool 106 is a semiconductor process tool that develops the photoresist layer exposed to the X-ray source to develop the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 can remove the unexposed portions of the photoresist layer to develop the pattern. In some embodiments, the developing tool 106 can remove the exposed portions of the photoresist layer to develop the pattern. In some embodiments, the developing tool 106 can use a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer to develop the pattern.

[0096] Etching tool 108 is a semiconductor process tool that can etch various materials from substrates, wafers, or semiconductor devices. For example, etching tool 108 may include wet etching tools, dry etching tools, and / or similar tools. In some embodiments, etching tool 108 includes a chamber for filling with an etchant, and a substrate may be placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, etching tool 108 may employ plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may use ionized gases to etch one or more portions isotropically or directionally. In some embodiments, etching tool 108 includes a plasma-based ashing stage to remove photoresist material and / or another material.

[0097] Planarization tool 110 is a semiconductor process tool that can grind or planarize various layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical polishing tool and / or another planarization tool that can grind or planarize layers or surfaces of deposited or plated materials. Planarization tool 110 can grind or planarize the surface of a semiconductor device using a combination of chemical and mechanical forces (such as chemical etching and free abrasive polishing). Planarization tool 110 may employ abrasives and corrosive chemical polishing slurries, along with a polishing pad and a retaining ring (typically larger in diameter than the semiconductor device). The polishing pad and semiconductor device may be pressed together by a dynamic polishing head and held by the retaining ring. The dynamic polishing head may rotate along different axes of rotation to remove material and flush any irregularities in the semiconductor device, making the semiconductor device smooth or planar.

[0098] The plating tool 112 is a semiconductor process tool that can plate one or more metals onto a substrate (such as a wafer, semiconductor device, and / or the like) or a portion thereof. For example, the plating tool 112 may include a copper plating apparatus, an aluminum plating apparatus, a nickel plating apparatus, a tin plating apparatus, an electroplating apparatus for compound materials or alloys (such as tin-silver, tin-lead, and / or the like), and / or an electroplating apparatus for one or more other types of conductive materials, metals, and / or similar materials.

[0099] The wafer and / or die transfer tool 114 includes mobile robots, robotic arms, light rail or railcars, overhead cranes, automated material handling systems, and / or other devices used for transferring substrates and / or semiconductor devices between semiconductor process tools such as deposition tool 102 to plating tool 112, between process chambers of the same semiconductor tool, and / or from other locations (such as wafer racks, storage chambers, or another location) or to other locations. In some embodiments, the wafer and / or die transfer tool 114 is a programmable tool configured to transport along a specific path and / or operate automatically or semi-automatically. In some embodiments, the environment 100 includes multiple wafer and / or die transfer tools 114.

[0100] For example, the wafer and / or die transfer tool 114 may be included in a clustering tool or another tool having multiple process chambers, and may be configured to transfer substrates and / or semiconductor devices between multiple process chambers, between process chambers and buffer zones, between process chambers and interface tools (such as equipment front-end modules), between process chambers and transfer carriers (such as front-opening wafer transfer boxes), and / or similar arrangements. In some embodiments, the wafer and / or die transfer tool 114 may be included in a multi-chamber (or clustering) deposition tool 102, which may include multiple pre-cleaning process chambers (for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from the substrate and / or semiconductor devices) and multiple deposition process chambers (such as process chambers for depositing different types of materials, or process chambers for performing different types of deposition steps). In these embodiments, the wafer and / or die transfer tool 114 is configured to transfer the substrate and / or semiconductor device between the process chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partially removing the vacuum) between the process chambers of the deposition tool 102 and / or between deposition steps, as described herein.

[0101] As described herein, semiconductor process tools such as deposition tools 102 to plating tools 112 can be used to perform combinations of steps to form one or more portions of a nanostructured transistor. In some embodiments, the combination of steps includes growing a seed layer on a spacer, depositing silicon on the seed layer to form amorphous silicon and depositing silicon on the channel to form crystalline silicon, oxidizing the amorphous silicon and crystalline silicon to form an interface layer, forming a high-dielectric-constant layer on the interface layer, and / or other steps.

[0102] Figure 1 The number and configuration of devices shown are for illustrative purposes only. In practice, there may be additional devices, fewer devices, different devices, or devices with different configurations (compared to combinations). Figure 1 (The device described). Furthermore, Figure 1 The two or more devices shown can be implemented in a single device, or Figure 1 The single device shown can be implemented in multiple distributed devices. A group of devices in environment 100 (such as one or more devices) can additionally or alternatively perform one or more functions performed by another group of devices in environment 100.

[0103] Figure 2 The accompanying drawings illustrate an example of the semiconductor device 200 described herein. The semiconductor device 200 includes one or more transistors. These transistors may include nanostructured transistors such as nanowire transistors, nanosheet transistors, fully wound gate transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors. The semiconductor device 200 may include one or more... Figure 2 Additional devices, structures, and / or layers not shown. For example, semiconductor device 200 may include additional layers and / or dies formed on... Figure 2 The semiconductor device 200 shown is on a layer above and / or below a portion of the semiconductor device 200. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed on an electronic device or integrated circuit (which includes semiconductor devices such as...) Figure 2 In the same layer of the semiconductor device 200 shown. Figure 3A-1 , Figure 3A-2 , Figure 3B-1 , Figure 3B-2 , Figure 4A-1 , Figure 4A-2 , Figure 4B-1 , Figure 4B-2 , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 , Figure 5C-2 , Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 , Figure 6C-2 , Figure 7A , Figure 7B-1 , Figure 7B-2 , Figure 7B-3 , Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 , Figure 8D-3 , Figure 9-1 , Figure 9-2 , Figure 9-3 , Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , Figure 10C-2 , Figure 10C-3 , Figure 10D , Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 , Figure 10G-3 , Figure 10H , Figure 11-1 , Figure 11-2 and Figure 11-3 for Figure 2 The diagram shows cross-sectional views of various parts of the semiconductor device 200, corresponding to various process stages in forming the nanostructure transistors of the semiconductor device 200.

[0104] Semiconductor device 200 includes a semiconductor substrate 205. Semiconductor substrate 205 includes a silicon substrate, a substrate formed of a silicon-containing material, a substrate of a III-V group semiconductor compound material (such as gallium arsenide), a silicon-on-insulator substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or another semiconductor substrate. Semiconductor substrate 205 may include various layers (such as conductive or insulating layers) formed on the semiconductor substrate. Semiconductor substrate 205 may include semiconductor compounds and / or semiconductor alloys. Semiconductor substrate 205 may include various doping configurations to conform to one or more design parameters. For example, different doping profiles (such as n-type wells or p-type wells) may be formed on regions of semiconductor substrate 205, and the regions may be designed for different device types (such as p-type metal-oxide-semiconductor nanostructure transistors and n-type metal-oxide-semiconductor nanostructure transistors). Suitable doping methods may include ion implantation dopant and / or diffusion processes. Furthermore, semiconductor substrate 205 may include epitaxial layers, may have stress to improve performance, and / or may have other suitable enhancement structures. Semiconductor substrate 205 may include a portion of a semiconductor wafer on which other semiconductor devices may be formed.

[0105] Mesa regions 210 may be contained on and / or extend above semiconductor substrate 205. The mesa regions 210 provide a structure in which nanostructures of the semiconductor device 200 can be formed, such as nanostructure channels, nanostructure gate portions covering each nanostructure channel, sacrificial nanostructures, and / or other structures. In some embodiments, one or more mesa regions 210 are formed within and / or from fin structures (such as silicon fin structures), and the fin structures are formed in the semiconductor substrate 205. Mesa regions 210 and semiconductor substrate 205 may include the same material and may be formed from semiconductor substrate 205. In some embodiments, mesa regions 210 are doped to form different types of nanostructure transistors, such as p-type nanostructure transistors and / or n-type nanostructure transistors. In some embodiments, mesa regions 210 include silicon or another semiconductor element material such as germanium. In some embodiments, the mesa region 210 includes semiconductor alloy materials such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or combinations thereof.

[0106] The mesa region 210 can be fabricated using suitable semiconductor process technologies, such as masking, photolithography, etching, and / or other processes. For example, the fin structure can be formed by etching a portion of the semiconductor substrate 205 to form a recess in the semiconductor substrate 205. An isolation material can then be filled into the recess, and the isolation material can be recessed or etched back to form a shallow trench isolation region 215 on the semiconductor substrate 205 between the fin structure and the mesa region. Source / drain recesses can be formed in the fin structure, resulting in the mesa region 210 being formed between the source / drain recesses. However, other fabrication techniques can also be used to form the shallow trench isolation region 215 and / or the mesa region 210.

[0107] Shallow trench isolation region 215 can electrically isolate adjacent fin structures and can provide other layers and / or layers on which the semiconductor device 200 is formed. Shallow trench isolation region 215 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, low dielectric constant dielectric materials, and / or another suitable insulating material. Shallow trench isolation region 215 may include a multilayer structure, such as having one or more pad layers.

[0108] Semiconductor device 200 includes a plurality of nanostructured channels 220 that extend between and are electrically coupled to source / drain regions 225. The source / drain region may refer to a single source or drain, or source and drain, depending on the context. The nanostructured channels 220 are arranged approximately perpendicular to the semiconductor substrate 205. In other words, the nanostructured channels 220 are vertically arranged or stacked on the semiconductor substrate 205.

[0109] The nanostructure channel 220 includes silicon-based nanostructures (such as nanosheets, nanowires, or other examples) that can serve as semiconductor channels for nanostructured transistors in the semiconductor device 200. In some embodiments, the nanostructure channel 220 may include silicon-germanium or another silicon-based material. The source / drain region 225 includes silicon with one or more dopants such as p-type materials (such as boron, gallium, or other materials), n-type materials (such as phosphorus, arsenic, or other materials), and / or another type of dopant. In summary, the semiconductor device 200 may include p-type metal-oxide-semiconductor nanostructured transistors (which include p-type source / drain regions 225), n-type metal-oxide-semiconductor nanostructured transistors (which include n-type source / drain regions 225), and / or other types of nanostructured transistors.

[0110] In some embodiments, buffer 230 is located between and below the fin structure on semiconductor substrate 205 and the source / drain region 225. Buffer 230 provides isolation between the source / drain region 225 and the adjacent mesa region 210. Buffer 230 can reduce, minimize, and / or prevent electrons from passing through mesa region 210 (instead passing through nanostructured channels 220 to reduce leakage current), and / or reduce, minimize, and / or prevent dopants from entering mesa region 210 from source / drain region 225 (which can reduce short-channel effects).

[0111] Capping layer 235 may be located above and / or below source / drain region 225. Capping layer 235 may include silicon, silicon-germanium, doped silicon, doped silicon-germanium, and / or another material. Capping layer 235 may reduce dopant diffusion and protect source / drain region 225 during semiconductor process steps used in semiconductor device 200 prior to junction formation. In addition, capping layer 235 facilitates the formation of metal-semiconductor alloys (such as silicides).

[0112] At least one set of nanostructured channels 220 extends through one or more gate structures 240. The gate structure 240 may be composed of one or more metallic materials, one or more high-dielectric-constant materials, and / or one or more other types of materials. In some embodiments, a dummy gate structure (such as a polysilicon gate structure or another gate structure) is formed at the location of the gate structure 240 (before the formation of the gate structure 240), thus allowing one or more other layers and / or structures of the semiconductor device 200 to be formed prior to the formation of the gate structure 240. This reduces and / or avoids damage to the gate structure 240, which might otherwise be caused by the steps of forming one or more layers and / or structures. A gate replacement process is then performed to remove the dummy gate structure and replace it with the gate structure 240 (e.g., a gate replacement structure).

[0113] like Figure 2 As shown, portions of the gate structure 240 are formed between pairs of nanostructure channels 220 in a staggered, vertically arranged configuration. In other words, the semiconductor device 200 includes one or more vertically stacked portions of the staggered nanostructure channels 220 and the gate structure 240, as... Figure 2 As shown. In this approach, the gate structure 240 covers multiple sides of the associated nanostructure channel 220 to increase the control of the nanostructure channel 220, increase the drive current used by the nanostructure transistor of the semiconductor device 200, and reduce the short-channel effect of the nanostructure transistor of the semiconductor device 200.

[0114] Such as pairing Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , Figure 10C-2 , Figure 10C-3 , Figure 10D , Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 , Figure 10G-3 and Figure 10H The detailed description allows for the formation of an interface layer between the gate structure 240 and the nanostructure channel 220. For example, the interface layer may be composed of a dielectric material such as an oxide (e.g., silicon oxide) to suppress electron tunneling out of the nanostructure channel 220. Furthermore, the thickness of the interface layer is approximately 0.5 nm to approximately 1.0 nm. Choosing a thickness of no more than 1.0 nm allows for significant miniaturization of the gate structure 240 and the nanostructure channel 220, as a thicker interface layer would reduce the efficiency of the gate structure 240. Choosing a thickness of at least 0.5 nm helps avoid leakage current in the nanostructure channel 220, as a thinner interface layer could allow electrons to tunnel out of the nanostructure channel 220 (e.g., tunneling to the inner spacer 245, as described below).

[0115] Two or more nanostructured transistors in semiconductor device 200 may share some source / drain regions 225 and gate structure 240. In these embodiments, one or more source / drain regions 225 and gate structure 240 may be connected to or coupled to multiple nanostructured channels 220, such as... Figure 2 The example shown. This can be achieved by controlling multiple nanostructured channels 220 with a single gate structure 240 and a pair of source / drain regions 225.

[0116] An inner spacer 245 may be located between the source / drain region 225 and the adjacent gate structure 240. Specifically, the inner spacer 245 may be located between the source / drain region 225 and the portion of the gate structure 240 that covers multiple nanostructure channels 220. The inner spacer 245 is located at the end of the portion of the gate structure 240 that covers the multiple nanostructure channels 220. The inner spacer 245 is contained within a void, and the void is formed between the end portions of adjacent nanostructure channels 220. The inner spacer 245 can reduce parasitic capacitance and protect the source / drain region 225 from etching during the nanosheet release step of removing sacrificial nanosheets between nanostructure channels 220. The inner spacer 245 includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, and / or another dielectric material.

[0117] In some embodiments, the semiconductor device 200 includes a hybrid fin structure (not shown). The hybrid fin structure can also be considered as a dummy fin, a hybrid fin, an active fin, or the like. The hybrid fin structure may be located between adjacent source / drain regions 225, between portions of the gate structure 240, between stacks of adjacent nanostructure channels 220, and / or between other structures. The hybrid fin extends approximately perpendicular to the gate structure 240.

[0118] Hybrid fin structures are configured to provide electrical isolation between two or more structures and / or components in the semiconductor device 200. In some embodiments, the hybrid fin structures are configured to provide electrical isolation between stacks of two or more nanostructure channels 220. In some embodiments, the hybrid fin structures are configured to provide electrical isolation between two or more source / drain regions 225. In some embodiments, the hybrid fin structures are configured to provide electrical isolation between portions of two or more gate structures. In some embodiments, the hybrid fin structures are configured to provide electrical isolation between the source / drain regions 225 and the gate structure 240.

[0119] Hybrid fin structures may include a variety of dielectric materials. Hybrid fin structures may include a combination of one or more low dielectric constant dielectric materials (such as silicon oxide, silicon nitride and / or other materials) and one or more high dielectric constant dielectric materials (such as hafnium oxide and / or other high dielectric constant dielectric materials).

[0120] Semiconductor device 200 may also include an interlayer dielectric layer, such as dielectric layer 250, on shallow trench isolation region 215. Dielectric layer 250 can be considered as a zeroth interlayer dielectric layer. Dielectric layer 250 surrounds gate structure 240 to provide electrical isolation and / or insulation between gate structure 240, source / drain region 225, and / or other structures. Conductive structures such as contacts and / or interconnects may pass through dielectric layer 250 to source / drain region 225 and gate structure 240 to control source / drain region 225 and gate structure 240.

[0121] As mentioned above, providing Figure 2 As an example, other examples may differ from the collocation. Figure 2 Examples to illustrate.

[0122] Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 As an example, this is an example of embodiment 300 of the fin formation process described herein. An example of embodiment 400 includes forming a fin structure for use in a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2One or more additional devices, structures, and / or layers not shown. Semiconductor device 200 may include additional layers and / or dies formed on... Figure 3A-1 , 3A-2 Above and / or below portions of the semiconductor device 200 shown in 3B-1 and 3B-2. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed in the same layer of the electronic device containing the semiconductor device 200.

[0123] Figure 3A-1 A perspective view of the semiconductor device 200 is shown, while Figure 3A-2 Show a sectional view along section AA in the perspective view. For example... Figure 3A-1 and Figure 3A-2 As shown, the semiconductor substrate 205 can be processed to form the semiconductor device 200. A layered stack 305 is formed on the semiconductor substrate 205. The layered stack 305 can be considered as a superlattice. In some embodiments, one or more steps related to the semiconductor substrate 205 may be performed before the layered stack 305 is formed. For example, a breakdown implantation step may be performed. A breakdown implantation step may be performed in one or more regions of the semiconductor substrate, on which nanostructured channels 220 may be formed. For example, a breakdown implantation step may be performed to reduce and / or avoid breakdown or unwanted diffusion into the semiconductor substrate 205.

[0124] The layered stack 305 includes multiple staggered layers arranged approximately perpendicular to the semiconductor substrate 205. For example, the layered stack 305 includes a first layer 310 and a second layer 315 that are vertically staggered on the semiconductor substrate 205. Figure 3A-1 and Figure 3A-2 The number of first layers 310 and second layers 315 shown is for illustrative purposes only, and other numbers of first layers 310 and second layers 315 are also within the scope of embodiments of this utility model. In some embodiments, the thicknesses of the first layers 310 and second layers 315 are different. For example, the thickness of the second layer 315 may be greater than the thickness of the first layer 310. In some embodiments, the thickness of the first layer 310 (or a group of first layers 310) may be approximately 4 nm to approximately 7 nm. In some embodiments, the thickness of the second layer 315 (or a group of second layers 315) may be approximately 8 nm to approximately 12 nm. However, other values ​​used for the thickness of the first layer 310 and the second layer 315 are also within the scope of embodiments of this utility model.

[0125] The first layer 310 includes a first material composition, while the second layer 315 includes a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. For example, the first layer 310 may include silicon-germanium, while the second layer 315 may include silicon. In some embodiments, the first and second material compositions have different oxidation rates and / or etching selectivity.

[0126] As described herein, the second layer 315 can be fabricated to form nanostructure channels 220 for subsequent fabrication of nanostructure transistors in the semiconductor device 200. The first layer 310 is a sacrificial nanostructure and will eventually be removed to define the vertical distance between adjacent nanostructure channels 220 for subsequent fabrication of the gate structure 240 in the semiconductor device 200. In summary, the first layer 310 can be considered a sacrificial layer, and the second layer 315 can be considered a channel layer.

[0127] Deposition tool 102 deposits and / or grows interlaced layers of layered stack 305 to form nanostructures (such as nanosheets) on semiconductor substrate 205. For example, deposition tool 102 may epitaxially grow interlaced layers. However, other processes may be used to form interlaced layers of layered stack 305. Methods for epitaxially growing interlaced layers of layered stack 305 may include molecular beam epitaxy, metal-organic chemical vapor deposition, and / or another suitable epitaxial growth process. In some embodiments, the epitaxially grown layers, such as the second layer 315, may comprise the same material as the semiconductor substrate 205. In some embodiments, the first layer 310 and / or the second layer 315 comprise materials different from the semiconductor substrate 205. As described above, in some embodiments, the first layer 310 comprises an epitaxially grown silicon-germanium layer, while the second layer 315 comprises an epitaxially grown silicon layer. The first layer 310 and / or the second layer 315 may be replaced with other materials such as germanium, semiconductor compound materials (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, or gallium arsenide phosphide indium) and / or combinations thereof. The choice of materials for the first layer 310 and / or the second layer 315 may provide different oxidation properties, different etching selectivity, and / or other different properties.

[0128] like Figure 3A-1 and Figure 3A-2As shown, the deposition tool 102 may form one or more additional layers on the layered stack 305. For example, a hard mask layer 320 may be formed on the layered stack 305, such as on the topmost second layer 315 of the layered stack 305. In another example, a capping layer 325 may be formed on the hard mask layer 320. In yet another example, another hard mask layer containing an oxide layer 330 and a nitride layer 335 may be formed on the capping layer 325. One or more hard mask layers 320, capping layers 325, and oxide layers 330 may be used to form one or more structures of the semiconductor device 200. The oxide layer 330 may serve as an adhesion layer between the layered stack 305 and the nitride layer 335, and may also serve as an etch stop layer for etching the nitride layer 335. One or more hard mask layers 320, capping layers 325, and oxide layers 330 may include silicon germanium, silicon nitride, silicon oxide, and / or another material. The capping layer 325 may include silicon and / or another material. In some embodiments, the capping layer 325 and the semiconductor substrate 205 may be made of the same material. In some embodiments, one or more additional layers may be formed by thermal growth or deposition (such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or another deposition technique).

[0129] Figure 3B-1 A perspective view of the semiconductor device 200 is shown, while Figure 3B-2 Show a sectional view along section AA. For example... Figure 3B-1 and Figure 3B-2 As shown, the layered stack 305 and the semiconductor substrate 205 can be etched to remove portions of the layered stack 305 and the semiconductor substrate 205. The portions 340 and mesa regions 210 of the layered stack 305 remaining after the etching step (which can also be considered as silicon mesas or mesa portions) can be considered as fin structures 345 on the semiconductor substrate 205 of the semiconductor device 200. The fin structure 345 includes portions 340 of the layered stack 305 located on the mesa regions 210 within and / or above the semiconductor substrate 205. The fin structure 345 can be formed using any suitable semiconductor process technology. For example, the deposition tool 102, exposure tool 104, development tool 106, and / or etching tool 108 can be used with one or more photolithography processes to form the fin structure 345, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, resulting in a pattern pitch smaller than that obtained using a single direct photolithography process. For example, a sacrificial layer can be formed on a substrate and patterned using a photolithography process. A self-aligned process is then used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can later be used to pattern fin structures.

[0130] In some embodiments, a deposition tool 102 forms a photoresist layer on a hard mask layer containing an oxide layer 330 and a nitride layer 335. An exposure tool 104 exposes the photoresist layer with radiation (such as deep ultraviolet or extreme ultraviolet light), performs a post-exposure baking process (to remove residual solvent from the photoresist layer), and a developing tool 106 develops the photoresist layer to form mask units (or patterns) in the photoresist layer. In some embodiments, the method of patterning the photoresist layer to form mask units can be an electron beam lithography process. The mask units can then be used to protect portions of the semiconductor substrate 205 and the layered stack 305 during the etching step, keeping portions of the semiconductor substrate 205 and the layered stack 305 unetched to form the fin structure 345. The unprotected portions of the substrate and the unprotected portions of the layered stack 305 can be etched (e.g., by an etching tool 108) to form trenches in the semiconductor substrate 205. The etching tool may employ dry etching techniques (such as reactive ion etching), wet etching techniques, and / or combinations thereof to etch the unprotected portions of the substrate and the unprotected portions of the layered stack 305.

[0131] In some embodiments, another fin-forming technique may be used to form the fin structure 345. For example, a fin region may be defined (e.g., defined by a mask or isolation region), and a growth portion 340 may be extended outward in the form of the fin structure 345. In some embodiments, the method of forming the fin structure 345 includes a trimming process to reduce the width of the fin structure 345. The trimming process may include a wet etching process, a dry etching process, and / or other processes.

[0132] like Figure 3B-1 and 3B-2 As shown, fin structures 345 can be formed for different types of nanostructure transistors used in the semiconductor device 200. Specifically, a first set of fin structures 345a can be formed for p-type nanostructure transistors (such as p-type metal-oxide-semiconductor nanostructure transistors), and a second set of fin structures 345b can be formed for n-type nanostructure transistors (such as n-type metal-oxide-semiconductor nanostructure transistors). The second set of fin structures 345b can be doped with p-type dopants (such as boron, germanium, and / or other dopants), while the first set of fin structures 345a can be doped with n-type dopants (such as phosphorus, arsenic, and / or other dopants). Subsequently, p-type source / drain regions can be additionally or alternatively formed for p-type nanostructure transistors containing the first set of fin structures 345a, and subsequently, n-type source / drain regions can be formed for n-type nanostructure transistors containing the second set of fin structures 345b.

[0133] The first set of fin structures 345a (such as a p-type metal-oxide-semiconductor fin structure) and the second set of fin structures 345b (such as an n-type metal-oxide-semiconductor fin structure) may have similar and / or different characteristics. For example, the first set of fin structures 345a may have a first height, while the second set of fin structures 345b may have a second height, wherein the first height and the second height are different. In another example, the first set of fin structures 345a may have a first width, while the second set of fin structures 345b may have a second width, wherein the first width and the second width are different. Figure 3B-1 and 3B-2 In the example shown, the second width of the second set of fin structures 345b (e.g., for an n-type metal-oxide-semiconductor nanostructure transistor) is greater than the first width of the first set of fin structures 345a (e.g., for a p-type metal-oxide-semiconductor nanostructure transistor). However, other examples also fall within the scope of this embodiment.

[0134] As mentioned above, providing Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 As an example, other examples may differ from the collocation. Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 Examples of implementation methods 300 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 (The steps are explained).

[0135] Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 As an example, this describes an embodiment 400 of the shallow trench isolation formation process. The embodiment 400 includes forming shallow trench isolation regions 215 between fin structures 345 for use in a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include... Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 One or more additional devices, structures, and / or layers not shown. Semiconductor device 200 may include additional layers and / or dies formed on... Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2Above and / or below a portion of the semiconductor device 200 shown. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed in the same layer of the electronic device containing the semiconductor device 200. In some embodiments, it may be combined with... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 Following the steps described, the relevant steps will be explained using an example of implementation method 400.

[0136] Figure 4A-1 A perspective view of the semiconductor device 200 is shown, while Figure 4A-2 Show a sectional view along section AA. For example... Figure 4A-1 and Figure 4A-2 As shown, pad 405 and dielectric layer 410 are formed on semiconductor substrate 205 and inserted into fin structures 345 (e.g., formed between fin structures 345). Deposition tool 102 can deposit pad 405 and dielectric layer 410 on semiconductor substrate 205 and in trenches between fin structures 345. Deposition tool 102 can form dielectric layer 410 such that the height of the upper surface of dielectric layer 410 is approximately the same as the height of the upper surface of nitride layer 335.

[0137] The deposition tool 102 can be modified to form a dielectric layer 410, such that the height of the dielectric layer 410 is greater than the height of the upper surface of the nitride layer 335, for example... Figure 4A-1 and Figure 4A-2 As shown. In this method, the dielectric layer 410 can be overfilled in the trenches between the fin structures 345 to ensure that the trenches are completely filled with the dielectric layer 410. A planarization or polishing step (such as a chemical mechanical polishing step) can be performed after the planarization tool 110 to planarize the dielectric layer 410. In this step, the nitride layer 335 of the hard mask layer can serve as a chemical mechanical polishing stop layer. In other words, the planarization tool 110 can planarize the dielectric layer 410 until the nitride layer 335 of the hard mask layer is exposed. In summary, the height of the upper surface of the dielectric layer 410 after this step can be approximately the same as the height of the upper surface of the nitride layer 335.

[0138] The deposition tool 102 may deposit the pad 405 using compliant deposition techniques. The deposition tool 102 may deposit the dielectric layer using chemical vapor deposition techniques (such as flowable chemical vapor deposition or another chemical vapor deposition technique), physical vapor deposition techniques, atomic layer deposition techniques, and / or another deposition technique. In some embodiments, the semiconductor device 200 may be annealed after depositing the pad 405 to improve the quality of the pad 405.

[0139] The pad 405 and the dielectric layer 410 may each comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric material, and / or another suitable insulating material. In some embodiments, the dielectric layer 410 may comprise a multilayer structure, such as having one or more pad layers.

[0140] Figure 4B-1 A perspective view of the semiconductor device 200 is shown, while Figure 4B-2 A sectional view along section AA. (e.g.) Figure 4B-1 and Figure 4B-2 As shown, a back etch step can be performed to remove portions of the pad 405 and the dielectric layer 410 to form a shallow trench isolation region 215. An etching tool 108 can etch the pad 405 and the dielectric layer 410 in the back etch step to form the shallow trench isolation region 215. The etching tool 108 can etch the pad 405 and the dielectric layer 410 against a hard mask layer (such as a hard mask layer containing an oxide layer 330 and a nitride layer 335). The etching tool 108 etches the pad 405 and the dielectric layer 410 such that the height of the shallow trench isolation region 215 is less than or approximately equal to the bottom height of the portion 340 of the layered stack 305. In summary, the portion 340 of the layered stack 305 extends above the shallow trench isolation region 215. In some embodiments, the pad 405 and the dielectric layer 410 are etched such that the height of the shallow trench isolation region 215 is less than the height of the upper surface of the mesa region 210.

[0141] In some embodiments, the etching tool 108 employs a dry etching technique to etch the pad 405 and the dielectric layer 410. Ammonia, hydrofluoric acid, and / or another etchant may be used. Plasma-based dry etching techniques can cause a reaction between the etchant and the materials of the pad 405 and the dielectric layer 410, including:

[0142] SiO2 + 4HF → SiF4 + 2H2O

[0143] The silicon oxide of the gasket 405 and dielectric layer 410 reacts with hydrofluoric acid to form a byproduct containing silicon tetrafluoride and water. Hydrofluoric acid and ammonia further decompose the silicon tetrafluoride to form ammonium fluorosilicate byproduct.

[0144] SiF4 + 2HF + 2NH3 → (NH4)2SiF6

[0145] Ammonium fluorosilicate byproducts can be removed from the process chamber of the self-etching tool 108. After the removal of ammonium fluorosilicate, it can be sublimated into silicon tetrafluoride, ammonia, and hydrofluoric acid at a post-processing temperature of approximately 100°C to approximately 250°C.

[0146] In some embodiments, the etching tool 108 etches the pad 405 and the dielectric layer 410 such that the height of the shallow trench isolation region 215 between the first set of fins 345a (e.g., for p-type metal-oxide-semiconductor nanostructure transistors) is greater than the height of the shallow trench isolation region 215 between the second set of fins 345b (e.g., for n-type metal-oxide-semiconductor nanostructure transistors). The main reason is that the width of the second set of fins 345b is greater than the width of the first set of fins 345a. Furthermore, this causes the upper surface of the shallow trench isolation region 215 between the first set of fins 345a and the second set of fins 345b to be inclined (e.g., inclined downwards from the first set of fins 345a to the second set of fins 345b, as shown). Figure 4B-1 and Figure 4B-2 (Example shown). The van der Waals force between the etchant and the surfaces of the pad 405 and dielectric layer 410 can first physically adsorb the etchant used to etch the pad 405 and dielectric layer 410, for example, the etchant physically bonds to the pad 405 and dielectric layer 410. The dipole moment force can capture the etchant. The etchant then adheres to the dangling bonds of the pad 405 and dielectric layer 410 and begins chemisorption. The chemisorption of the etchant on the surfaces of the pad 405 and dielectric layer 410 causes the etching of the pad 405 and dielectric layer 410. The larger trench width between the second set of fin structures 345b allows for a larger surface area for chemisorption, resulting in a higher etching rate between the second set of fin structures 345b. The higher etching rate results in a shallow trench isolation region 215 between the second set of fin structures 345b having a smaller height than the shallow trench isolation region 215 between the first set of fin structures 345a.

[0147] As mentioned above, providing Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 As an example, other examples may differ from the collocation. Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 Examples of implementation methods 400 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 (The steps are explained).

[0148] Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 and Figure 5C-2As an example, this describes an embodiment 500 of the covered sidewall process. The embodiment 500 includes forming covered sidewalls on the sides of a portion 340 of a layered stack 305 for use with a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include... Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 and Figure 5C-2 One or more additional devices, structures, and / or layers not shown. Semiconductor device 200 may include additional layers and / or dies formed on... Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 and Figure 5C-2 Above and / or below a portion of the semiconductor device 200 shown. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed in the same layer of the electronic device containing the semiconductor device 200. In some embodiments, it may be combined with... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 and Figure 3B-2 and Figure 4A-1 , Figure 4A-2 , Figure 4B-1 and Figure 4B-2 Following the steps described, the relevant steps will be explained using an example of implementation method 500.

[0149] Figure 5A-1 A perspective view of the semiconductor device 200 is shown, while Figure 5A-2 Show a sectional view along section AA. For example... Figure 5A-1 and Figure 5A-2 As shown, a cladding layer 505 is formed over the fin structure 345 (such as over the upper surface and sidewalls of the fin structure 345) and over the shallow trench isolation region 215 between the fin structures 345. The cladding layer 505 comprises silicon germanium or another material. The constituent material of the cladding layer 505 may be the same as that of the first layer 310, allowing the same etching steps (such as a nanostructure release process) to remove the covering sidewalls (to be formed by the cladding layer 505) and the first layer 310, while a replacement gate (such as gate structure 240) may be formed in the area originally occupied by the covering sidewalls and the first layer 310. This allows the replacement gate to completely surround the nanostructure channels of the nanostructure transistors of the semiconductor device 200.

[0150] Deposition tool 102 can deposit a capping layer 505. In some embodiments, deposition tool 102 deposits a seed layer (such as a silicon seed layer or another seed layer) on the fin structure 345 (such as on the upper surface and sidewalls of the fin structure 345) and on the shallow trench isolation region 215 between the fin structures 345. Deposition tool 102 can then deposit silicon germanium on the seed layer to form the capping layer 505. The seed layer can promote the growth and adhesion of the capping layer 505.

[0151] The step of depositing the seed layer may include providing the silicon precursor to the process chamber of the deposition tool 102 using a carrier gas such as nitrogen, hydrogen, or other gases. Some embodiments include a pre-cleaning step before depositing the seed layer to reduce the formation of germanium oxide. The silicon precursor may include silane or another silicon precursor. Using silane is advantageous for forming a seed layer with a thickness of approximately 0.5 nm to approximately 1.5 nm to provide sufficient coverage sidewall thickness and to achieve a controllable and consistent thickness of the cladding 505. However, other ranges and values ​​for the thickness of the seed layer are also within the scope of this embodiment.

[0152] The temperature for depositing the seed crystal layer can be approximately 45°C. C to approximately 50 C (or another range of temperatures), pressure can be approximately 30 Torr to approximately 100 Torr (or another range of pressures), time can be approximately 100 seconds to approximately 300 seconds (or another range of times), and / or other parameters.

[0153] The step of depositing silicon-germanium coating 505 may include forming a coating 505 containing an amorphous configuration to promote compliant deposition of the coating 505. The germanium content of the silicon-germanium may be approximately 15% to approximately 25%. However, other values ​​for the germanium content are also within the scope of this embodiment. The step of depositing coating 505 may include using a carrier gas such as nitrogen, hydrogen, or other gases to provide a silicon precursor (such as silane, silane, or other silicon precursor) and a germanium precursor (such as germanane or another germanium precursor) to the deposition chamber of the deposition tool 102. The temperature for depositing coating 505 may be approximately 50°C. C to approximately 55 C (or another range of temperatures) and / or pressure can be approximately 5 Torr to approximately 20 Torr (or another range of pressures).

[0154] Figure 5B-1 Show perspective, and Figure 5B-2 Show a sectional view along section AA. For example... Figure 5B-1 and 5B-2As shown, a back etch step is performed to etch the cladding 505 to form the cover sidewall 510. The etching tool 108 may employ a plasma-based dry etching technique or another etching technique to etch the cladding 505. The etching tool 108 may perform a back etch step to remove a portion of the cladding 505 from the top of the fin structure 345 and the top of the shallow trench isolation region 215. Removing the cladding 505 from the top of the shallow trench isolation region 215 between the fin structures 345 ensures that the cover sidewall 510 does not have feet located on the shallow trench isolation region 215 between the fin structures 345. This ensures that the cover sidewall 510 does not have feet located under the hybrid fin structure, which will be formed on the shallow trench isolation region 215 between the fin structures 345.

[0155] In some embodiments, the etching tool 108 uses a fluorine-based etchant to etch the coating 505. The fluorine-based etchant may include sulfur hexafluoride, fluorinated methane, and / or another fluorine-based etchant. Other reactants and / or carrier gases such as methane, hydrogen, argon, and / or helium may also be used in the etch-back step. In some embodiments, the plasma bias used in the etch-back step may be approximately 500 volts to approximately 2000 volts. However, other values ​​of plasma bias used are also within the scope of this embodiment. In some embodiments, the step of removing a portion of the coating 505 from the top of the shallow trench isolation region 215 includes performing highly directional (e.g., anisotropic) etching to selectively remove (e.g., selectively etch) the coating 505 on the top of the shallow trench isolation region 215 between the fin structures 345.

[0156] In some embodiments, the cover sidewall 510 includes asymmetrical features (e.g., different lengths, depths, and / or angles). Asymmetrical features can increase the depth of the gate structure 240 used in different types of nanotransistors (e.g., p-type or n-type nanotransistors) and reduce and / or minimize the pins of the cover sidewall 510 on the shallow trench isolation region 215 beneath the hybrid fin structure of the nanotransistor of the semiconductor device 200 (thus reducing and / or minimizing the pins of the gate structure 240 formed in the area originally occupied by the cover sidewall 510 after its removal). Reducing and / or minimizing the pins can further reduce electrical short-circuit and / or leakage current problems.

[0157] Figure 5C-1 A perspective view of the semiconductor device 200 is shown, while Figure 5C-2 Show a sectional view along section AA. For example... Figure 5C-1 and Figure 5C-2As shown, the hard mask layer containing oxide layer 330 and nitride layer 335, as well as capping layer 325, are removed to expose hard mask layer 320. In some embodiments, the removal of capping layer 325, oxide layer 330, and nitride layer 335 may employ an etching step (performed by etching tool 108), planarization technique (performed by planarization tool 110), and / or another semiconductor process technique.

[0158] As mentioned above, providing Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 and Figure 5C-2 As an example, other examples may differ from the collocation. Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 and Figure 5C-2 Examples of implementation methods 500 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 and Figure 5C-2 (The steps are explained).

[0159] Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 and Figure 6C-2 As an example, this describes an embodiment 600 of the hybrid fin structure formation process. The embodiment 600 includes forming a hybrid fin structure between fin structures 345 for use in a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include... Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 and Figure 6C-2 One or more additional devices, structures, and / or layers not shown. Semiconductor device 200 may include additional layers and / or dies formed on... Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 and Figure 6C-2 Above and / or below a portion of the semiconductor device 200 shown. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed in the same layer of the electronic device containing the semiconductor device 200. In some embodiments, it may be combined with... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 , Figure 3B-2 , Figure 4A-1 , Figure 4A-2 , Figure 4B-1 , Figure 4B-2 , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 and Figure 5C-2 Following the steps described, the relevant steps will be explained using an example of implementation method 600.

[0160] Figure 6A-1 A perspective view of the semiconductor device 200 is shown, while Figure 6A-2 Show a sectional view along section AA. For example... Figure 6A-1 and Figure 6A-2 As shown, a pad 605 and a dielectric layer 610 are formed on a shallow trench isolation region 215 sandwiched between fin structures 345 and on the fin structures 345. A deposition tool 102 can deposit the pad 605 and the dielectric layer 610. The deposition tool 102 can employ compliant deposition techniques to deposit the pad 605. The deposition tool 102 can use chemical vapor deposition techniques (such as flowable chemical vapor deposition or another chemical vapor deposition technique), physical vapor deposition techniques, atomic layer deposition techniques, and / or another deposition technique. In some embodiments, the semiconductor device 200 can be annealed after depositing the dielectric layer 610 to improve the quality of the dielectric layer 610.

[0161] The deposition tool 102 can be configured such that the height of the upper surface of the formed dielectric layer 610 is approximately the same as the height of the upper surface of the hard mask layer 320. Alternatively, the deposition tool 102 can be modified to make the height of the upper surface of the formed dielectric layer 610 greater than the height of the upper surface of the hard mask layer 320, such as... Figure 6A-1 and Figure 6A-2 The example shown illustrates this approach. In this manner, the dielectric layer 610 is overfilled with trenches between the fin structures 345 to ensure that the trenches are completely filled with the dielectric layer 610. A planarization or polishing step (such as a chemical mechanical polishing step) can be performed after the planarization tool 110 to planarize the dielectric layer 610.

[0162] The pad 605 and the dielectric layer 610 may each comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, fluorosilicate glass, a dielectric material with a low dielectric constant, and / or another suitable insulating material. In some embodiments, the dielectric layer 610 may comprise a multilayer structure, such as having one or more pad layers.

[0163] Figure 6B-1 A perspective view of the semiconductor device 200 is shown, while Figure 6B-2 Show a sectional view along section AA. For example... Figure 6B-1 and Figure 6B-2 As shown, an etch-back step is performed to remove a portion of dielectric layer 610. Etching tool 108 may etch dielectric layer 610 during the etch-back step to reduce the height of the upper surface of dielectric layer 610. Specifically, etching tool 108 etches dielectric layer 610 such that the height of the portion of dielectric layer 610 between fin structures 345 is less than the height of the upper surface of hard mask layer 320. In some embodiments, etching tool 108 etches dielectric layer 610 such that the height of the portion of dielectric layer 610 between fin structures 345 is approximately equal to the height of the upper surface of the topmost second layer 315 of portion 340.

[0164] Figure 6C-1 A perspective view of the semiconductor device 200 is shown, while Figure 6C-2 Show a sectional view along section AA. For example... Figure 6C-1 and Figure 6C-2 As shown, a high-dielectric-constant layer 615 is deposited on a portion of the dielectric layer 610 between the fin structures 345. The deposition tool 102 can deposit a high-dielectric-constant material such as hafnium oxide and / or another high-dielectric-constant dielectric material to form the high-dielectric-constant layer 615, and the formation method can employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or another deposition technique. The combination of the portion of the dielectric layer 610 between the fin structures 345 and the portion of the high-dielectric-constant layer 615 between the fin structures 345 can be considered as a hybrid fin structure 620 (or a dummy fin structure). In some embodiments, the planarization tool 110 can perform a planarization step to planarize the high-dielectric-constant layer 615 so that the height of the upper surface of the high-dielectric-constant layer 615 is approximately the same as the height of the hard mask layer 320.

[0165] Then as Figure 6C-1 and Figure 6C-2 As shown, the hard mask layer 320 is removed. Methods for removing the hard mask layer 320 may include using etching techniques (such as plasma etching, wet chemical etching, and / or another etching technique) or another removal technique.

[0166] As mentioned above, providing Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 and Figure 6C-2 As an example, other examples may differ from the collocation. Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 and Figure 6C-2 Examples of implementation methods 600 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 and Figure 6C-2 (The steps are explained).

[0167] Figure 7A , Figure 7B-1 , Figure 7B-2 and Figure 7B-3 As an example, this is an example of embodiment 700 of the dummy gate formation process described herein. The example of embodiment 700 includes forming a dummy gate structure for use in a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include... Figure 7A , Figure 7B-1 , Figure 7B-2 and Figure 7B-3 One or more additional devices, structures, and / or layers not shown. Semiconductor device 200 may include additional layers and / or dies formed on... Figure 7A , Figure 7B-1 , Figure 7B-2 and Figure 7B-3 Above and / or below a portion of the semiconductor device 200 shown. One or more additional semiconductor structures and / or semiconductor devices may be additionally or alternatively formed in the same layer of the electronic device containing the semiconductor device 200. In some embodiments, it may be combined with... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 , Figure 3B-2 , Figure 4A-1 , Figure 4A-2 , Figure 4B-1 , Figure 4B-2 , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 , Figure 5C-2 , Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 and Figure 6C-2 Following the steps described, the relevant steps will be explained using an example of implementation method 700.

[0168] Figure 7A A perspective view of the semiconductor device 200 is shown. (See figure) Figure 7AAs shown, a dummy gate structure 705 (which can also be viewed as a dummy gate stack or temporary gate structure) is formed on the fin structure 345 and the hybrid fin structure 620. The dummy gate structure 705 is a sacrificial structure that will be replaced by a replacement gate structure or replacement gate stack (such as gate structure 240) in subsequent process stages used in the semiconductor device 200. A portion of the fin structure 345 below the dummy gate structure 705 can be viewed as a channel region. The dummy gate structure 705 can also define the source / drain regions of the fin structure 345, such as the regions of the fin structure 345 on both sides of the channel region and adjacent to both sides of the channel region.

[0169] The dummy gate structure 705 may include a gate layer 710, a hard mask layer 715 on the gate layer 710, and spacer layers 720 on both sides of the gate layer 710 and the hard mask layer 715. The dummy gate structure 705 may be formed on the gate dielectric layer 725 between the topmost second layer 315 and the dummy gate structure 705, and between the hybrid fin structure 620 and the dummy gate structure 705. The gate layer 710 includes polysilicon or another material. The hard mask layer 715 includes one or more layers such as oxide layers (e.g., a pad oxide layer containing silicon dioxide or another material) and nitride layers formed on the oxide layers (e.g., a pad nitride layer containing silicon nitride such as trisilicon tetranitride or another material). The spacer layer 720 includes silicon carbide, nitrogen-free silicon carbide, or another suitable material. The gate dielectric layer 725 may include silicon oxide (such as silicon dioxide), silicon nitride (such as silicon tetranitride), a dielectric material with a high dielectric constant, and / or another suitable material.

[0170] The method for forming the layered structure 705 can employ various semiconductor process technologies such as deposition (e.g., by deposition tool 102), patterning (e.g., by exposure tool 104 and developing tool 106), etching (e.g., by etching tool 108), and / or other techniques. Examples may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, electron beam evaporation, photolithography, electron beam lithography, photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), dry etching (e.g., reactive ion etching), wet etching, and / or other techniques.

[0171] In some embodiments, a gate dielectric layer 725 is compliantly deposited on the semiconductor device 200, followed by selective removal of the gate dielectric layer 725 from portions of the semiconductor device 200 (e.g., source / drain regions). A gate layer 710 is then deposited on the retained portions of the gate dielectric layer 725. A hard mask layer 715 is then deposited on the gate layer 710. A spacer layer 720 can be compliantly deposited in a manner similar to that of the gate dielectric layer 725, and the spacer layer 720 can be etched back to retain the spacer layer 720 on the sidewalls of the dummy gate structure 705. In some embodiments, the spacer layer 720 includes multiple spacer layers. For example, the spacer layer 720 may include a sealing spacer layer formed on the sidewalls of the dummy gate structure 705, and a substrate spacer layer formed on the sealing spacer layer. The sealing spacer layer and the substrate spacer layer may be composed of similar or different materials. In some embodiments, the substrate spacer layer is formed without the plasma surface treatment used for the sealing spacer layer. In some embodiments, the thickness of the substrate spacer layer is greater than the thickness of the sealing spacer layer. In some embodiments, the gate dielectric layer 725 can be omitted from the dummy gate structure formation process and instead formed in the gate replacement process.

[0172] Figure 7A The reference cross-sections used in subsequent figures are further shown. Cross-section AA (which can be considered a y-section) in the xz plane crosses the fin structure 345 and the hybrid fin structure 620 in the source / drain region of the semiconductor device 200. Cross-section BB (which can be considered an x-section) in the yz plane is perpendicular to cross-section AA and crosses the dummy gate structure 705 in the source / drain region of the semiconductor device 200. Cross-section CC in the xz plane is parallel to cross-section AA and perpendicular to cross-section BB, and runs along the dummy gate structure 705. Subsequent figures will be based on these reference cross-sections for clarity. In some figures, identical reference numerals for shown components or structures may be omitted to avoid obscuring other components or structures, thus improving clarity.

[0173] Figure 7B-1 , Figure 7B-2 and Figure 7B-3 Each includes along Figure 7A The sectional views of sections AA, BB, and CC. For example... Figure 7B-2 and 7B-3 As shown in cross-sections BB and CC, the dummy gate structure 705 is formed on the fin structure 345. (As shown in the cross-sections BB and CC) Figure 7B-3 As shown in the cross-section CC, a portion of the gate dielectric layer 725 and a portion of the gate layer 710 are formed in a recess on the fin structure 345, and the recess is formed by removing the hard mask layer 320.

[0174] As mentioned above, providing Figure 7A , Figure 7B-1 , Figure 7B-2 and Figure 7B-3 As an example, other examples may differ from the collocation. Figure 7A , Figure 7B-1 , Figure 7B-2 and Figure 7B-3 Examples of implementation methods 700 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 7A , Figure 7B-1 , Figure 7B-2 and Figure 7B-3 (The steps are explained).

[0175] Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 and Figure 8D-3 As an example, this describes an embodiment 800 of the source / drain recess formation process and the inner spacer formation process. The embodiment 800 includes an example of forming source / drain recesses and inner spacers 245 for use in a semiconductor device 200. Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 and Figure 8D-3 like Figure 7A As shown in the perspective view, they respectively include Figure 7A The sectional view of section AA in the middle. Figure 7A The sectional view of section BB in the middle, and Figure 7A A cross-sectional view of section CC. In some embodiments, it can be combined with... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 , Figure 3B-2 , Figure 4A-1 , Figure 4A-2 , Figure 4B-1 , Figure 4B-2 , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 , Figure 5C-2 , Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 , Figure 6C-2 , Figure 7A , Figure 7B-1 , Figure 7B-2 and Figure 7B-3 Following the steps described, the relevant steps will be explained using an example of implementation method 800.

[0176] like Figure 8A-1 and Figure 8A-2 As shown in cross-sections AA and BB, a source / drain recess 805 is formed in portion 340 of the fin structure 345 during the etching step. The source / drain recess 805 is formed to provide space on both sides of the dummy gate structure 705 after the source / drain region 225 is formed. The etching tool 108 can perform the etching step, which can be considered as a strained source / drain etching step. In some embodiments, the etching step includes plasma etching, wet chemical etching, and / or another etching technique.

[0177] The source / drain recess 805 also extends into a portion of the mesa region 210 of the fin structure 345. This can form multiple mesa regions 210 in each fin structure 345, with the sidewalls of the portion of the source / drain recess 805 below the portion 340 corresponding to the sidewalls of the mesa region 210. The source / drain recess 805 can penetrate wells (such as p-type or n-type wells) of the fin structure 345. In embodiments where the semiconductor substrate 205 includes a (100) oriented silicon material, a (111) crystal plane can be formed at the bottom of the source / drain recess 805, resulting in a V-shaped or triangular bottom profile of the source / drain recess 805. In some embodiments, wet etching using tetramethylammonium hydroxide and / or chemical dry etching using hydrogen chloride can be used to form the V-shaped profile. However, the bottom profile of the source / drain recess 805 can include other shapes, such as circular, semi-circular, or other shapes.

[0178] like Figure 8A-2 and Figure 8A-3 As shown in cross-sections BB and CC, after the etching step that forms the source / drain recess 805, portions of the first layer 310 and the second layer 315 of the layered stack 305 can be retained beneath the dummy gate structure 705. The portion of the second layer 315 beneath the dummy gate structure 705 can form the nanostructure channel 220 of the nanostructure transistor of the semiconductor device 200. The nanostructure channel 220 extends between adjacent source / drain recesses 805 and adjacent hybrid fin structures 620.

[0179] like Figure 8B-2As shown in section BB, the first layer 310 can be etched laterally during the etching step (e.g., in a direction approximately parallel to the length of the first layer 310) to form voids 810 between portions of the nanostructure channel 220. Specifically, the etching tool 108 can laterally etch the ends of the first layer 310 beneath the dummy gate structure 705 via the source / drain recess 805 to form voids 810 between the ends of the nanostructure channel 220. In embodiments where the first layer 310 is silicon-germanium and the second layer 315 is silicon, the etching tool 108 can selectively etch the first layer 310 using a wet etchant such as a mixed solution containing hydrogen peroxide, acetic acid, and / or hydrofluoric acid, followed by cleaning with water. The mixed solution and water can be provided to the source / drain recess 805 to etch the first layer 310 from the source / drain recess 805. In some embodiments, the steps of etching with the mixed solution and cleaning with water can be repeated approximately 10 to approximately 20 times. In some embodiments, the etching time of the mixed solution can be from about 1 minute to about 2 minutes. The operating temperature of the mixed solution can be from approximately 60°C to approximately 90°C. However, other values ​​used for the parameters of the etching step are also within the scope of this embodiment.

[0180] The void 810 can be formed in an approximately arcuate, approximately concave, approximately triangular, approximately square, or other shape. In some embodiments, the depth of one or more voids 810 (e.g., the dimension of the void extending from the source / drain recess 805 into the first layer 310) can be approximately 0.5 nm to approximately 5 nm. In some embodiments, the depth of one or more voids 810 can be approximately 1 nm to approximately 3 nm. However, other values ​​used for the depth of the void 810 are also within the scope of this embodiment. In some embodiments, the length of the void 810 formed by the etching tool 108 (e.g., the dimension of the void extending from the nanostructure channel 220 under the first layer 310 to another nanostructure channel 220 on the first layer 310) can allow the void 810 to partially extend into the side of the nanostructure channel 220 (e.g., the width or length of the void 810 is greater than the thickness of the first layer 310). In this manner, the inner spacers subsequently formed in the void 810 can extend into the end portion of the nanostructure channel 220. In some implementations, the formation of void 810 causes thinning of the cover sidewall 510 in the source / drain recess 805.

[0181] like Figure 8C-1 and Figure 8C-2As shown in cross-sections AA and BB, an insulating layer 815 can be compliantly deposited along the sidewalls and bottom of the source / drain recess 805. The insulating layer 815 may further extend along the spacer layer 720. The deposition tool 102 may employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or another deposition technique to deposit the insulating layer 815. The insulating layer 815 comprises silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, and / or another dielectric material. The material comprising the insulating layer 815 may differ from the material of the spacer layer 720.

[0182] The thickness of the insulating layer 815 formed by the deposition tool 102 is sufficient to fill the voids 810 between the nanostructure channels 220. For example, the thickness of the insulating layer 815 can be approximately 1 nm to approximately 10 nm. In another example, the thickness of the insulating layer 815 can be approximately 2 nm to approximately 5 nm. However, other values ​​used for the thickness of the insulating layer 815 are also within the scope of this embodiment.

[0183] like Figure 8D-1 and Figure 8D-2 As shown in cross-sections AA and BB, the insulating layer 815 can be partially removed, so that the remaining portion of the insulating layer 815 corresponds to the inner spacer 245 in the cavity 810. An etching tool 108 can perform an etching step to partially remove the insulating layer 815. (As shown in the cross-sections AA and BB, the insulating layer 815 can be partially removed.) Figure 8D-1 As shown in section AA, the covering sidewall 510 can also be removed from the source / drain recess 805 during the etching step to partially remove the insulating layer 815.

[0184] In some embodiments, the etching step may cause the surface of the inner spacer 245 facing the source / drain recess 805 to be arc-shaped or recessed. The recess depth in the inner spacer 245 may be approximately 0.2 nm to approximately 3 nm. In another example, the recess depth in the inner spacer 245 may be approximately 0.5 nm to approximately 2 nm. In yet another example, the recess depth in the inner spacer 245 may be less than approximately 0.5 nm. In some embodiments, the surface of the inner spacer 245 facing the source / drain recess 805 is approximately flat, such that the surface of the inner spacer 245 is approximately flush with the end surface of the nanostructure channel 220.

[0185] As mentioned above, providing Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 and Figure 8D-3 As an example, other examples may differ from the collocation. Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 and Figure 8D-3 Examples of implementation methods 800 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 and Figure 8D-3 (The steps are explained).

[0186] Figure 9-1 , Figure 9-2 , Figure 9-3 As an example, this describes an embodiment 900 of the source / drain region formation process. The embodiment 900 includes forming source / drain regions 225 in a source / drain recess 805 for use in a semiconductor device 200. Figure 9-1 , Figure 9-2 and Figure 9-3 like Figure 7A As shown in the perspective view, including Figure 7A The sectional view of section AA in the middle. Figure 7A The sectional view of section BB in the middle, and Figure 7A A cross-sectional view of section CC. In some embodiments, it can be combined with... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 , Figure 3B-2 , Figure 4A-1 , Figure 4A-2 , Figure 4B-1 , Figure 4B-2 , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 and Figure 5C-2 , Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 , Figure 6C-2 , Figure 7A , Figure 7B-1 , Figure 7B-2 , Figure 7B-3 , Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 and Figure 8D-3 Following the steps described, the relevant steps will be explained using an example of implementation method 900.

[0187] like Figure 9-1 and Figure 9-2 As shown in cross-sections AA and BB, one or more layers are filled into the source / drain recess 805 to form a source / drain region 225 within the source / drain recess 805. For example, deposition tool 102 may deposit a buffer layer 230 at the bottom of the source / drain recess 805, deposit the source / drain region 225 on the buffer layer 230, and deposit a capping layer 235 on the source / drain region 225. The buffer layer 230 may include silicon, boron-doped silicon, or another doped silicon and / or another material. The buffer layer 230 may reduce, minimize, and / or prevent the migration of dopants and / or leakage current from the source / drain region 225 to the adjacent mesa region 210, which could otherwise cause short-channel effects in the semiconductor device 200. In summary, the buffer layer 230 may increase the performance and / or yield of the semiconductor device 200.

[0188] The source / drain region 225 may include one or more layers of epitaxially grown material. For example, the deposition tool 102 may epitaxially grow a first layer (represented as L1) of the source / drain region 225 on the buffer 230, and may epitaxially grow a second layer (represented as L2, L2-1, and / or L2-2) of the source / drain region 225 on the first layer. The first layer may include lightly doped (e.g., doped with boron, phosphorus, and / or other dopants) silicon and may serve as a mask layer to reduce short-channel effects in the semiconductor device 200 and reduce dopant intrusion or migration into the nanostructure channel 220. The second layer may include heavily doped silicon or highly doped silicon-germanium. The second layer may provide compressive stress to the source / drain region 225 to reduce boron loss.

[0189] As mentioned above, providing Figure 9-1 , Figure 9-2 and Figure 9-3 As an example, other examples may differ from the collocation. Figure 9-1 , Figure 9-2 and Figure 9-3Examples of implementation 900 may include additional steps, fewer steps, different steps, and / or steps in a different order (compared to the combination). Figure 9-1 , Figure 9-2 and Figure 9-3 (The steps are explained).

[0190] Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , Figure 10C-2 , Figure 10C-3 , Figure 10D , Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 , Figure 10G-3 and Figure 10H As an example, this describes an embodiment 1000 of the interface layer formation process. The embodiment 1000 includes examples of the formation process of the interface layer 1010a and the high dielectric constant layer 1010b of the semiconductor device 200. Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , Figure 10C-2 , Figure 10C-3 , Figure 10D , Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 , Figure 10G-3 and Figure 10H like Figure 7A As shown in the perspective view, including Figure 7A The sectional view of section AA in the middle. Figure 7A The sectional view of section BB in the middle, and Figure 7A A cross-sectional view of section CC. In some embodiments, it can be combined with... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 , Figure 3B-2 , Figure 4A-1 , Figure 4A-2 , Figure 4B-1 , Figure 4B-2 , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 , Figure 5C-2 , Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 , Figure 6C-2 , Figure 7A , Figure 7B-1 , Figure 7B-2 , Figure 7B-3 , Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 , Figure 8D-3 , Figure 9-1 , Figure 9-2 and Figure 9-3 Following the steps described, the relevant steps will be explained using an example of implementation method 1000.

[0191] like Figure 10A-1 and Figure 10A-2 As shown in cross-sections AA and BB, dielectric layer 250 is formed on the source / drain region 225. Dielectric layer 250 fills the areas between the dummy gate structures 705, between the hybrid fin structures 620, and above the source / drain region 225. During the interface layer formation process, dielectric layer 250 can reduce and / or avoid damage to the source / drain region 225. Dielectric layer 250 can be considered as a zeroth interlayer dielectric layer or another interlayer dielectric layer.

[0192] In some embodiments, prior to the formation of dielectric layer 250, a contact etch stop layer is conformally deposited (e.g., using deposition tool 102) on source / drain regions 225, dummy gate structure 705, and spacer layer 720. Dielectric layer 250 is then formed on the contact etch stop layer. The contact etch stop layer provides a mechanism to stop the etch process when forming the contacts or vias used in the source / drain regions 225. The contact etch stop layer may be composed of a dielectric material with an etch selectivity different from that of adjacent layers or components. The contact etch stop layer may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the contact etch stop layer may include or may be silicon nitride, silicon carbonitride, carbon nitride, silicon oxynitride, silicon oxycarbide, combinations thereof, or other materials. The deposition method for the contact etch stop layer may employ deposition techniques such as atomic layer deposition, chemical vapor deposition, or another deposition technique.

[0193] like Figure 10B-2 and Figure 10B-3As shown in cross-sections BB and CC, the dummy gate structure 705 is removed from the semiconductor device 200 by one or more semiconductor process tools, such as deposition tool 102 to plating tool 112. Removing the dummy gate structure 705 leaves an opening 1005 (or a recess) between the dielectric layer 250 on the source / drain regions 225 and between the hybrid fin structures 620. The dummy gate structure 705 can be removed by one or more etching steps. This etching step may include plasma etching, wet chemical etching, and / or another etching technique.

[0194] like Figure 10C-2 and Figure 10C-3 As shown in cross-sections BB and CC, a nanostructure release step (such as a silicon-germanium release step) is performed to remove the first layer 310 (such as a silicon-germanium layer). This will form openings 1005 between the nanostructure channels 220 (such as the region surrounding the nanostructure channels 220). The nanostructure release step may include an etching step performed with an etching tool 108, which removes the first layer 310 based on the difference in etch selectivity between the material of the first layer 310 and the material of the nanostructure channels 220 (and the difference in etch selectivity between the material of the first layer 310 and the material of the inner spacer 245). The inner spacer 245 may serve as an etch stop layer in the etching step to protect the source / drain regions 225 from etching. Figure 10C-1 , Figure 10C-2 and Figure 10C-3 As shown, the nanostructure release step removes the covering sidewall 510. This exposes the area around the nanostructure channel 220, allowing the interface layer 1010a and the high dielectric constant layer 1010b to be formed all around the nanostructure channel 220.

[0195] like Figure 10D As shown in cross-section BB, interface layer 1010a is formed on nanostructure channel 220, inner spacer 245, and spacer layer 720. Furthermore, interface layer 1010a may be additionally deposited on dielectric layer 250. In embodiments where capping layer 235 extends around the sidewalls of dielectric layer 250, interface layer 1010a may be additionally deposited on capping layer 235. In other words, because the method of forming interface layer 1010a employs anti-selective deposition, interface layer 1010a can be formed on all exposed surfaces of semiconductor device 200 after removing dummy gate structure 705 and first layer 310. The method of forming interface layer 1010a is as follows... Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 and Figure 10G-3 The following is an explanation.

[0196] like Figure 10E-1 , Figure 10E-2 and Figure 10E-3 As shown, the starting process used to form amorphous silicon 1015a and crystalline silicon 1015b is the same as that used to form interface layer 1010a. Figure 10E-1 , Figure 10E-2 and 10E-3 Regions 200A, 200B, and 200C in section BB are shown respectively. Specifically, amorphous silicon 1015a can be formed on the spacer layer 720 and the inner spacer 245, while crystalline silicon 1015b can be formed on the nanostructure channel 220. Different chemical reactions, such as... Figure 10F-1 and Figure 10F-2 The described method allows for the formation of amorphous silicon 1015a on the spacer layer 720 and the inner spacer 245, while crystalline silicon 1015b is formed on the nanostructure channel 220. The thickness of the amorphous silicon 1015a can be approximately 4.0 Å to approximately 6.0 Å. Choosing a thickness of at least 4.0 Å allows the interface layer 1010a to have a thickness of at least 0.5 nm, while a thinner amorphous silicon interface layer may cause leakage current in the nanostructure channel 220 (to the inner spacer 245). Choosing a thickness of no more than 6.0 Å allows the interface layer 1010a to have a thickness of no more than 1.0 nm, while a thicker amorphous silicon layer may reduce the volume of the gate structure 240, thus reducing the efficiency of the gate structure 240. The thickness of the crystalline silicon 1015b can similarly be approximately 4.0 Å to approximately 6.0 Å. In this way, the interface layer 1010a has a more consistent thickness (for example, within an error range of less than or equal to 5.0 Å).

[0197] The chemical reaction that forms amorphous silicon 1015a and crystalline silicon 1015b is as follows: Figure 10F-1 and Figure 10F-2 As shown. First, before forming amorphous silicon 1015a and crystalline silicon 1015b, the nanostructure channel 220 can be cleaned using a chemical oxide removal step (e.g., via one or more semiconductor process tools such as deposition tool 102 to plating tool 112). The chemical oxide removal step removes silicon oxide from the exposed surface of the nanostructure channel 220. In one example, hydrogen fluoride and ammonia can react with silicon oxide to form water and salts such as ammonium fluorosilicate, as shown in the following chemical reaction:

[0198] SiO2+4HF SiF4 + 2H2O, and

[0199] SiF4 + 2HF + 2NH3 (NH4)2SiF6.

[0200] Vaporizable salts (e.g., annealed via one or more semiconductor processing tools such as deposition tool 102 to plating tool 112) are reacted as shown in the following chemical reaction:

[0201] (NH4)2SiF6 SiF4 + 2HF + 2NH3.

[0202] In this way, silicon oxide can be removed from the exposed surface of the nanostructure channel 220. However, hydroxyl groups can remain on the surface of the inner spacer 245 and the spacer layer 720. A precursor can be delivered (e.g., by one or more semiconductor process tools such as deposition tool 102 to plating tool 112) to begin silicon growth on the nanostructure channel 220, the inner spacer 245, and the spacer layer 720. The precursor may have the following structure:

[0203] .

[0204] Silyl compounds (bonded to nitrogen in the precursor) can be deposited on the exposed surfaces of the nanostructured channel 220 and can be replaced by free hydrogen retained on the exposed surfaces (or by otherwise transporting the carrier gas and precursor). Similarly, silyl compounds can be deposited on the exposed surfaces of the inner spacers 245 and the spacer layer 720 and can be replaced by hydrogen from hydroxyl groups retained on the exposed surfaces. Thus, silyl compounds can be formed on the nanostructured channel 220, while the seed layer 1015a' (e.g., containing silanol groups) is formed on the inner spacers 245 and the spacer layer 720.

[0205] In the precursor structure, the groups R1, R2, R3, or R4 do not react with the silicon of the nanostructure channel 220 or the hydroxyl groups of the inner spacer 245 and spacer layer 720. For example, at least one R1, R2, R3, or R4 may include a methyl group. In fact, two or more R1, R2, R3, or R4 may include methyl groups. In one example, the precursor may include diisopropylaminosilane.

[0206] The temperature at which the precursor is introduced can be approximately 200°C to approximately 300°C. Choosing a temperature of at least 200°C allows the precursor to react with the nanostructured channel 220, the inner spacer 245, and the spacer layer 720. Temperatures that are too low may inhibit the formation of silanes on the nanostructured channel 220 and inhibit the formation of the seed layer 1015a' on the inner spacer 245 and the spacer layer 720. Choosing a temperature no higher than 300°C facilitates the reaction between the precursor and the hydroxyl groups of the inner spacer 245 and the spacer layer 720, thereby improving the adhesion of the seed layer 1015a'.

[0207] like Figure 10F-1 and Figure 10F-2As shown, silane and / or silane (e.g., delivered by one or more semiconductor process tools such as deposition tool 102 to plating tool 112) can be delivered to form amorphous silicon 1015a on the inner spacer 245 and spacer layer 720 to replace the seed layer 1015a'. Furthermore, silane and / or silane can be delivered to grow crystalline silicon 1015b on the nanostructure channel 220.

[0208] Semiconductor device 200 can be located in a chamber with a pressure of less than 3 Torr to deposit silicon. Choosing a pressure of less than 3 Torr reduces impurities in amorphous silicon 1015a and crystalline silicon 1015b, while too high a pressure may increase contamination in the chamber and inhibit the formation of amorphous silicon 1015a and crystalline silicon 1015b. The temperature at which silane and / or silane are delivered can be approximately 300°C to approximately 500°C. Choosing a temperature of at least 300°C allows silane and / or silane to react with the nanostructure channel 220, the inner spacer 245, and the spacer layer 720, while too low a temperature may inhibit silicon deposition. Choosing a temperature of no more than 500°C improves the thickness control of the deposited silicon, while too high a temperature may create an excessively thick interface layer, which may reduce the volume of the gate structure 240 and thus reduce the efficiency of the gate structure 240.

[0209] In some embodiments, the deposition time for forming amorphous silicon 1015a and crystalline silicon 1015b is proportional to the temperature of silane and / or silane. For example, the deposition time using silane at a temperature close to 500°C is approximately 15 minutes compared to using silane at a temperature close to 400°C. In another example, the deposition time using silane at a temperature close to 400°C is approximately 20 minutes compared to using silane at a temperature close to 300°C. The selection of deposition time and / or temperature can be achieved using a machine learning model. The machine learning model may include and / or may be related to one or more of the following: regression model, random forest model, cluster model, neural network, and / or other models. In some embodiments, the machine learning model accepts candidate temperatures and / or deposition times as input, and the machine learning model can determine the likelihood, probability, or confidence level of a specific output (such as the target thickness of amorphous silicon 1015a and crystalline silicon 1015b) that can be achieved using the candidate parameters. In some implementations, the machine learning model accepts a target thickness as input, and the machine learning model can identify or recognize a specific combination of temperature and / or deposition time to achieve the target thickness.

[0210] Machine learning models can be trained, updated, and / or optimized to increase the accuracy of the results and / or parameters validated by the machine learning model. For example, machine learning models can be trained, updated, and / or optimized based on feedback and / or results from subsequent silicon deposition steps and historical or related silicon deposition steps (e.g., from hundreds, thousands, or more historical or related silicon deposition steps).

[0211] Therefore, the thickness of each of the amorphous silicon 1015a and crystalline silicon 1015b can be approximately 4.0 Å to approximately 6.0 Å, as described above. The amorphous silicon 1015a and / or crystalline silicon 1015b can be made to a larger thickness (e.g., up to approximately 9.0 Å). Thus, a cycle of oxidation and finishing can be performed on the semiconductor device 200. In other words, a portion of the amorphous silicon 1015a and / or crystalline silicon 1015b can be oxidized (e.g., by applying oxygen and / or another oxygen-dominant molecule), followed by partial etching of the oxidized portion (e.g., using dry etching and / or wet etching). Since the thicker layers of amorphous silicon 1015a and crystalline silicon 1015b undergo more oxidation, the same thicker layers can be etched. In this way, the amorphous silicon 1015a and crystalline silicon 1015b ultimately have a more consistent thickness (e.g., within an error range of less than or equal to 3.0 Å).

[0212] like Figure 10G-1 , Figure 10G-2 and Figure 10G-3 As shown, an interface layer 1010a is formed from amorphous silicon 1015a and crystalline silicon 1015b. Section 10G shows regions 200A, 200B, and 200C in cross-section BB. Specifically, amorphous silicon 1015a and crystalline silicon 1015b are oxidized (e.g., by one or more semiconductor process tools such as deposition tool 102 to plating tool 112) to form the interface layer 1010a. The thickness of the interface layer 1010a can be approximately 0.5 nm to approximately 1.0 nm, as described above. Furthermore, the ratio of the thickness of the inner spacer 245 to the thickness of the interface layer 1010a can be approximately 4.0 to approximately 8.0. Choosing a thickness ratio of at least 4.0 ensures that the thickness of the inner spacer 245 is sufficient to isolate the gate structure 240 from the source / drain region 225, while an excessively small thickness ratio may increase the leakage current of the gate structure 240. Choosing a thickness ratio of no more than 8.0 ensures that the thickness of the interface layer 1010a is sufficient to isolate the gate structure 240 from the nanostructure channel 220, while an excessively large thickness ratio may increase the leakage current of the nanostructure channel 220. In one example, the thickness of the inner spacer 245 is approximately 3.5 nm to approximately 4.5 nm. Similarly, the ratio of the thickness of the spacer layer 720 to the thickness of the interface layer 1010a is approximately 4.0 to approximately 8.0. In one example, the thickness of the spacer layer 720 is approximately 3.5 nm to approximately 4.5 nm.

[0213] like Figure 10H As shown, the interface layer 1010a is located at the interface between the inner spacer 245 and the nanostructure channel 220. Figure 10H As shown, the barrier layer 1020 can inhibit electrons from tunneling from the nanostructure channel 220 to the inner spacer 245. For example, the barrier layer 1020 can be formed before the inner spacer 245 is formed, such as in combination with Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 and 8D-3 The description specifies that the barrier layer 1020 can be an oxygen-rich layer. Here, "oxygen-rich" refers to a chemical composition in which oxygen atoms outnumber nitrogen atoms (e.g., unlike nitrogen-rich layers such as the inner spacer 245). Figure 10H As shown, due to the non-selective formation of the interface layer 1010a, the interface layer 1010a contacts the inner spacer 245, the nanostructure channel 220, and the interface between the inner spacer 245 and the nanostructure channel 220 (e.g., Figure 10H (as shown in the corner). In this way, the interface layer 1010a reduces the leakage current from the nanostructure channel 220 to the inner spacer 245 at the corner. For example, the interface layer 1010a can increase the leakage current-related threshold voltage between the nanostructure channel 220 and the inner spacer 245. In this way, the semiconductor device 200 can operate at high voltages compared to a semiconductor device without an interface layer formed from a fresh silicon cap process.

[0214] The above steps (such as chemical oxide removal, formation of seed layer 1015a', formation of amorphous silicon 1015a and crystalline silicon 1015b, and oxidation) can be performed in situ. Furthermore, a high dielectric constant layer 1010b is formed on the interface layer 1010a. The high dielectric constant layer 1010b can also be formed in situ (or separately).

[0215] As mentioned above, providing Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , Figure 10C-2 , Figure 10C-3 , Figure 10D , Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 , Figure 10G-3 and Figure 10H The number and configuration of the apparatus and steps shown are one or more examples. In practice, additional steps and apparatus, fewer steps and apparatus, different steps and apparatus, or different configurations of steps and apparatus may be used (compared to the combination). Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , 10B-3 , Figure 10C-1 , Figure 10C-2, Figure 10C-3 , Figure 10D , Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 , Figure 10G-3 and Figure 10H (Description of steps and apparatus).

[0216] Figure 11-1 , Figure 11-2 and Figure 11-3 The accompanying drawing illustrates an embodiment 1100 of the gate displacement process as an example. Examples of embodiment 1100 include examples of gate displacement processes used to form the gate structure 240 (such as a gate displacement structure) of a semiconductor device 200. Figure 11-1 , Figure 11-2 and Figure 11-3 like Figure 7A As shown in the perspective view, they respectively include Figure 7A The sectional view of section AA in the middle. Figure 7A The sectional view of section BB in the middle, and Figure 7A A cross-sectional view of section CC. In some embodiments, it can be combined with... Figure 3A-1 , Figure 3A-2 , Figure 3B-1 , Figure 3B-2 , Figure 4A-1 , Figure 4A-2 , Figure 4B-1 , Figure 4B-2 , Figure 5A-1 , Figure 5A-2 , Figure 5B-1 , Figure 5B-2 , Figure 5C-1 , Figure 5C-2 , Figure 6A-1 , Figure 6A-2 , Figure 6B-1 , Figure 6B-2 , Figure 6C-1 , Figure 6C-2 , Figure 7A , Figure 7B-1 , Figure 7B-2 , Figure 7B-3 , Figure 8A-1 , Figure 8A-2 , Figure 8A-3 , Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , Figure 8C-1 , Figure 8C-2 , Figure 8C-3 , Figure 8D-1 , Figure 8D-2 , Figure 8D-3 , Figure 9-1 , Figure 9-2 , Figure 9-3 , Figure 10A-1 , Figure 10A-2 , Figure 10A-3 , Figure 10B-1 , Figure 10B-2 , Figure 10B-3 , Figure 10C-1 , Figure 10C-2 , Figure 10C-3 , Figure 10D , Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 , Figure 10G-3 and Figure 10H Following the steps described, the relevant steps will be explained using an example of implementation method 1100.

[0217] like Figure 11-2 and Figure 11-3 As shown in cross-sections BB and CC, a continuous gate displacement step is performed, wherein the deposition tool 102 and / or plating tool 112 can form a gate structure 240 (such as a displacement gate structure) between the opening 1005 between the source / drain regions 225 and the hybrid fin structure 620. Specifically, the gate structure 240 fills the area between and around the nanostructure channels 220 (previously occupied by the first layer 310 and the covering sidewalls 510), thus the gate structure 240 completely covers and surrounds the nanostructure channels 220. The gate structure 240 may include a metal gate structure. (The last sentence appears to be incomplete and possibly contains errors.) Figure 10D , Figure 10E-1 , Figure 10E-2 , Figure 10E-3 , Figure 10F-1 , Figure 10F-2 , Figure 10G-1 , Figure 10G-2 , Figure 10G-3 and 10H The barrier layer 1010, comprising the interface layer 1010a and the high dielectric constant layer 1010b, can be formed between the nanostructure channel 220 and the gate structure 240. The gate structure 240 may include additional layers such as a work function adjustment layer, a metal electrode structure, and / or other layers.

[0218] As mentioned above, providing Figure 11-1 , Figure 11-2 and Figure 11-3 The number and configuration of structures and steps shown are one or more examples. In practice, additional steps and structures, fewer steps and structures, different steps and structures, or different configurations of steps and structures (compared to combinations) can be used. Figure 11-1 , Figure 11-2 and Figure 11-3 (The steps and structure explained).

[0219] Figure 12 The accompanying drawing illustrates, for example, the components of the apparatus 1200 described herein. In some embodiments, one or more semiconductor process tools, such as deposition tools 102 to plating tools 112 and / or wafer / die transfer tools 114, may include one or more apparatuses 1200 and / or one or more components of apparatus 1200. Figure 12 As shown, the device 1200 may include a bus 1210, a processor 1220, a memory 1230, an input component 1240, an output component 1250, and / or a communication component 1260.

[0220] Bus 1210 includes one or more components that enable wired and / or wireless communication of components of device 1200. Bus 1210 enables... Figure 12 Two or more components are coupled together, for example via operative coupling, communicative coupling, electronic coupling, and / or electrical coupling. Processor 1220 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, special-purpose integrated circuit, and / or another processing component. Processor 1220 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1220 may include one or more processors that can be programmed to perform one or more steps or processes described elsewhere.

[0221] Memory 1230 may include volatile and / or non-volatile memory. For example, memory 1230 may include random access memory, read-only memory, hard disk, and / or another type of memory (such as flash memory, magnetic memory, and / or optical memory). Memory 1230 may include internal memory (such as dynamic random access memory, read-only memory, or hard disk) and / or removable memory (such as that moved via a universal serial bus connection). Memory 1230 may be a non-transitory computer-readable medium. Memory 1230 may store data, instructions, and / or software (such as one or more software applications) related to the operation of device 1200. In some embodiments, memory 1230 includes one or more memories coupled to one or more processors (such as processor 1220) via bus 1210.

[0222] Input component 1240 enables device 1200 to receive input, such as user input and / or sensed input. For example, input component 1240 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, accelerometer, gyroscope, and / or actuator. Output component 1250 enables device 1200 to provide output, such as via a screen, speaker, and / or LED. Communication component 1260 enables device 1200 to communicate with other devices via wired and / or wireless connections. For example, communication component 1260 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0223] Apparatus 1200 may perform one or more of the steps or processes described herein. For example, a non-transitory computer-readable medium (such as memory 1230) may store a set of instructions (such as one or more instructions or codes) executed by processor 1220. Processor 1220 may execute a set of instructions to perform one or more of the steps or processes described herein. In some embodiments, one or more processors 1220 execute a set of instructions, causing one or more processors 1220 and / or apparatus 1200 to perform one or more of the steps or processes described herein. In some embodiments, hardware circuitry may replace or be combined with instructions to perform one or more of the steps or processes described herein. Processor 1220 may be additionally or alternatively configured to perform one or more of the steps or processes described herein. Therefore, the implementation methods described herein are not limited to any particular combination of hardware circuitry and software.

[0224] Figure 12 The number and arrangement of components shown are merely examples. Device 1200 may include additional components, fewer components, different components, or components with different configurations (compared to a combination). Figure 12 (The components described). One or more functions performed by another set of components of device 1200 may be performed by one set of components of device 1200, either additionally or alternatively.

[0225] Figure 13 The flowchart illustrates, in one example, the related process 1300 for forming the interface layer. In some embodiments, this process may be performed by one or more semiconductor process tools (such as deposition tools 102 to plating tools 112). Figure 13 One or more process steps. These may additionally or alternatively be performed by one or more components of device 1200 (e.g., processor 1220, memory 1230, input component 1240, output component 1250, and / or communication component 1260). Figure 13 One or more process steps.

[0226] like Figure 13As shown, process 1300 may include growing a seed layer on the spacer (step 1310). For example, one or more semiconductor process tools, such as deposition tool 102 to plating tool 112, may be used to grow a seed layer 1015a' on the inner spacer 245 or spacer layer 720, as described herein.

[0227] like Figure 13 As shown, process 1300 may include depositing silicon on a seed layer to form amorphous silicon and depositing silicon on a channel to form crystalline silicon (step 1320). For example, one or more semiconductor process tools such as deposition tool 102 to plating tool 112 may be used to deposit silicon on the seed layer 1015a' to form an amorphous silicon layer 1015a and to deposit silicon on the nanostructure channel 220 to form crystalline silicon 1015b, as described herein.

[0228] like Figure 13 As shown, process 1300 may include oxidizing amorphous silicon and crystalline silicon to form an interface layer (step 1330). For example, one or more semiconductor process tools, such as deposition tools 102 to plating tools 112, may be used to oxidize amorphous silicon 1015a and crystalline silicon 1015b to form interface layer 1010a, as described herein.

[0229] like Figure 13 As shown, process 1300 may include forming a high dielectric constant layer on the interface layer (step 1340). For example, one or more semiconductor process tools, such as deposition tool 102 to plating tool 112, may be used to form a high dielectric constant layer 1010b on the interface layer 1010a, as described herein.

[0230] Process 1300 may include additional implementations, such as any single implementation described below, or any combination of one or more other processes described below and / or elsewhere.

[0231] In the first embodiment, the step of growing the seed layer 1015a' includes using a precursor to form the seed layer, and the seed layer includes diisopropylaminosilane.

[0232] In the second embodiment (which can be carried out alone or in combination with the first embodiment), the temperature for growing the seed crystal layer 1015a' can be approximately 200°C to approximately 300°C.

[0233] In the third embodiment (which may be carried out alone or in combination with one or more of the first and second embodiments), silicon deposition includes using silane or silane to deposit silicon.

[0234] In the fourth embodiment (which can be carried out alone or in combination with one or more of the first to third embodiments), the temperature for silicon deposition can be approximately 300°C to approximately 500°C.

[0235] In the fifth embodiment (which can be performed alone or in combination with one or more of the first to fourth embodiments), the process pressure for silicon deposition can be less than 3.0 Torr.

[0236] In the sixth embodiment (which may be performed alone or in combination with one or more of the first to fifth embodiments), process 1300 includes a chemical oxide removal step to clean the nanostructure channel 220 before depositing silicon on the nanostructure channel 220.

[0237] In the seventh embodiment (which may be carried out alone or in combination with one or more of the first to sixth embodiments), the thickness of the crystalline silicon 1015b is approximately 4.0 Å to approximately 6.0 Å.

[0238] In the eighth embodiment (which may be carried out alone or in combination with one or more of the first to seventh embodiments), the thickness of the amorphous silicon 1015a is approximately 4.0 Å to approximately 6.0 Å.

[0239] Although Figure 13 Examples of the steps in display process 1300, in some embodiments of process 1300 may include additional steps, fewer steps, different steps, or steps configured differently (with combinations). Figure 13 (The steps described are similar). Two or more steps of process 1300 can be performed in parallel, either additionally or alternatively.

[0240] In this approach, a fresh silicon capping process is used to form the interface layer. For example, using diisopropylaminosilane as a precursor, amorphous silicon can be formed on the spacers and crystalline silicon on the channels. The amorphous silicon and crystalline silicon are oxidized to form an interface layer with a relatively uniform thickness, approximately 0.5 nm to approximately 1.0 nm. This improves miniaturization and gate efficiency, and reduces leakage current outside the channels.

[0241] As detailed above, some embodiments described herein provide methods for forming semiconductor structures. The methods include growing a seed layer on a spacer. The methods include depositing silicon on the seed layer to form amorphous silicon and depositing silicon on a channel to form crystalline silicon. The methods include oxidizing amorphous silicon and crystalline silicon to form an interface layer. The methods include forming a high-dielectric-constant layer on the interface layer.

[0242] In some embodiments, the step of growing a seed layer includes forming a seed layer using a precursor, wherein the precursor includes diisopropylaminosilane.

[0243] In some embodiments, the temperature for growing the seed crystal layer is approximately 200°C to approximately 300°C.

[0244] In some embodiments, the silicon deposition step includes using at least one of silane and disilane to deposit silicon.

[0245] In some embodiments, the temperature for silicon deposition is approximately 300°C to approximately 500°C.

[0246] In some embodiments, the pressure for silicon deposition is less than 3.0 Torr.

[0247] In some embodiments, the method further includes a chemical oxide removal step to clean the channel before depositing silicon onto it.

[0248] In some embodiments, the thickness of the crystalline silicon is approximately 4.0 Å to approximately 6.0 Å.

[0249] In some embodiments, the thickness of the amorphous silicon is approximately 4.0 Å to approximately 6.0 Å.

[0250] As detailed above, some embodiments described herein provide methods for forming semiconductor structures. The methods include growing a seed layer on a spacer. The methods include depositing silicon on the seed layer to form amorphous silicon and depositing silicon on a channel to form crystalline silicon. The methods include performing multiple cycles such that the thicknesses of the crystalline silicon and amorphous silicon are each approximately 4.0 Å to approximately 6.0 Å, wherein each cycle includes an oxidation process and a trimming process. The methods include oxidizing the amorphous silicon and crystalline silicon to form an interface layer.

[0251] In some embodiments, the step of growing a seed layer includes: using a precursor to form a seed layer, wherein the precursor includes diisopropylaminosilane.

[0252] In some embodiments, the silicon deposition step includes using at least one of silane and disilane to deposit silicon.

[0253] In some embodiments, the trimming process includes an etching process that is selective for silicon oxide.

[0254] As detailed above, some embodiments described herein provide semiconductor structures. The semiconductor structure includes nanostructured channels formed between multiple source / drain regions. The semiconductor structure includes a gate structure formed around the nanostructured channels. The semiconductor structure includes spacers located between an interlayer dielectric layer and the gate structure. The semiconductor structure includes an interface layer contacting the nanostructured channels and the spacers, the interface layer comprising silicon oxide, and the thickness of the interface layer being approximately 0.5 nm to approximately 1.0 nm.

[0255] In some embodiments, the semiconductor structure further includes an inner spacer located between the source / drain region and the gate structure, wherein the interface layer is in contact with the inner spacer.

[0256] In some embodiments, the portion of the interface layer that contacts the nanostructure channel, the portion of the interface layer that contacts the spacer, and the portion of the interface layer that contacts the inner spacer have the same thickness.

[0257] In some embodiments, the semiconductor structure further includes an oxygen-rich layer located at the interface between the nanostructure channel and the inner spacer.

[0258] In some embodiments, the ratio of the thickness of the inner spacer to the thickness of the interface layer is approximately 4.0 to approximately 8.0.

[0259] In some embodiments, the thickness of the inner spacer is approximately 3.5 nm to approximately 4.5 nm.

[0260] In some embodiments, the interface layer is in contact with the interface between the nanostructure channel and the spacer.

[0261] In some embodiments, the ratio of the thickness of the spacer to the thickness of the interface layer is approximately 4.0 nm to approximately 8.0 nm.

[0262] In some embodiments, the thickness of the spacer is approximately 3.5 nm to approximately 4.5 nm.

[0263] In some embodiments, the portion of the interface layer that contacts the nanostructure channel and the portion of the interface layer that contacts the spacer have the same thickness.

[0264] The term "meets the critical value" as used here, depending on the context, can mean greater than the critical value, greater than or equal to the critical value, less than the critical value, less than or equal to the critical value, equal to the critical value, not equal to the critical value, or a similar definition.

[0265] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A nanostructured channel is formed between multiple source / drain regions; A gate structure is formed around the plurality of said nanostructure channels; A spacer is located between an interlayer dielectric layer and the gate structure; as well as An interface layer is provided that contacts the nanostructure channel and the spacer. The interface layer includes silicon oxide and has a thickness of 0.5 nm to 1.0 nm.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: An inner spacer is located between the plurality of source / drain regions and the gate structure. The interface layer is in contact with the inner spacer.

3. The semiconductor structure as described in claim 2, characterized in that, The portion of the interface layer that contacts the nanostructure channel, the portion that contacts the spacer, and the portion that contacts the inner spacer have the same thickness.

4. The semiconductor structure as described in claim 2, characterized in that, Also includes: An oxygen-rich layer is located at the interface between the nanostructure channel and the inner spacer.

5. The semiconductor structure as described in claim 2, characterized in that, The ratio of the thickness of the inner spacer to the thickness of the interface layer is 4.0 to 8.

0.

6. The semiconductor structure as described in claim 5, characterized in that, The thickness of the inner spacer is 3.5 nm to 4.5 nm.

7. The semiconductor structure as described in claim 1, characterized in that, The interface layer is in contact with the interface between the nanostructure channel and the spacer.

8. The semiconductor structure as described in claim 1, characterized in that, The ratio of the thickness of the spacer to the thickness of the interface layer is 4.0 nm to 8.0 nm.

9. The semiconductor structure as described in claim 8, characterized in that, The thickness of the spacer is 3.5 nm to 4.5 nm.

10. The semiconductor structure as claimed in claim 1, characterized in that, The thickness of the portion of the interface layer that contacts the nanostructure channel and the portion of the interface layer that contacts the spacer are the same.

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