Solar cell

Abstract

The utility model discloses a solar cell, and relates to the technical field of solar cells. The solar cell includes: a silicon substrate; the P-type doped region and the N-type doped region are arranged on the main surface of the silicon substrate; the N-type doped region is provided with a first tunneling oxide layer, a first N-type doped layer, a heat-resistant isolation layer and a second N-type doped layer from inside to outside; and the P-type doped region is provided with a second tunneling oxide layer and a P-type doped layer from inside to outside. According to the embodiment, synchronous diffusion of the N-type doping element and the P-type doping element can be realized through one-time high-temperature annealing.

Description

Technical Field

[0001] This utility model relates to the field of solar cell technology, and in particular to a solar cell. Background Technology

[0002] With the development of photovoltaic technology, increasing emphasis is being placed on the fabrication efficiency of solar cells. For solar cells containing both P-type and N-type doped regions, the diffusion temperatures and rates of N-type and P-type dopants differ. The diffusion temperature of P-type dopants during P-type layer fabrication is higher than that of N-type dopants during N-type layer fabrication. Therefore, P-type and N-type doped layers need to be fabricated separately, resulting in a complex, cumbersome, and time-consuming solar cell fabrication process. Utility Model Content

[0003] In view of this, the present invention provides a solar cell that can achieve simultaneous diffusion of N-type and P-type dopants through a single high-temperature annealing process.

[0004] To achieve the above objectives, a solar cell is provided according to an embodiment of the present invention, comprising:

[0005] Silicon substrate;

[0006] P-type doped regions and N-type doped regions are disposed on the main surface of the silicon substrate;

[0007] The aforementioned N-type doped region is provided with a first tunneling oxide layer, a first N-type doped layer, a heat-insulating layer, and a second N-type doped layer from the inside out;

[0008] The aforementioned P-type doped region is provided with a second tunneling oxide layer and a P-type doped layer from the inside out.

[0009] Optionally, the thickness of the first tunneling oxide layer is 1-2 nm.

[0010] Optionally, the thickness of the heat-insulating layer is 1-20 nm.

[0011] Optionally, the thickness of both the first N-type doped layer and the second N-type doped layer is 80-200 nm.

[0012] Optionally, the N-type doped region further includes a third tunneling oxide layer, wherein,

[0013] The third tunneling oxide layer is located between the first N-type doped layer and the thermally insulating layer.

[0014] Optionally, the thickness of the third tunneling oxide layer is 1-2 nm;

[0015] Optionally, the N-type doped region further includes: a fourth tunneling oxide layer, wherein,

[0016] The fourth tunneling oxide layer is located between the thermally insulating layer and the second N-type doped layer.

[0017] Optionally, the thickness of the fourth tunneling oxide layer is 1-2 nm.

[0018] Optionally, the doping concentration of the first N-type doped layer is lower than the doping concentration of the second N-type doped layer.

[0019] Optionally, the doping concentration of the first N-type doped layer is less than or equal to 4 × 10⁻⁶. 20 pcs / cm 3 ;

[0020] And / or,

[0021] The doping concentration of the second N-type doped layer is greater than or equal to 5 × 10⁻⁶. 20 pcs / cm 3 And less than or equal to 5 × 10 25 pcs / cm 3 .

[0022] One embodiment of the above-mentioned utility model has the following advantages or beneficial effects: a stacked structure including a first tunneling oxide layer, a first N-type doped layer, a heat-insulating layer, and a second N-type doped layer is formed from the inside to the outside in the N-type doped region. The heat-insulating layer can block some heat. Even at a high annealing temperature, the temperature received by the functional layer between the heat-insulating layer and the silicon substrate is lower than the external annealing temperature. This can prevent the N-type dopant element from excessively penetrating the first tunneling oxide layer, increase the upper limit of the diffusion temperature of the N-type dopant element that can be withstood during the preparation of the first N-type doped layer, and ensure the yield and photoelectric conversion efficiency of the solar cell.

[0023] In addition, by setting a third and a fourth tunneling oxide layer, a tunneling channel is provided for the diffusion of N-type dopants, which improves the diffusion rate of N-type dopants and further ensures that the doping concentration of the first N-type doped layer after high-temperature annealing can meet the process requirements.

[0024] The further effects of the aforementioned unconventional alternative methods will be explained below in conjunction with specific implementation methods. Attached Figure Description

[0025] The accompanying drawings are provided to better understand this utility model and do not constitute an undue limitation thereof. Wherein:

[0026] Figure 1 This is a schematic flowchart of a method for preparing a solar cell according to an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of another structure of a solar cell according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the TOPCon battery according to Embodiment 1 of this utility model;

[0030] Figure 5 This is a structural schematic diagram of the TBC battery according to Embodiment 2 of this utility model.

[0031] Figure label:

[0032] 10-Silicon substrate; 20-N-type doped region; 21-First tunneling oxide layer; 22-First N-type doped layer; 23-Third tunneling oxide layer; 24-Heat-insulating layer; 25-Fourth tunneling oxide layer; 26-Second N-type doped layer; 27-Second metal electrode; 30-P-type doped region; 31-Second tunneling oxide layer; 32-P-type doped layer; 33-P+ layer; 34-First metal electrode; 40-Passivation layer; 50-Antireflection layer. Detailed Implementation

[0033] The following description, in conjunction with the accompanying drawings, illustrates exemplary embodiments of the present invention, including various details to aid understanding. These embodiments should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0034] It should be noted that, where there is no conflict, the embodiments of this utility model and the technical features thereof can be combined with each other.

[0035] Figure 1 This is a schematic diagram illustrating the main steps of a solar cell fabrication method according to an embodiment of the present invention. Figure 1 As shown, the solar cell fabrication method of this utility model embodiment mainly includes the following steps A1 to A2:

[0036] Step A1: A first tunneling oxide layer 21, a functional adjustment layer, a thermal insulation layer 24, and an N-type initial doped layer are formed from the inside to the outside of the N-type doped region 20 on the main surface of the silicon substrate 10, and a second tunneling oxide layer 31 and a P-type initial doped layer are formed from the inside to the outside of the P-type doped region 30 on the main surface of the silicon substrate 10; wherein the N-type initial doped layer contains N-type doping elements, and the P-type initial doped layer contains P-type doping elements.

[0037] The N-type doped region 20 may be located on either surface of the silicon substrate 10. Optionally, depending on the type of solar cell to be fabricated, the N-type doped region 20 and the P-type doped region 30 may be located on two separate main surfaces of the silicon substrate 10; or, the N-type doped region 20 and the P-type doped region 30 may be located on the same main surface of the silicon substrate 10. As an example, when fabricating a TOPCon (Tunnel Oxide Passivated Contact) cell, the N-type doped region 20 and the P-type doped region 30 should be located on two main surfaces of the silicon substrate 10, depending on the structure of the TOPCon cell; when fabricating an interdigitated back contact (IBC) cell or a TBC (TOPCon-IBC) cell, the N-type doped region 20 and the P-type doped region 30 should be located on the same main surface of the silicon substrate 10.

[0038] The functional adjustment layer is a silicon film layer. The concentration of N-type dopant in this silicon film layer is greater than or equal to 0. As an example, the silicon film layer can be a polycrystalline silicon layer containing an N-type dopant concentration of 0. As another example, the silicon film layer can be a polycrystalline silicon layer containing an N-type dopant concentration greater than 0.

[0039] It should be noted that the doping concentration of the functional adjustment layer is lower than that of the initial N-type doped layer, so that during the annealing process, the N-type dopant in the initial N-type doped layer can diffuse into the functional adjustment layer, thereby achieving gradient diffusion of the N-type dopant.

[0040] Among them, N-type doping elements include valence elements such as phosphorus or arsenic that can provide additional free electrons; P-type doping elements include trivalent elements such as aluminum or boron that can form holes.

[0041] A thermal barrier layer 24 is provided between the functional adjustment layer and the initial N-type doped layer to block high temperatures during annealing, preventing the functional adjustment layer from being subjected to excessively high temperatures that could affect the diffusion of N-type doped elements. The thermal barrier layer 24 can be prepared by plasma-enhanced chemical vapor deposition (PECVD), but is not limited to this method.

[0042] Furthermore, the heat-insulating layer 24 can be a silicon carbide layer, which can block some heat without hindering the diffusion of N-type doped elements.

[0043] The N-type initial doped layer is a polycrystalline silicon layer with an N-type dopant concentration greater than 0, and the N-type dopant concentration contained therein is greater than that contained in the functional tuning layer.

[0044] Step A2: Simultaneously perform high-temperature annealing on the N-type doped region 20 and the P-type doped region 30 to diffuse the P-type dopant and the N-type dopant. The high-temperature annealing temperature satisfies the diffusion temperature of the P-type dopant. The N-type dopant diffuses through the heat-insulating layer 24 to the functional adjustment layer, thereby transforming the functional adjustment layer into a first N-type doped layer 22, the initial N-type doped layer into a second N-type doped layer 26, and the initial P-type doped layer into a P-type doped layer 32.

[0045] During the simultaneous high-temperature annealing of N-type doped region 20 and P-type doped region 30, the annealing temperature should meet the diffusion temperature of P-type dopant, so that the diffusion of P-type dopant in P-type doped region 30 and the diffusion of N-type dopant in N-type doped region 20 can occur simultaneously, avoiding the situation where the diffusion of P-type dopant cannot occur due to the annealing temperature being too low.

[0046] Alternatively, the annealing temperature can be between 870℃ and 1100℃. As an example, the annealing temperature can be 870℃, 950℃, 1030℃, or 1100℃, etc.

[0047] Optionally, the high-temperature annealing process can be carried out in a tube furnace or a chain furnace, but is not limited to these.

[0048] During the high-temperature annealing process, the heat-insulating layer 24 can block some of the high temperature, so that the temperature received by the functional adjustment layer is lower than the annealing temperature, thereby allowing the N-type dopant element in the initial N-type doped layer to diffuse into the functional adjustment layer, thus realizing the diffusion of the N-type dopant element.

[0049] Furthermore, by adjusting the thickness control function of the heat-insulating layer 24, the temperature received by the layer is adjusted. After high-temperature annealing, only a small amount of N-type dopant penetrates the first tunneling oxide layer 21, thereby avoiding excessive penetration of the first tunneling oxide layer 21 by the N-type dopant at high temperature, which reduces its passivation effect. This allows the diffusion rate and concentration of the N-type dopant to meet the process requirements, thereby forming the first N-type doped layer 22. This achieves the adjustment of the doping concentration of the N-type dopant in the first N-type doped layer 22, and the synchronous diffusion of P-type and N-type dopant is achieved through a single annealing process.

[0050] Optionally, the temperature of the functional conditioning layer during the annealing process can be 600℃-800℃. As an example, the temperature of the functional conditioning layer during the annealing process can be 600℃, 650℃, 700℃, 750℃, or 800℃, etc.

[0051] Furthermore, the thickness of the thermal barrier layer 24 can be 1-20 nm. By setting the thickness of the thermal barrier layer 24 within a reasonable range, it not only blocks some heat from reaching the functional adjustment layer, but also allows an appropriate concentration of N-type dopant to reach the functional adjustment layer, causing the functional adjustment layer to transform into a first N-type doped layer 22 with a suitable doping concentration. As an example, the thickness of the thermal barrier layer 24 can be 1 nm, 5 nm, 10 nm, 18 nm, or 20 nm, etc.

[0052] In an optional embodiment, step A1 above includes:

[0053] Step A11: A first tunneling oxide layer 21, a functional adjustment layer and a thermal insulation layer 24 are formed from the inside to the outside of the N-type doped region 20 on the main surface of the silicon substrate 10.

[0054] Step A12: An N-type initial doped layer is formed on the outside of the heat-insulating layer 24 by in-situ doping or high-temperature furnace tube diffusion doping.

[0055] The first tunneling oxide layer 21 can be prepared by low-pressure chemical vapor deposition (LPCVD), but is not limited to this method.

[0056] Step A12, which involves forming an N-type initial doped layer through in-situ doping, includes introducing N doping elements into the reaction material flow during the growth process of the N-type initial doped layer, thereby doping while growing, and finally forming an N-type initial doped layer.

[0057] Step A12, which involves diffusion doping through a high-temperature furnace tube, mainly includes: forming a polycrystalline silicon layer on the outside of the heat-insulating layer 24; placing the silicon substrate 10, which forms the first tunneling oxide layer 21, the functional adjustment layer, the heat-insulating layer 24, and the polycrystalline silicon layer from the inside to the outside of the N-type doped region 20 on the main surface, on a support tool such as a quartz boat; placing the support tool into the high-temperature furnace tube; heating the furnace to the diffusion temperature of the N-type dopant element; introducing the N-type dopant source gas; stopping the introduction of the N-type dopant source gas after a preset doping time; and cooling the high-temperature furnace tube to obtain the initial N-type doped layer on the outside of the heat-insulating layer 24.

[0058] It should be noted that when using high-temperature furnace tube diffusion doping to form the initial N-type doped layer, due to the high temperature conditions, some N-type dopants can diffuse into the functional adjustment layer through the heat-insulating layer 24 during the formation of the initial N-type doped layer, thus achieving N-type dopant diffusion. However, due to the limitations of doping temperature and doping time in this step, the N-type dopants diffused into the functional adjustment layer may not be able to completely transform the functional adjustment layer into the first N-type doped layer 22. Therefore, a subsequent high-temperature annealing step is still required to ensure that the functional adjustment layer is completely transformed into the first N-type doped layer 22.

[0059] In one possible implementation of an alternative embodiment, step A11 above includes:

[0060] Step A111: A first tunneling oxide layer 21 is formed at the position of the N-type doped region 20 on the main surface of the silicon substrate 10;

[0061] Step A112: The above-mentioned functional adjustment layer is formed on the outside of the first tunneling oxide layer 21 by in-situ doping;

[0062] Step A113: Form a heat-insulating layer 24 on the outside of the above-mentioned functional adjustment layer.

[0063] The functional adjustment layer is a silicon film with an N-type dopant concentration greater than or equal to 0. Furthermore, the silicon film can be a polycrystalline silicon layer.

[0064] Step A112, forming a functional adjustment layer through in-situ doping, includes: introducing N doping elements into the reactive material flow during the growth process of the functional adjustment layer, thereby doping while growing, and finally forming the functional adjustment layer.

[0065] It is understandable that when the concentration of N-type dopants in the functional adjustment layer is 0, a polysilicon layer can be grown directly on the outside of the first tunneling oxide layer 21 without in-situ doping, and the polysilicon layer with a concentration of N-type dopants of 0 can be directly used as the functional adjustment layer.

[0066] In an optional embodiment, step A1 further includes forming a third tunneling oxide layer 23 between the functional adjustment layer and the thermal insulation layer 24 for the N-type doped region 20 on the main surface of the silicon substrate 10.

[0067] Specifically, step A1 includes forming a first tunneling oxide layer 21, a functional adjustment layer, a third tunneling oxide layer 23, a thermal insulation layer 24, and an N-type initial doped layer from the inside to the outside of the N-type doped region 20 on the main surface of the silicon substrate 10.

[0068] By forming a third tunneling oxide layer 23 between the functional adjustment layer and the thermal insulation layer 24, a tunneling channel for N-type doped elements is formed. Due to the quantum tunneling effect, the tunneling channel facilitates the passage of N-type doped elements and their rapid arrival at the functional adjustment layer, thereby shortening the process time.

[0069] In an optional embodiment, step A1 further includes forming a fourth tunneling oxide layer 25 between the thermally insulating layer 24 and the initial N-type doped layer for the N-type doped region 20 on the main surface of the silicon substrate 10.

[0070] Specifically, step A1 includes forming a first tunneling oxide layer 21, a functional adjustment layer, a thermal insulation layer 24, a fourth tunneling oxide layer 25, and an N-type initial doped layer from the inside to the outside of the N-type doped region 20 on the main surface of the silicon substrate 10.

[0071] By forming a fourth tunneling oxide layer 25 between the heat-insulating layer 24 and the initial N-type doped layer, a tunneling channel for the N-type doped element is formed, which assists in the diffusion of the N-type doped element during the annealing process.

[0072] Furthermore, step A1 further includes: forming a third tunneling oxide layer 23 between the functional adjustment layer and the thermal barrier layer 24 for the N-type doped region 20 on the main surface of the silicon substrate 10; and forming a fourth tunneling oxide layer 25 between the thermal barrier layer 24 and the N-type initial doped layer for the N-type doped region 20 on the main surface of the silicon substrate 10.

[0073] Specifically, step A1 includes forming, from the inside out, a first tunneling oxide layer 21, a functional adjustment layer, a third tunneling oxide layer 23, a thermal insulation layer 24, a fourth tunneling oxide layer 25, and an N-type initial doped layer on the N-type doped region 20 on the main surface of the silicon substrate 10.

[0074] By forming a third tunneling oxide layer 23 between the functional adjustment layer and the thermal insulation layer 24, and a fourth tunneling oxide layer 25 between the thermal insulation layer 24 and the N-type initial doped layer, a tunneling channel for the N-type doped element is formed, which assists in the diffusion of the N-type doped element during the annealing process.

[0075] According to the solar cell fabrication method of this utility model embodiment, by forming a stacked structure from the inside to the outside of the N-type doped region 20, including a first tunneling oxide layer 21, a functional adjustment layer, a heat-insulating layer 24, and an N-type initial doped layer, when the diffusion temperatures of N-type dopants and P-type dopants are different, the heat-insulating layer 24 can block some heat, so that the diffusion of N-type and P-type dopants does not need to be carried out in steps. The synchronous diffusion of N-type and P-type dopants can be achieved through a single high-temperature annealing, which optimizes the solar cell fabrication process, shortens the fabrication time, and improves the production capacity. At the same time, by blocking some heat through the heat-insulating layer 24, the excessive penetration of N-type dopants into the first tunneling oxide layer 21 is prevented, thus reducing its passivation effect and ensuring the yield and photoelectric conversion efficiency of the solar cell.

[0076] Furthermore, by setting the doping concentration of the initial N-type doped layer to be greater than that of the functional adjustment layer, gradient diffusion of N-type doped elements was achieved. By setting the third tunneling oxide layer 23 and the fourth tunneling oxide layer 25, tunneling channels were provided for the diffusion of N-type doped elements, increasing the diffusion rate of N-type doped elements and further ensuring that the doping concentration of the first N-type doped layer 22 after high-temperature annealing met the process requirements.

[0077] Figure 2 This is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention. Figure 2 , Figure 4 and Figure 5 As shown, the solar cell of this utility model embodiment includes: a silicon substrate 10; a P-type doped region 30 and an N-type doped region 20 disposed on the main surface of the silicon substrate 10; the N-type doped region 20 is provided with a first tunneling oxide layer 21, a first N-type doped layer 22, a heat-insulating layer 24, and a second N-type doped layer 26 from the inside to the outside, wherein the N-type doping element contained in the first N-type doped layer 22 is partially or entirely derived from the second N-type doped layer 26; the P-type doped region 30 is provided with a second tunneling oxide layer 31 and a P-type doped layer 32 from the inside to the outside.

[0078] By setting the heat-insulating layer 24, some heat is blocked during the annealing process, allowing N-type dopants and P-type dopants to diffuse synchronously.

[0079] The thickness of the first tunneling oxide layer 21 can be 1-2 nm to ensure that the thinner first tunneling oxide layer 21 utilizes the quantum tunneling effect, allowing electrons to tunnel through quickly during solar cell operation while blocking hole recombination, thereby improving solar cell efficiency. As an example, the thickness of the first tunneling oxide layer 21 can be 1 nm, 1.3 nm, 1.5 nm, or 2 nm, etc.

[0080] The thickness of the aforementioned heat-insulating layer 24 can be 1-20 nm. By adjusting the thickness of the heat-insulating layer 24, the amount of heat it blocks can be controlled, further controlling the temperature received by the functional layer between the heat-insulating layer 24 and the silicon substrate 10 to be lower than the external annealing temperature. Even at higher annealing temperatures, N-type dopant elements can diffuse to form the first N-type doped layer 22 without excessively penetrating the first tunneling oxide layer 21. As an example, the thickness of the heat-insulating layer 24 can be 1 nm, 5 nm, 10 nm, or 20 nm, etc.

[0081] In addition, the heat-insulating layer 24 can be a silicon carbide layer, which can block some heat without blocking the diffusion of N-type doped elements.

[0082] The thicknesses of the first N-type doped layer 22 and the second N-type doped layer 26 can be 80-200 nm. It is understood that the thicknesses of the first N-type doped layer 22 and the second N-type doped layer 26 can be the same or different. By controlling the thicknesses of the first N-type doped layer 22 and the second N-type doped layer 26 within a reasonable range, the open-circuit voltage and fill factor of the solar cell are improved, the series resistance is reduced, and the performance of the solar cell is further enhanced. For example, the thickness of the first N-type doped layer 22 can be 80 nm, 100 nm, 140 nm, 180 nm, or 200 nm, etc.; the thickness of the second N-type doped layer 26 can be 80 nm, 110 nm, 140 nm, 190 nm, or 200 nm, etc.

[0083] In an optional embodiment of the present invention, the doping concentration of the first N-type doped layer 22 is less than the doping concentration of the second N-type doped layer 26.

[0084] Understandably, during the diffusion of N-type dopants, the functional adjustment layer transforms into a first N-type doped layer 22, and the initial N-type doped layer transforms into a second N-type doped layer 26. At this point, since the doping concentration of the initial N-type doped layer is greater than that of the functional adjustment layer, the N-type dopants diffuse from the initial N-type doped layer towards the functional adjustment layer, achieving gradient diffusion of the N-type dopants. After the N-type dopants have diffused, since some or all of the N-type dopants in the first N-type doped layer 22 originate from the second N-type doped layer 26, the doping concentration of the first N-type doped layer 22 is less than that of the second N-type doped layer 26. During the diffusion of N-type dopants from the initial N-type doped layer towards the functional adjustment layer, the thermal barrier layer 24 is relatively thin, allowing the N-type dopants to find a diffusion path within it. Furthermore, due to the high diffusion temperature and intense atomic thermal motion of the N-type dopants, they easily overcome the obstruction of the thermal barrier layer 24 and diffuse into the functional adjustment layer.

[0085] Furthermore, the doping concentration of the first N-type doped layer 22 is less than or equal to 4 × 10⁻⁶. 20 pcs / cm 3 And greater than or equal to 4 × 10 19 pcs / cm 3 The doping concentration of the second N-type doped layer 26 is greater than or equal to 5 × 10⁻⁶. 20 pcs / cm 3 By controlling the doping concentration of the first N-type doped layer 22 to be lower than that of the second N-type doped layer 26, a concentration gradient is formed. During the operation of the solar cell, charge carriers diffuse from the high-concentration region to the low-concentration region under the influence of this concentration gradient. By controlling the doping concentrations of the first N-type doped layer 22 and the second N-type doped layer 26 within a reasonable range, the solar cell can more effectively collect photogenerated charge carriers. For example, the doping concentration of the first N-type doped layer 22 can be 4 × 10⁻⁶. 19 pcs / cm 3 10×10 19 pcs / cm 3 22×10 19 pcs / cm 3 3×10 20 pcs / cm 3 Or 4×10 20 pcs / cm 3 The doping concentration of the second N-type doped layer 26 can be 5 × 10⁻⁶. 20 pcs / cm 3 7×10 20 pcs / cm 3 Or 9×10 20 pcs / cm 3 wait.

[0086] In an optional embodiment of this invention, the N-type doped region 20 further includes a third tunneling oxide layer 23, wherein the third tunneling oxide layer 23 is located between the first N-type doped layer 22 and the thermal barrier layer 24. That is, the N-type doped region 20 is sequentially provided with a first tunneling oxide layer 21, a first N-type doped layer 22, a third tunneling oxide layer 23, a thermal barrier layer 24, and a second N-type doped layer 26 from the inside out. The third tunneling oxide layer 23 provides a tunneling channel for the diffusion of N-type dopants, assisting their diffusion and improving diffusion efficiency.

[0087] The thickness of the third tunneling oxide layer 23 can be 1-2 nm. By controlling the thickness of the third tunneling oxide layer 23, a thinner third tunneling oxide layer 23 can provide tunneling channels for N-type dopants to improve their passage speed without affecting other battery performance characteristics. For example, the thickness of the third tunneling oxide layer 23 can be 1 nm, 0.3 nm, 0.5 nm, 0.8 nm, or 2 nm.

[0088] In an optional embodiment of this invention, the N-type doped region 20 further includes a fourth tunneling oxide layer 25, wherein the fourth tunneling oxide layer 25 is located between the thermally insulating layer 24 and the second N-type doped layer 26. That is, the N-type doped region 20 is sequentially provided with a first tunneling oxide layer 21, a first N-type doped layer 22, a thermally insulating layer 24, a fourth tunneling oxide layer 25, and a second N-type doped layer 26 from the inside out. The fourth tunneling oxide layer 25 provides a tunneling channel for the diffusion of N-type dopants, assisting their diffusion and improving diffusion efficiency.

[0089] The thickness of the fourth tunneling oxide layer 25 can be 1-2 nm. By controlling the thickness of the fourth tunneling oxide layer 25, a thinner fourth tunneling oxide layer 25 can provide tunneling channels for N-type dopants to improve their passage speed without affecting other battery performance characteristics. For example, the thickness of the fourth tunneling oxide layer 25 can be 1 nm, 0.3 nm, 0.5 nm, 0.8 nm, or 2 nm, etc.

[0090] In one optional embodiment of this utility model, such as Figure 3 As shown, the aforementioned N-type doped region 20 is provided with, from the inside out, a first tunneling oxide layer 21, a first N-type doped layer 22, a third tunneling oxide layer 23, a thermally insulating layer 24, a fourth tunneling oxide layer 25, and a second N-type doped layer 26. Specifically, a third tunneling oxide layer 23 is disposed between the first N-type doped layer 22 and the thermally insulating layer 24, and a fourth tunneling oxide layer 25 is disposed between the thermally insulating layer 24 and the second N-type doped layer 26. The placement of the third tunneling oxide layer 23 and the fourth tunneling oxide layer 25 provides tunneling channels for the diffusion of N-type dopants, assisting their diffusion and improving diffusion efficiency.

[0091] It should be noted that, Figure 2 and Figure 3 The schematic diagram of the solar cell shown only shows a part of the solar cell structure, namely the structure of the silicon substrate 10 and an N-type doped region 20 on its main surface.

[0092] According to the embodiment of the present invention, a solar cell is formed in the N-type doped region 20 from the inside out, comprising a first tunneling oxide layer 21, a first N-type doped layer 22, a heat-insulating layer 24, and a second N-type doped layer 26. The heat-insulating layer 24 can block some heat. Even at a high annealing temperature, the temperature received by the functional layer between the heat-insulating layer 24 and the silicon substrate 10 is lower than the external annealing temperature. This can prevent the N-type dopant element from excessively penetrating the first tunneling oxide layer 21, and increase the upper limit of the diffusion temperature of the N-type dopant element that can be withstood during the preparation of the first N-type doped layer 22. The diffusion of N-type dopant element and P-type dopant element can be realized simultaneously, ensuring the yield and photoelectric conversion efficiency of the solar cell.

[0093] In addition, by setting the third tunneling oxide layer 23 and the fourth tunneling oxide layer 25, a tunneling channel is provided for the diffusion of N-type doped elements, which improves the diffusion rate of N-type doped elements and further ensures that the doping concentration of the first N-type doped layer 22 after high-temperature annealing can meet the process requirements.

[0094] Example 1

[0095] This embodiment provides a method for fabricating a TOPCon battery and its structure, the structure of which can be referenced. Figure 4 The preparation method includes the following steps B1 to B11:

[0096] Step B1: Texturing the two main surfaces of the N-type silicon substrate 10 to form a silicon substrate 10 with a pyramidal textured surface on the main surfaces;

[0097] Step B2: The N-type silicon substrate 10 is subjected to boron diffusion treatment to prepare a PN junction, thereby forming a P+ layer 33 and a borosilicate glass (BSG) layer from the inside to the outside on the first main surface. At the same time, a P+ layer 33 and a BSG layer are formed on the second main surface due to the winding plating phenomenon.

[0098] Among them, a PN junction exists in the P+ layer 33;

[0099] It should be noted that the first main surface of the N-type silicon substrate 10 refers to the side of the solar cell that faces the sunlight when it is working, and correspondingly, the second main surface refers to the side of the solar cell that faces away from the sunlight when it is working.

[0100] Step B3: Etch the second main surface to remove the P+ layer 33 and BSG layer generated by the wrap-around plating; retain the BSG layer on the first main surface;

[0101] Step B4: Deposit a first tunneling oxide layer 21 on the second main surface of the N-type silicon substrate 10 using LPCVD, and form a functional adjustment layer on the outside of the first tunneling oxide layer 21 by in-situ doping.

[0102] Step B5: The third tunneling oxide layer 23, the thermal barrier layer 24 and the fourth tunneling oxide layer 25 are sequentially deposited on the functional adjustment layer using the LPCVD method, and phosphorus doping is performed by in-situ doping to form an N-type initial doped layer on the outside of the fourth tunneling oxide layer 25.

[0103] In this case, the doping concentration of the N-type initial doped layer is greater than the doping concentration of the functional tuning layer;

[0104] Step B6: Remove the P+ layer and BSG layer from the first main surface and side surfaces by etching;

[0105] Step B7: Cover the first main surface with a mask suitable for the TOPCon cell structure, deposit the second tunneling oxide layer 31 on the P+ layer 33 using LPCVD, and perform boron doping treatment in situ to form a P-type initial doped layer on the outside of the second tunneling oxide layer 31.

[0106] Step B8: Simultaneously perform high-temperature annealing on the above-mentioned N-type doped region 20 and the above-mentioned P-type doped region 30 to achieve synchronous diffusion of boron and phosphorus elements.

[0107] The annealing temperature is 870℃. During the high-temperature annealing process, the heat-insulating layer 24 can block some of the high temperature, so that the heat received by the functional adjustment layer is lower than the annealing temperature, thereby allowing the phosphorus element in the N-type initial doped layer to diffuse into the functional adjustment layer and achieve phosphorus diffusion; at the same time, since the annealing temperature meets the temperature for boron diffusion, boron diffusion and phosphorus diffusion occur simultaneously.

[0108] Before the high-temperature annealing treatment, the P-type doped region 30 includes a P+ layer 33, a second tunneling oxide layer 31, and a P-type initial doped layer on the first main surface of the silicon substrate 10; the N-type doped region 20 includes a first tunneling oxide layer 21, a functional adjustment layer, a third tunneling oxide layer 23, a thermally insulating layer 24, a fourth tunneling oxide layer 25, and an N-type initial doped layer on the second main surface of the silicon substrate 10.

[0109] Through simultaneous diffusion of P-type and N-type dopants, the initial P-type doped layer is transformed into a P-type doped layer 32, the functional adjustment layer is transformed into a first N-type doped layer 22, and the initial N-type doped layer is transformed into a second N-type doped layer 26. Therefore, after high-temperature annealing, the P-type doped region 30 includes a P+ layer 33, a second tunneling oxide layer 31, and a P-type doped layer 32 on the first main surface of the silicon substrate 10; the N-type doped region 20 includes a first tunneling oxide layer 21, a first N-type doped layer 22, a third tunneling oxide layer 23, a thermally insulating layer 24, a fourth tunneling oxide layer 25, and a second N-type doped layer 26 on the second main surface of the silicon substrate 10.

[0110] Step B9: Form a passivation layer 40 on the P-type doped layer 32 on the first main surface; wherein, the passivation layer 40 is an aluminum oxide layer;

[0111] Step B10: An antireflection layer 50 is formed on the second N-type doped layer 26 on the second main surface and the passivation layer 40 on the first main surface, respectively; wherein, the material of the antireflection layer 50 includes, but is not limited to, silicon nitride;

[0112] Step B11: Screen printing is performed on the first and second main surfaces to form a first metal electrode 34 on the first main surface and a second metal electrode 27 on the second main surface. Then, the semi-finished battery cell with the electrodes is sintered and inspected to obtain a product possessing the following characteristics: Figure 4 The TOPCon battery with the structure shown.

[0113] Example 2

[0114] This embodiment provides a method for preparing a TBC battery and its structure, the structure of which can be referred to... Figure 5 The preparation method includes the following steps C1 to C10:

[0115] Step C1: Polish the two main surfaces of the N-type silicon substrate 10;

[0116] Step C2: A second tunneling oxide layer 31 is deposited on the second main surface of the silicon substrate 10 using LPCVD, and boron doping is performed in situ to form a P-type initial doped layer on the outside of the second tunneling oxide layer 31.

[0117] Step C3: Laser removal of the second tunneling oxide layer 31 and the initial P-type doped layer in the N-type doped region 20 and the isolation region; and cleaning of the laser-grooved area;

[0118] Step C4: Cover the second main surface with a mask suitable for TBC cell structure, deposit the first tunneling oxide layer 21 in the N-type doped region 20 and the isolation region using LPCVD, and perform phosphorus doping on the second amorphous silicon layer in situ to form a functional adjustment layer.

[0119] Step C5: The third tunneling oxide layer 23, the heat-insulating layer 24 and the fourth tunneling oxide layer 25 are sequentially deposited on the functional adjustment layer using the LPCVD method, and phosphorus doping is performed by high-temperature furnace tube diffusion doping to form an N-type initial doped layer on the outside of the fourth tunneling oxide layer 25.

[0120] In this case, the doping concentration of the N-type initial doped layer is greater than the doping concentration of the functional tuning layer;

[0121] Step C6: Remove the first tunneling oxide layer 21, the functional adjustment layer, the third tunneling oxide layer 23, the thermal insulation layer 24, the fourth tunneling oxide layer 25, and the N-type initial doped layer of the isolation region by laser.

[0122] Step C7: Simultaneously perform high-temperature annealing on the above-mentioned N-type doped region 20 and the above-mentioned P-type doped region 30 to achieve synchronous diffusion of boron and phosphorus elements.

[0123] The annealing temperature is 1100℃. During the high-temperature annealing process, the heat-insulating layer 24 can block some of the high temperature, so that the heat received by the functional adjustment layer is lower than the annealing temperature, thereby allowing the phosphorus element in the N-type initial doped layer to diffuse into the functional adjustment layer and achieve phosphorus diffusion; at the same time, since the annealing temperature meets the temperature for boron diffusion, boron diffusion and phosphorus diffusion occur simultaneously.

[0124] Before high-temperature annealing, the P-type doped region 30 includes a second tunneling oxide layer 31 and a P-type initial doped layer on the first main surface of the silicon substrate 10; the N-type doped region 20 includes a first tunneling oxide layer 21, a functional adjustment layer, a third tunneling oxide layer 23, a thermal insulation layer 24, a fourth tunneling oxide layer 25, and an N-type initial doped layer on the second main surface of the silicon substrate 10.

[0125] Through simultaneous diffusion of P-type and N-type dopants, the initial P-type doped layer transforms into a P-type doped layer 32. Simultaneously, a BSG layer forms on the surface of the P-type doped layer 32 away from the silicon substrate 10. The functional adjustment layer transforms into a first N-type doped layer 22, and the initial N-type doped layer transforms into a second N-type doped layer 26. Simultaneously, a phosphorosilicate glass (PSG) layer forms on the surface of the second N-type doped layer 26 away from the silicon substrate 10. Therefore, after high-temperature annealing, the P-type doped region 30 includes a second tunneling oxide layer 31, a P-type doped layer 32, and a BSG layer on the first main surface of the silicon substrate 10; the N-type doped region 20 includes a first tunneling oxide layer 21, a first N-type doped layer 22, a third tunneling oxide layer 23, a thermally insulating layer 24, a fourth tunneling oxide layer 25, a second N-type doped layer 26, and a PSG layer on the second main surface of the silicon substrate 10.

[0126] Step C8: Perform texturing on the isolation area and remove the BSG and PSG layers through texturing;

[0127] Step C9: A passivation layer 40 and an antireflection layer 50 are formed on both the first and second main surfaces; wherein, the passivation layer 40 is a titanium oxide layer; and the antireflection layer 50 is a silicon nitride layer.

[0128] Step C10: Screen printing is performed on the second main surface to form a first metal electrode 34 in the P-type doped region 30 and a second metal electrode 27 in the N-type doped region 20. Then, the semi-finished battery cell with the electrodes is sintered and inspected to obtain a product with the following characteristics: Figure 5 The TBC battery structure shown.

[0129] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can occur depending on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A solar cell, characterized by, The solar cell comprises: a silicon substrate (10); a P-type doped region (30) and an N-type doped region (20) arranged on a main surface of the silicon substrate (10); the N-type doped region (20) is arranged with a first tunneling oxide layer (21), a first N-type doped layer (22), a thermal insulation layer (24), and a second N-type doped layer (26) from inside to outside; the P-type doped region (30) is arranged with a second tunneling oxide layer (31) and a P-type doped layer (32) from inside to outside.

2. The solar cell according to claim 1, wherein a thickness of the first tunneling oxide layer (21) is 1-2 nm.

3. The solar cell according to claim 1, wherein a thickness of the thermal insulation layer (24) is 1-20 nm.

4. The solar cell according to claim 1, wherein a thickness of the first N-type doped layer (22) and the second N-type doped layer (26) is 80-200 nm.

5. The solar cell according to claim 1, wherein the N-type doped region (20) further comprises a third tunneling oxide layer (23), wherein the third tunneling oxide layer (23) is arranged between the first N-type doped layer (22) and the thermal insulation layer (24).

6. The solar cell according to claim 5, wherein a thickness of the third tunneling oxide layer (23) is 1-2 nm.

7. The solar cell according to claim 5, wherein the N-type doped region (20) further comprises a fourth tunneling oxide layer (25), wherein the fourth tunneling oxide layer (25) is arranged between the thermal insulation layer (24) and the second N-type doped layer (26).

8. The solar cell according to claim 7, wherein a thickness of the fourth tunneling oxide layer (25) is 1-2 nm.

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