Device for detecting optical pulse energy of laser and laser

Abstract

The utility model discloses a laser light pulse energy detection device and a laser, the laser light pulse energy detection device comprises an amplification circuit, an ADC module, an FPGA module and a clock module used for providing clock signals for the ADC module, the input end of the amplification circuit is electrically connected with a photoelectric conversion module; the output end of the amplifying circuit is electrically connected with the input end of the ADC module, the clock module is electrically connected with the ADC module, and the output end of the ADC module is electrically connected with the input end of the FPGA module. According to the utility model, the device for detecting the optical pulse energy of the laser is arranged inside the laser, so that the data such as the optical pulse energy and the pulse width of the laser can be precisely monitored through the device for detecting the optical pulse energy of the laser, and the working state of the laser can be adjusted in real time, so that the laser can obtain higher stability, and the average power of the laser can be counted.

Description

Technical Field

[0001] This utility model relates to the field of laser detection technology, and in particular to a device for detecting the energy of a laser pulse and a laser. Background Technology

[0002] As lasers are increasingly used in various industries, especially in the field of precision manufacturing, higher requirements are being placed on the laser's output stability, response speed, single-pulse energy stability, single-pulse pulse width stability, and the aesthetics and practicality of the human-machine interface.

[0003] Currently, in the industrial application of lasers, commercially available lasers face the problem of performance degradation of internal components over time, and inconsistent stability of single pulse and average power across different lifecycles of the laser. Utility Model Content

[0004] This invention aims to solve at least one of the technical problems existing in the prior art, and proposes a laser pulse energy detection device and a laser.

[0005] The technical solution of this utility model is implemented as follows: This utility model discloses a laser pulse energy detection device, including an amplifier circuit, an ADC module, a processor, and a clock module for providing a clock signal to the ADC module. The input terminal of the amplifier circuit is electrically connected to the photoelectric conversion module, the output terminal of the amplifier circuit is electrically connected to the input terminal of the ADC module, the clock module is electrically connected to the ADC module, and the output terminal of the ADC module is electrically connected to the input terminal of the processor.

[0006] Furthermore, the photoelectric conversion module includes a photoelectric sensor and an attenuator. The attenuator is used to attenuate the incident laser to obtain an attenuated optical signal. The photoelectric sensor is used to receive the attenuated optical signal and convert it into an electrical signal.

[0007] Furthermore, the ADC module is disposed on a first circuit board, and the processor is disposed on a second circuit board. The first circuit board is provided with a first connector, and the second circuit board is provided with a second connector. The first connector and the second connector are electrically connected, so that the first circuit board and the second circuit board are electrically connected. The first circuit board is provided with a photoelectric probe interface for connecting to the photoelectric conversion module.

[0008] The first circuit board and the second circuit board are also fixedly connected by bolts. The first circuit board and the second circuit board are arranged overlappingly.

[0009] Furthermore, the amplification circuit includes a first-stage amplification circuit and a second-stage amplification circuit. The input terminal of the first-stage amplification circuit is electrically connected to the photoelectric conversion module, the output terminal of the first-stage amplification circuit is electrically connected to the input terminal of the second-stage amplification circuit, and the output terminal of the second-stage amplification circuit is electrically connected to the first input terminal of the ADC module.

[0010] Furthermore, the first-stage amplifier circuit includes a buffer U9, an input terminal, a first output terminal, and a second output terminal. The input terminal of the buffer U9 is electrically connected to the input terminal of the first-stage amplifier circuit, the output terminal of the buffer U9 is electrically connected to the first output terminal of the amplifier circuit, and the second output terminal of the amplifier circuit is grounded through a resistor R123.

[0011] or / and,

[0012] The second-stage amplifier circuit includes amplifier U4, which has differential input and differential output. Amplifier U4 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of amplifier U4 is directly or electrically connected to the first output terminal of the first-stage amplifier circuit via resistor R15. The second input terminal of amplifier U4 is directly or electrically connected to the second output terminal of the first-stage amplifier circuit via resistor R18. The first output terminal of amplifier U4 is directly or electrically connected to the first input terminal of the ADC module via resistor R16. The second output terminal of amplifier U4 is directly or electrically connected to the second input terminal of the ADC module via resistor R19.

[0013] Furthermore, the first-stage amplifier circuit also includes operational amplifier U18. The non-inverting input terminal of operational amplifier U18 is electrically connected to the input terminal of the first-stage amplifier circuit via resistor R96. The non-inverting input terminal of operational amplifier U18 is grounded via resistor R122. The inverting input terminal of operational amplifier U18 is electrically connected to the output terminal of the buffer via resistor R98. The inverting input terminal of operational amplifier U18 is grounded via resistor R123. The output terminal of operational amplifier U18 is electrically connected to the auxiliary input pin IN_Aux of buffer U9.

[0014] or / and,

[0015] The input terminal of buffer U9 is electrically connected to one end of capacitor C26, and the other end of capacitor C26 is electrically connected directly or via a resistor to the input terminal of the first-stage amplifier circuit.

[0016] or / and,

[0017] The first-stage amplifier circuit also includes a sliding rheostat R124. The sliding end of the sliding rheostat R124 is electrically connected to one end of the resistor R123. One end of the sliding rheostat R124 is left floating, and the other end of the sliding rheostat R124 is grounded.

[0018] Furthermore, the output terminal of buffer U9 is electrically connected to one end of resistor R8, and the other end of resistor R8 is electrically connected to the first output terminal of the first stage amplifier circuit; the second output terminal of the first stage amplifier circuit is electrically connected to one end of resistor R56, and the other end of resistor R56 is electrically connected to one end of resistor R123, and the other end of resistor R123 is grounded.

[0019] Furthermore, the inverting input terminal of op-amp U18 is electrically connected to one end of capacitor C30, and the other end of capacitor C30 is electrically connected to the output terminal of op-amp U18.

[0020] Furthermore, the output terminal of operational amplifier U18 is electrically connected to one end of resistor R100, the other end of resistor R100 is electrically connected to one end of capacitor C29 and the auxiliary input pin IN_Aux of buffer U9, and the other end of capacitor C29 is grounded.

[0021] Furthermore, the bias input pin IN_Bias of buffer U9 is electrically connected to the input terminal of buffer U9 via resistor R65.

[0022] Furthermore, the first input terminal of amplifier U4 is electrically connected to one end of resistor R15 and one end of resistor R13, respectively. The other end of resistor R13 is electrically connected to the FB+ (positive feedback) pin of amplifier U4. The other end of resistor R15 is electrically connected to the first output terminal of the first stage amplifier circuit and one end of capacitor C24, respectively. The other end of capacitor C24 is electrically connected to one end of resistor R12, and the other end of resistor R12 is grounded.

[0023] Furthermore, the second input terminal of amplifier U4 is electrically connected to one end of resistor R18 and one end of resistor R121, respectively. The other end of resistor R21 is electrically connected to the FB- (negative feedback) pin of amplifier U4. The other end of resistor R18 is electrically connected to the second output terminal of the first stage amplifier circuit, one end of capacitor C25, and one end of capacitor C40, respectively. The other end of capacitor C25 is electrically connected to one end of resistor R23, and the other end of resistor R23 is grounded. The other end of capacitor C40 is electrically connected to one end of resistor R24, and the other end of resistor R24 ​​is grounded.

[0024] Furthermore, the laser pulse energy detection device of this invention also includes a display screen, which is electrically connected to the processor;

[0025] or,

[0026] It also includes an interface for connecting to a host computer or display screen, and a data transmission module is provided between the processor and the interface.

[0027] Furthermore, the processor employs an FPGA;

[0028] or / and,

[0029] The ADC module is a high-speed ADC module, the processor is a high-speed processor, and the clock module is a high-speed clock module.

[0030] This utility model also discloses a laser, in which a laser pulse energy detection device as described above is installed inside the laser.

[0031] Furthermore, the laser pulse energy detection device is installed on the laser cavity, and the entire laser unit adopts water cooling for heat dissipation.

[0032] This invention has at least the following beneficial effects: By installing a laser pulse energy detection device inside the laser, the laser's pulse energy, pulse width, and other data can be precisely monitored, allowing for real-time adjustment of the laser's operating state to achieve higher stability and the calculation of the laser's average power. The laser pulse energy detection device of this invention is used to detect single-pulse energy and can detect changes in optical signals with an equivalent frequency of 200MHz.

[0033] The ADC module of this invention is mounted on a first circuit board, and the processor is mounted on a second circuit board. The first circuit board has a first connector, and the second circuit board has a second connector. The first and second connectors are electrically connected, thus electrically connecting the first and second circuit boards. The first circuit board has a photoelectric probe interface for connection to the photoelectric conversion module. This invention provides a highly integrated laser pulse energy detection device, which can reduce the size of the laser pulse energy detection device and thus reduce the space occupied by the laser equipment cavity.

[0034] This invention employs a high-speed photodetector and a high-speed ADC, and uses a high-speed FPGA for data processing. The response time for single-pulse laser measurement is less than 10 ns, and the response time for the next pulse train adjustment is less than 1 μs, thereby improving the response speed. The photodetector and high-speed ADC possess high stability. This invention uses a high-speed FPGA for data processing to achieve rapid adjustment of the optical pulse.

[0035] This invention employs a high-stability photoelectric probe and ADC, and uses water-cooled heat dissipation for single-pulse measurement with a stability of ≤1%.

[0036] Water cooling is used to maintain a constant temperature and improve measurement accuracy: The laser pulse energy detection device of this invention is installed on the laser cavity, and the entire laser is kept at a constant temperature by water cooling to improve measurement accuracy.

[0037] This invention also includes an interface for connecting to a host computer or display screen, and a data transmission module is provided between the processor and the interface. The FPGA transmits data to the display screen or host computer via serial port, SPI, I2C, or other communication methods. The display screen or computer screen can display the single pulse energy and the power output of the laser. The human-machine interface is user-friendly, simple and beautiful, and provides a good user experience. Attached Figure Description

[0038] Figure 1 A schematic diagram of a laser pulse energy detection device provided in one embodiment of this utility model;

[0039] Figure 2 A circuit diagram of a laser pulse energy detection device provided in one embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the photoelectric conversion principle inside the photoelectric conversion module provided in one embodiment of this utility model;

[0041] Figure 4 A detailed circuit diagram of the first-stage amplifier circuit provided in one embodiment of this utility model;

[0042] Figure 5 A detailed circuit diagram of the second-stage amplifier circuit provided in one embodiment of this utility model;

[0043] Figure 6 A detailed circuit diagram of a data transmission module provided in one embodiment of this utility model;

[0044] Figure 7 A detailed circuit diagram of a clock module provided in one embodiment of this utility model. Detailed Implementation

[0045] To enable those skilled in the art to better understand the technical solution of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Unless otherwise defined, the technical or scientific terms used in this utility model shall have the ordinary meaning understood by one of ordinary skill in the art to which this utility model pertains. The terms "first," "second," and similar terms used in this utility model do not indicate any order, quantity, or importance, but are merely used to distinguish different components. In the description of this utility model, unless otherwise stated, "a plurality" or "several" means two or more. Similarly, "a," "one," or "the" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0047] In the various figures, the same elements are represented by similar reference numerals. For clarity, not all parts in the figures are drawn to scale. Furthermore, some well-known parts may not be shown in the figures.

[0048] Many specific details of this invention, such as the structure, materials, dimensions, processing techniques, and methods of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0049] See Figure 1 and Figure 2 This utility model discloses a laser pulse energy detection device, including an amplifier circuit, an ADC module, a processor, and a clock module for providing a clock signal to the ADC module. The input terminal of the amplifier circuit is electrically connected to the photoelectric conversion module, the output terminal of the amplifier circuit is electrically connected to the input terminal of the ADC module, the clock module is electrically connected to the ADC module, and the output terminal of the ADC module is electrically connected to the input terminal of the processor.

[0050] The ADC module and the processor can be set up separately or integrated into one unit.

[0051] Preferably, the processor is an FPGA.

[0052] Furthermore, the photoelectric conversion module includes a photoelectric sensor and an attenuator. The attenuator is used to attenuate the incident laser to obtain an attenuated optical signal. The photoelectric sensor is used to receive the attenuated optical signal and convert it into an electrical signal.

[0053] Furthermore, the ADC module is disposed on the first circuit board, the FPGA module is disposed on the second circuit board, the first circuit board is provided with a first connector, the second circuit board is provided with a second connector, the first connector and the second connector are electrically connected, so that the first circuit board and the second circuit board are electrically connected, and the first circuit board is provided with a photoelectric probe interface for connecting to the photoelectric conversion module.

[0054] The first circuit board and the second circuit board are also fixedly connected by bolts. The first circuit board and the second circuit board are arranged overlappingly.

[0055] In some embodiments, the photoelectric conversion module is provided with screw holes for easy fixing to the laser's output port. An attenuator is fixed to the light inlet of the housing. When the laser emits light, the laser beam strikes the attenuator, and after attenuation, a lower intensity light signal is obtained, which then enters the photoelectric sensor. After the signal is processed by the internal circuitry of the photoelectric conversion module, it is connected to the first circuit board via a BNC connector and then a BNC-SMA male-to-male connector.

[0056] A photoelectric sensor is a photoelectric probe, which is a sensor that converts light signals into electrical signals. It typically includes a photosensitive element (such as a photodiode or photomultiplier tube) and signal processing circuitry. When light shines on the photosensitive element, it generates a current or voltage signal, which is related to the intensity or other characteristics of the light. The pulsed laser detected by the photoelectric probe is a laser pulse that emits high energy in a very short time. It typically has a short pulse width and high peak power. Therefore, when using a photoelectric probe to detect light pulses, the probe's sensitivity, response time, and linearity must be considered. Because the pulse energy of the laser is very high, an attenuator needs to be added in front of the photoelectric probe to protect it and to test higher light power. Simultaneously, the optimal distance between the probe and the laser pulse must be determined to ensure signal quality. The internal photoelectric conversion principle diagram of the photoelectric conversion module is shown below. Figure 3 As shown.

[0057] Furthermore, the amplification circuit includes a first-stage amplification circuit and a second-stage amplification circuit. The input terminal of the first-stage amplification circuit is electrically connected to the photoelectric conversion module, the output terminal of the first-stage amplification circuit is electrically connected to the input terminal of the second-stage amplification circuit, and the output terminal of the second-stage amplification circuit is electrically connected to the first input terminal of the ADC module.

[0058] Optionally, the output of the first-stage amplifier circuit is electrically connected to the second input of the ADC module, and the output of the first-stage amplifier circuit directly enters the input of the ADC, which is a reserved path.

[0059] The first-stage amplifier circuit corresponds to Figure 2The Pre-Amplify circuit in the image amplifies the optical signal in one stage, thereby indirectly enabling the acquisition of pulsed laser signals. The Pre-Amplify circuit diagram is shown below. Figure 4 As shown.

[0060] The second-stage amplifier circuit corresponds to Figure 2 The Amplify circuit amplifies the signal while simultaneously adjusting the output impedance to match the input signal to the ADC. The ADC then acquires the corresponding electrical signal, indirectly achieving the acquisition of the pulsed laser signal. The Amplify circuit diagram is shown below. Figure 5 As shown.

[0061] In some embodiments, the first-stage amplifier circuit includes a buffer U9, an input terminal, a first output terminal, and a second output terminal. The input terminal of the buffer U9 is electrically connected to the input terminal of the first-stage amplifier circuit, the output terminal of the buffer U9 is electrically connected to the first output terminal of the amplifier circuit, and the second output terminal of the amplifier circuit is grounded through a resistor R123.

[0062] In some embodiments, the first-stage amplifier circuit includes an input terminal and two output terminals OUTQ_P1 and OUTQ_N1, and a buffer U9. The input terminal of the buffer U9 is electrically connected to one end of capacitor C26 and one end of resistor R65, respectively. The other end of resistor R65 is electrically connected to the bias input pin IN_Bias of the buffer U9. The other end of capacitor C26 is electrically connected to the input terminal of the first-stage amplifier circuit via resistor R54 and / or resistor R53. The output terminal of the buffer U9 is electrically connected to one end of resistor R8 and one end of resistor R98, respectively. The other end of resistor R8 is electrically connected to the first output terminal OUTQ_P1 of the first-stage amplifier circuit. The other end of resistor R98 is connected to one end of resistor R56, one end of resistor R123, the sliding terminal of the variable resistor R124, and the inverting pin of operational amplifier U18, respectively. The input terminals are electrically connected. The other end of resistor R56 is electrically connected to the second output terminal OUTQ_N1 of the first-stage amplifier circuit. The other end of resistor R123 is grounded. One end of the sliding rheostat R124 is left floating, and the other end of the sliding rheostat R124 is grounded. The non-inverting input terminal of operational amplifier U18 is electrically connected to one end of resistor R122 and one end of resistor R96, respectively. The other end of resistor R122 is grounded. The other end of resistor R96 is electrically connected to the first output terminal of the first-stage amplifier circuit. The output terminal of operational amplifier U18 is electrically connected to one end of resistor R100 and one end of capacitor C30, respectively. The other end of capacitor C30 is electrically connected to the inverting input terminal of operational amplifier U18. The other end of resistor R100 is electrically connected to one end of capacitor C29 and the auxiliary input pin IN_Aux of buffer U9, respectively. The other end of capacitor C29 is grounded.

[0063] The model of buffer U9 can be selected according to needs, and is not limited to... Figure 4The example shown.

[0064] The function of buffer U9 is to reduce signal distortion and improve signal quality. Operational amplifier U18 inputs the DC component of the input signal into the buffer, working in conjunction with buffer U9 to reduce signal distortion and improve signal quality. OUTQ_P1 and OUTQ_N1 are a set of differential inputs to the second-stage amplifier circuit.

[0065] Furthermore, the second-stage amplifier circuit includes amplifier U4, which has differential input and differential output. Amplifier U4 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of amplifier U4 is directly or electrically connected to the first output terminal OUTQ_P1 of the first-stage amplifier circuit via resistor R15. The second input terminal of amplifier U4 is directly or electrically connected to the second output terminal OUTQ_N1 of the first-stage amplifier circuit via resistor R18. The first output terminal of amplifier U4 is directly or electrically connected to the first input terminal of the ADC module via resistor R16. The second output terminal of amplifier U4 is directly or electrically connected to the second input terminal of the ADC module via resistor R19.

[0066] The first input terminal of amplifier U4 is electrically connected to one end of resistor R15 and one end of resistor R13. The other end of resistor R13 is electrically connected to the FB+ (positive feedback) pin of amplifier U4. The other end of resistor R15 is electrically connected to the first output terminal of the first stage amplifier circuit and one end of capacitor C24. The other end of capacitor C24 is electrically connected to one end of resistor R12. The other end of resistor R12 is grounded.

[0067] The second input terminal of amplifier U4 is electrically connected to one end of resistor R18 and one end of resistor R121, respectively. The other end of resistor R21 is electrically connected to the FB- (negative feedback) pin of amplifier U4. The other end of resistor R18 is electrically connected to the second output terminal of the first stage amplifier circuit, one end of capacitor C25, and one end of capacitor C40, respectively. The other end of capacitor C25 is electrically connected to one end of resistor R23, and the other end of resistor R23 is grounded. The other end of capacitor C40 is electrically connected to one end of resistor R24, and the other end of resistor R24 ​​is grounded.

[0068] Amplifier U4 has differential input and differential output. The model of amplifier U4 can be selected according to needs, and is not limited to... Figure 5 Examples disclosed in the embodiments.

[0069] Since a high-speed ADC converts a high-speed analog signal into a high-speed digital signal, a high-speed clock signal is required to acquire the high-speed signal. The clock frequency affects the sampling speed of the analog signal.

[0070] Because the laser pulse duration is extremely short, it is necessary to maximize the sampling speed of the high-speed ADC to achieve high-speed sampling. Therefore, a high-precision, high-speed clock signal is essential. The sampling speed of the high-speed ADC clock signal is 2.5 Gsps, thus requiring a high-speed RF clock with a frequency of 2.5 GHz. Simultaneously, the clock signal needs to be stable and reliable to improve the sampling accuracy and stability of the ADC.

[0071] High-speed RF clock module Figure 2 The RF_CLOCK parameter provides high-speed clock signals RFOUTP and RFOUTN to the ADC. The clock module circuit diagram is shown below. Figure 7 As shown.

[0072] According to Nyquist's sampling theorem, the sampling rate of an ADC must be at least twice the signal bandwidth. High-speed ADCs require sufficiently high sampling rates to acquire high-bandwidth input signals. A single pulse lasts approximately 5 ns, with a theoretical bandwidth of about 200 MHz. Therefore, a minimum high-speed ADC of 400 Mbps is required. However, to capture changes in single-pulse energy more frequently and acquire more details of the optical pulses, this module uses a 2.5 Gbps high-speed ADC, achieving an ultra-high sampling rate of 5 Gbps in interleaved mode. This module employs a 12-bit high-precision ADC to improve the accuracy of single-pulse energy detection.

[0073] As ADC sampling rates increase, interface technologies also evolve. Common interfaces include low-speed serial interfaces (such as I2C and SPI), parallel LVCMOS or LVDS interfaces, and the faster JESD204B serial interface. This module uses an LVDS interface, which offers advantages such as high speed, low power consumption, good noise characteristics, and low cost.

[0074] An external clock for the high-speed ADC provides a stable time base, ensuring accurate signal sampling during high-speed sampling. This module employs a frequency-adjustable high-speed RF clock to achieve sampling rates of 2.5 Gsps in non-interleaved mode and 5 Gsps in interleaved mode.

[0075] High-speed ADCs typically generate large amounts of data, especially at high sampling rates and high resolutions. High-speed FPGAs, with their powerful parallel computing capabilities and flexible logic resources, can effectively handle these massive data streams. Furthermore, high-speed FPGAs can achieve low-latency data processing, ensuring timely data processing in real-time applications.

[0076] The FPGA features a high-speed LVDS interface, allowing direct connection to a high-speed ADC. The LVDS parallel interface enables simultaneous processing of multiple data streams, improving system throughput.

[0077] Meanwhile, FPGAs can preprocess data using algorithms, such as noise reduction, filtering, and correction. After the data sampled by the high-speed ADC enters the FPGA, the FPGA can perform necessary front-end processing.

[0078] Furthermore, the ADC module is a high-speed ADC module.

[0079] Furthermore, the FPGA module is a high-speed FPGA module.

[0080] Furthermore, the clock module is a high-speed clock module.

[0081] In some embodiments, the high-speed ADC module uses ADI's AD9625-2500, which features high sampling rate, high linearity, high signal-to-noise ratio, wide input bandwidth, differential input, high-speed serial output, flexible digital output mode, and low noise spectral density. It can acquire signals from the photoelectric detection module and transmit high-speed, high-precision signals to the FPGA module for further processing.

[0082] In some embodiments, the high-speed clock module uses ADI's MAX2870, which features: a wide frequency range, low phase noise, high-performance PFD, multiple integrated VCOs, programmable output power, various output dividers, compatibility with 1.8V control logic, and a wide operating temperature range. The clock module's clock frequency is adjustable, providing a high-speed sampling clock for the ADC chip.

[0083] In some embodiments, the high-speed FPGA module uses the ALTERA CycloneIV EP4CE10F17C8N chip, which features low cost, low power consumption, high performance, flexibility, and broad protocol support. After the digital signal sampled by the high-speed ADC is transmitted to the high-speed FPGA, the FPGA performs filtering and other processing to improve the signal-to-noise ratio. It then calculates the laser's output power using an algorithm, ultimately displaying the laser's single-pulse energy and output power on a display screen or host computer. This invention calculates the average power of the laser and allows for flexible program configuration. Using the same module, it can detect the output power of lasers with different power levels, with a maximum detectable optical power of 200W.

[0084] In some embodiments, the laser pulse energy detection device of the present invention further includes a display screen, which is electrically connected to the FPGA module.

[0085] In other embodiments, the laser pulse energy detection device of this invention further includes an interface for connecting to a host computer or display screen, and a data transmission module is provided between the FPGA module and the interface. See the circuit diagram of the data transmission module. Figure 6 As shown.

[0086] FPGAs can process and compress high-speed data in real time, reducing data volume and improving transmission efficiency. Simultaneously, FPGAs support multiple communication interfaces (such as SPI, serial port, and I2C), enabling flexible data transmission and communication with other system components. This improves the compatibility of the single-pulse detection module and allows for flexible configuration within lasers with different interfaces, reducing the overall system complexity and cost.

[0087] The laser pulse energy detection device of this invention is designed to precisely monitor the laser pulse energy, pulse width, and other data, adjust the laser's operating state in real time to achieve higher stability, and calculate the laser's average power. By installing the laser pulse energy detection device inside the laser, the purpose is to monitor the laser pulse energy in real time and measure the laser output power.

[0088] The present invention will be further described in detail below with reference to the embodiments.

[0089] Measurement experimental conditions:

[0090] Example 1: Measurement of single-pulse energy. Same power meter, same light source, same power components, but different power levels.

[0091] Example 2: Measurement of optical power. Same power meter, same light source, same power components, but different power levels.

[0092] Example 1

[0093]

[0094] Example 2

[0095]

[0096]

[0097] This utility model embodiment also discloses a laser, in which a laser pulse energy detection device as described above is installed.

[0098] Furthermore, the laser pulse energy detection device is installed on the laser cavity, and the entire laser unit adopts water cooling for heat dissipation.

[0099] This invention involves installing a laser pulse energy detection device inside a laser. This device allows for precise monitoring of the laser's pulse energy, pulse width, and other data, enabling real-time adjustment of the laser's operating state to achieve higher stability and calculating the laser's average power. The laser pulse energy detection device of this invention is used to detect single-pulse energy and can detect changes in optical signals with an equivalent frequency of 200MHz.

[0100] The ADC module of this invention is mounted on a first circuit board, and the FPGA module is mounted on a second circuit board. The first circuit board has a first connector, and the second circuit board has a second connector. The first and second connectors are electrically connected, thus electrically connecting the first and second circuit boards. The first circuit board has a photoelectric probe interface for connection to the photoelectric conversion module. This invention provides a highly integrated laser pulse energy detection device, which can reduce the size of the laser pulse energy detection device and thus reduce the space occupied by the laser equipment cavity.

[0101] This invention employs a high-speed photodetector and a high-speed ADC, and uses a high-speed FPGA for data processing. The response time for single-pulse laser measurement is less than 10 ns, and the response time for the next pulse train adjustment is less than 1 μs, thereby improving the response speed. The photodetector and high-speed ADC possess high stability. This invention uses a high-speed FPGA for data processing to achieve rapid adjustment of the optical pulse.

[0102] This invention employs a high-stability photoelectric probe and ADC, and uses water-cooled heat dissipation for single-pulse measurement with a stability of ≤1%.

[0103] Water cooling is used to maintain a constant temperature and improve measurement accuracy: The laser pulse energy detection device of this invention is installed on the laser cavity, and the entire laser is kept at a constant temperature by water cooling to improve measurement accuracy.

[0104] This invention also includes an interface for connecting to a host computer or display screen, and a data transmission module is provided between the FPGA module and the interface. The FPGA transmits data to the display screen or host computer via serial port, SPI, I2C, or other communication methods. The display screen or computer screen can display the single-pulse energy and the power output of the laser. The human-machine interface is user-friendly, simple, and aesthetically pleasing, providing a good user experience. Of course, the FPGA module can also be directly electrically connected to the display screen.

[0105] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of this utility model, and the utility model is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of this utility model, and these modifications and improvements are also considered to be within the protection scope of this utility model.

Claims

1. A device for detecting the energy of a laser light pulse, characterized in that: It includes an amplifier circuit, an ADC module, a processor, and a clock module for providing a clock signal to the ADC module. The input terminal of the amplifier circuit is electrically connected to the photoelectric conversion module, the output terminal of the amplifier circuit is electrically connected to the input terminal of the ADC module, the clock module is electrically connected to the ADC module, and the output terminal of the ADC module is electrically connected to the input terminal of the processor.

2. The device for detecting the energy of laser light pulses according to claim 1, characterized in that: The photoelectric conversion module includes a photoelectric sensor and an attenuator. The attenuator is used to attenuate the incident laser to obtain an attenuated optical signal. The photoelectric sensor is used to receive the attenuated optical signal and convert it into an electrical signal.

3. The device for detecting the energy of laser light pulses according to claim 1, characterized in that: The ADC module is mounted on a first circuit board, and the processor is mounted on a second circuit board. The first circuit board has a first connector, and the second circuit board has a second connector. The first connector and the second connector are electrically connected, so that the first circuit board and the second circuit board are electrically connected. The first circuit board has a photoelectric probe interface for connecting to the photoelectric conversion module.

4. The laser pulse energy detection device according to claim 1, characterized in that: The amplifier circuit includes a first-stage amplifier circuit and a second-stage amplifier circuit. The input terminal of the first-stage amplifier circuit is electrically connected to the photoelectric conversion module, the output terminal of the first-stage amplifier circuit is electrically connected to the input terminal of the second-stage amplifier circuit, and the output terminal of the second-stage amplifier circuit is electrically connected to the first input terminal of the ADC module.

5. The device for detecting the energy of laser light pulses according to claim 4, characterized in that: The first-stage amplifier circuit includes a buffer U9, an input terminal, a first output terminal, and a second output terminal. The input terminal of the buffer U9 is electrically connected to the input terminal of the first-stage amplifier circuit, the output terminal of the buffer U9 is electrically connected to the first output terminal of the amplifier circuit, and the second output terminal of the amplifier circuit is grounded through a resistor R123. or / and, The second-stage amplifier circuit includes amplifier U4, which has differential input and differential output. Amplifier U4 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of amplifier U4 is directly or electrically connected to the first output terminal of the first-stage amplifier circuit via resistor R15. The second input terminal of amplifier U4 is directly or electrically connected to the second output terminal of the first-stage amplifier circuit via resistor R18. The first output terminal of amplifier U4 is directly or electrically connected to the first input terminal of the ADC module via resistor R16. The second output terminal of amplifier U4 is directly or electrically connected to the second input terminal of the ADC module via resistor R19.

6. The device for detecting the energy of laser light pulses according to claim 5, characterized in that: The first-stage amplifier circuit also includes operational amplifier U18. The non-inverting input terminal of operational amplifier U18 is electrically connected to the input terminal of the first-stage amplifier circuit via resistor R96. The non-inverting input terminal of operational amplifier U18 is grounded via resistor R122. The inverting input terminal of operational amplifier U18 is electrically connected to the output terminal of the buffer via resistor R98. The inverting input terminal of operational amplifier U18 is grounded via resistor R123. The output terminal of operational amplifier U18 is electrically connected to the auxiliary input pin IN_Aux of buffer U9. or / and, The input terminal of buffer U9 is electrically connected to one end of capacitor C26, and the other end of capacitor C26 is electrically connected directly or via a resistor to the input terminal of the first-stage amplifier circuit. or / and, The first-stage amplifier circuit also includes a sliding rheostat R124. The sliding end of the sliding rheostat R124 is electrically connected to one end of the resistor R123. One end of the sliding rheostat R124 is left floating, and the other end of the sliding rheostat R124 is grounded.

7. The apparatus for detecting the energy of laser light pulses according to claim 1, characterized in that: It also includes a display screen, which is electrically connected to the processor; or, It also includes an interface for connecting to a host computer or display screen, and a data transmission module is provided between the processor and the interface.

8. The device for detecting the energy of laser light pulses according to any one of claims 1 to 7, characterized in that: The processor uses an FPGA; or / and, The ADC module is a high-speed ADC module, the processor is a high-speed processor, and the clock module is a high-speed clock module.

9. A laser characterized by: The laser pulse energy detection device as described in any one of claims 1 to 8 is installed inside the laser.

10. The laser of claim 9, wherein: The laser pulse energy detection device is installed on the laser cavity, and the entire laser unit uses water cooling for heat dissipation.

Images