Interface conversion device and electronic equipment
By reconfiguring the idle pins of the interface connector, the interface conversion device is connected to the pins of the UFS device, realizing the communication connection between the UFS device and the central controller. This solves the problem of the UFS device not being pluggable, simplifies the user's replacement and expansion process, and reduces maintenance costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- LCFC HEFEI ELECTRONICS TECH
- Filing Date
- 2025-04-16
- Publication Date
- 2026-04-21
AI Technical Summary
The BGA packaging of UFS devices makes analysis difficult during the notebook R&D and testing phase, increases after-sales maintenance costs for customers and inconveniences for end users, and is also not conducive to plugging, unplugging and capacity expansion.
Design an interface conversion device that reconfigures the idle pins of the interface connector to connect them to the pins of the UFS device, thereby enabling communication between the central controller and the UFS device and supporting plug-in/plug-out operations.
This solves the problem of UFS devices not being pluggable, simplifies the process of user replacement and expansion, reduces maintenance costs, and improves user experience.
Smart Images
Figure CN224152967U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of memory card technology, and more particularly to an interface conversion device and an electronic device. Background Technology
[0002] UFS (Universal Flash Storage) is a storage system that encapsulates NAND flash memory and a flash controller protocol interface together. It is primarily used in consumer electronics products such as digital cameras and smartphones. However, because UFS is packaged in BGA (Ball Grid Array) and directly soldered onto the motherboard, it not only presents challenges for troubleshooting during the laptop R&D and testing phase but also hinders asynchronous verification and implementation. Furthermore, it increases after-sales maintenance costs for customers and inconveniences end-users due to the difficulty in plugging, unplugging, and upgrading. Therefore, resolving the pluggable / unpluggable issue between UFS and its interface is a crucial concern. Utility Model Content
[0003] This disclosure provides an interface conversion device and an electronic device to at least solve the above-mentioned technical problems existing in the prior art.
[0004] According to a first aspect of this disclosure, an interface conversion apparatus is provided, wherein the apparatus includes:
[0005] The interface slot has multiple electrical contacts;
[0006] An interface connector with multiple pins;
[0007] The plurality of electrical contacts make electrical contact with at least a portion of the plurality of pins to enable the interface conversion device to operate; the portion of the pins that make electrical contact with the electrical contacts are obtained by reconfiguring the idle pins of the interface connector; the interface conversion device in operation enables the central controller and the UFS device to communicate, and the UFS device is plugged into and plugged into the interface conversion device.
[0008] In one embodiment, the idle pins of the interface connector are reconfigured as differential signal pins, clock signal pins, reset pins, and ground pins.
[0009] In one possible implementation, the number of at least some pins is greater than or equal to 28.
[0010] In one possible implementation, the at least some pins include at least: 9 power supply pins, 9 ground pins, 8 differential signal pins, 1 clock signal pin, and 1 reset pin.
[0011] In one embodiment, the device further includes a UFS data channel and a PCIe data channel coupled to the interface connector, wherein the UFS data channel enables communication between the UFS device and the central controller, or the PCIe data channel enables communication between the SSD device and the central controller.
[0012] In one possible implementation, the UFS data channel is a two-channel system, and the PCIe data channel is a four-channel system.
[0013] In one possible implementation, the interface connector is an M2 connector.
[0014] In one embodiment, the device further includes a signal connection line for connecting the interface connector and the central controller.
[0015] In one embodiment, the length of the signal connection line is less than or equal to 5900 mils.
[0016] According to a second aspect of this disclosure, an electronic device is provided, including an interface conversion device as described in any of the foregoing embodiments.
[0017] This disclosure discloses an interface conversion device and an electronic device. The interface connector of this disclosure includes multiple idle pins. By reconfiguring these idle pins, the idle pins of the interface connector are given new definitions. Because the UFS device and the interface conversion device need to have pins with the same definitions to achieve a corresponding connection, the idle pins of the interface connector are redefined. With the new definitions, the idle pins can be connected to the pins of the UFS device, thereby enabling the central controller and the UFS device to communicate through the interface conversion device. At the same time, the UFS device and the interface conversion device can also achieve a pluggable connection, solving the problem of non-pluggable UFS devices in the prior art, which is more conducive to the replacement and expansion of end users.
[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0019] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which:
[0020] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
[0021] Figure 1 A top view of the interface conversion device provided in the embodiments of this disclosure;
[0022] Figure 2 A side view of the interface conversion device provided in an embodiment of this disclosure;
[0023] Figure 3 This is the circuit diagram for the interface connector;
[0024] Figure 4 This is a schematic diagram showing the connection between the interface conversion device and the central controller. Detailed Implementation
[0025] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0026] This disclosure provides an interface conversion device. Figure 1 This is a top view of the interface conversion device provided in the embodiments of this disclosure. Figure 2 A side view of the interface conversion device provided in the embodiments of this disclosure, such as... Figure 1 and Figure 2 As shown, the interface conversion device 10 includes:
[0027] Interface slot 11 has multiple electrical contacts 111;
[0028] An interface connector (not shown in the figure) has multiple pins;
[0029] The plurality of electrical contacts 111 make electrical contact with at least a portion of the plurality of pins to enable the interface conversion device 10 to operate. The portion of the pins that make electrical contact with the electrical contacts 111 are obtained by reconfiguring the idle pins of the interface connector. The interface conversion device 10 in operation enables the central controller and the UFS device to communicate with each other, and the UFS device is plugged into and plugged into the interface conversion device 10.
[0030] It should be noted that the central controller and UFS devices are independent of the interface conversion device.
[0031] Multiple electrical contacts 111 within the interface slot 11 are connected to multiple pins of the UFS device to enable communication between the UFS device and the interface conversion device. The electrical contacts 111 can be made of conductive metal.
[0032] When the interface conversion device 10 connects to the UFS device, it needs to understand the definition of each pin that needs to be connected on the UFS device, so that the corresponding pin definitions can also be set on the interface conversion device.
[0033] Table 1: Pins required for UFS device connection and their definitions.
[0034]
[0035]
[0036] Table 1 describes the multiple pins included in the UFS device. The information in the table indicates whether a connection is required, that is, whether the pin of the UFS device needs to be connected to the interface conversion device. If the pin needs to be connected, the corresponding pin needs to be set on the interface connector of the interface conversion device.
[0037] In one embodiment, the interface connector is an M2 connector. M2 connectors are generally used to connect SSD devices, so the original M2 connector does not include pins for connecting to UFS devices. In order for the interface conversion device to communicate with UFS devices, the M2 connector needs to define pins corresponding to the pins on the UFS device.
[0038] The interface connector includes multiple idle pins, which are referred to as NC (Not Connected) pins. In this disclosure, multiple idle pins are reconfigured to give them new definitions so that the central controller and the UFS device can communicate through the interface conversion device, and the UFS device and the interface conversion device can also be plugged and plugged in.
[0039] Figure 3 This is a circuit diagram for the interface connector. (Example) Figure 3 As shown, the interface connector contains multiple free pins, such as NC5, NC6 to NC22 in the figure.
[0040] In one embodiment, the idle pins of the interface connector are reconfigured as differential signal pins, clock signal pins, reset pins, and ground pins.
[0041] At least some of the pins have a number greater than or equal to 28.
[0042] At least some of the pins include: 9 power supply pins, 9 ground pins, 8 differential signal pins, 1 clock signal pin, and 1 reset pin.
[0043] Based on the information in Table 1 above, the differential signal pins correspond to the DIN0 (or DIN), DIN1, DOUT0 (or DOUT), and DOUT1 pins in Table 1; the clock signal pins correspond to the REF_CLK pins in Table 1; the reset pins correspond to the RST_n pins in Table 1; the ground pins (GND) correspond to the VSS pins in Table 1; and the power supply pins correspond to the VCC, VCCQ, and VCCQ2 pins in Table 1. For details, please refer to Table 2 below.
[0044] Table 2: Pin Correspondence between Interface Connectors and UFS Devices
[0045] UFS devices require pin names for interface. Interface connector corresponding pins Number of pins required VCC 3.3V / 1.8V ≥3 VCCQ 1.2V ≥3 VCCQ2 1.8V ≥3 VSS GND ≥4 RST_n Reset 1 REF_CLK clock signal 1 DIN0 Differential signal pairs 2 DIN1 Differential signal pairs 2 DOUT0 Differential signal pairs 2 DOUT1 Differential signal pairs 2 Differential signal pair requires GND Differential signal pairs require GND on both sides. ≥5
[0046] See Figure 3 The interface connector includes 9 power supply pins, 9 ground pins, and 19 unused pins, which can meet the pin requirements for connecting to UFS devices.
[0047] The power supply pins can be provided by the existing 3.3V pins in the interface connector. The 3.3V power supply pin can be directly reused from the existing 3.3V pin, but the 1.8V and 1.2V power supply pins require conversion using a low-dropout regulator (LDO) chip. Some ground pins are provided by the existing ground pins in the interface connector, while others are obtained by reconfiguring idle pins. Specifically, the ground pin corresponding to the VSS pin can be provided by the existing ground pin, and the ground pin corresponding to the GND required for the differential signal pair can be obtained by reconfiguring idle pins. The reset pin, clock signal pin, and differential signal pin are all obtained by reconfiguring idle pins.
[0048] Figure 4 This is a schematic diagram showing the connection between the interface conversion device and the central controller.
[0049] In one embodiment, the interface conversion device further includes a UFS data channel and a PCIe (Peripheral Component Interconnect express) data channel coupled to the interface connector, wherein the UFS data channel enables communication between the UFS device and the central controller, or the PCIe data channel enables communication between the SSD device and the central controller.
[0050] External devices that can be plugged into and plugged into the interface conversion device can be UFS devices or SSD devices. For example... Figure 4As shown, if the external device is a UFS device, select the UFS data channel, which is a two-lane UFS in the diagram. If the external device is an SSD device, select the PCIe data channel, which is a four-lane PCIe in the diagram.
[0051] If the external device is an SSD, the pins of the interface connector that connect to the external device will be switched to the original pins of the interface connector that correspond to the SSD device.
[0052] like Figure 3 As shown, the interface connector also includes a select pin (pin 69 in the figure). When the select pin is high, it corresponds to the SSD PCIe protocol; when the select pin is low, it corresponds to the SSD SATA protocol. In this disclosure, the select pin is generally high, meaning that when corresponding to an SSD device, the PCIe protocol is generally selected.
[0053] In one embodiment, the interface conversion device further includes a signal connection line for connecting the interface connector and the central controller.
[0054] The length of the signal connection cable should be less than or equal to 5900 mils to reduce signal transmission delay and interference.
[0055] The interface connector disclosed herein includes multiple idle pins. By reconfiguring these idle pins, the idle pins of the interface connector are redefined. These redefined idle pins can then be connected to the corresponding pins of the UFS device, enabling the central controller and the UFS device to communicate through the interface conversion device. At the same time, the UFS device and the interface conversion device can also be plugged in and out, solving the problem of non-pluggable UFS devices in the prior art, and making it easier for end users to replace and expand their devices.
[0056] This disclosure also provides an electronic device including an interface conversion device as described in any of the above embodiments.
[0057] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.
[0058] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.
[0059] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. An interface conversion device, characterized by, The device includes: The interface slot has multiple electrical contacts; An interface connector with multiple pins; The plurality of electrical contacts make electrical contact with at least a portion of the plurality of pins to enable the interface conversion device to operate. The portion of the pins that make electrical contact with the electrical contacts are obtained by reconfiguring the idle pins of the interface connector. The interface conversion device in operation enables the central controller and the Universal Flash Storage (UFS) device to communicate with each other, and the UFS device is plugged into and plugged into the interface conversion device.
2. The apparatus according to claim 1, characterized in that, The idle pins of the interface connector are reconfigured as differential signal pins, clock signal pins, reset pins, and ground pins.
3. The apparatus according to claim 1, characterized in that, The number of at least some of the pins is greater than or equal to 28.
4. The apparatus according to claim 2 or 3, characterized in that, The at least some of the pins include at least: 9 power supply pins, 9 ground pins, 8 differential signal pins, 1 clock signal pin, and 1 reset pin.
5. The apparatus of claim 1, wherein, The device further includes: The interface connector is coupled to a UFS data channel and a PCIe data channel for high-speed peripheral component interconnection. The UFS data channel enables communication between the UFS device and the central controller, or the PCIe data channel enables communication between the solid-state drive (SSD) device and the central controller.
6. The apparatus according to claim 5, characterized in that, The UFS data channel is a two-channel system, and the PCIe data channel is a four-channel system.
7. The apparatus according to claim 1, characterized in that, The interface connector is an M2 connector.
8. The apparatus of claim 1, wherein, The device further includes: A signal connection cable is used to connect the interface connector and the central controller.
9. The apparatus according to claim 8, characterized in that, The length of the signal connection line is less than or equal to 5900 mils.
10. An electronic device, comprising: Includes the interface conversion device as described in any one of claims 1-9.