Device for reducing peak voltage of three-level circuit
By setting a non-inductive absorption capacitor and an RC series absorption circuit in the three-level circuit, the problem of excessive switching peak voltage of MOSFETs is solved, thereby reducing the difficulty and cost of device selection and improving electromagnetic interference.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HEFEI KEWELL POWER SYST CO LTD
- Filing Date
- 2025-02-07
- Publication Date
- 2026-04-21
AI Technical Summary
In a three-level circuit, excessive switching spike voltages between MOSFETs can lead to difficulties in device selection, increased costs, and electromagnetic interference.
Non-inductive absorption capacitors are placed near the MOSFETs and diodes, and an RC series absorption circuit is set between the source and drain of each MOSFET to shorten the commutation path and discharge loop path.
It significantly reduces the switching peak voltage of the MOSFET, improves the electromagnetic compatibility performance of the system, and reduces the difficulty and cost of device selection.
Smart Images
Figure CN224154131U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of power electronics technology and relates to a device for reducing the peak voltage of a three-level circuit. Background Technology
[0002] As the requirements for inverter performance such as power density, efficiency, and output waveform quality gradually increase, the three-level topology inverter with neutral point clamped (NPC) has been widely used. Taking the NPC1 three-level circuit as an example, compared with the two-level inverter circuit, it adds a zero-level path. The three-level circuit output waveform has fewer harmonic components, the voltage waveform is closer to a sine wave, and it has a lower THD.
[0003] MOSFETs are frequently used in power control units to achieve voltage, current, and power conversion. If the circuit voltage, current, and power are low, a single MOSFET is sufficient. However, when the circuit current, voltage, and power are high, the current capacity or heat dissipation of a single MOSFET is insufficient. In three-level circuits, current technology typically uses multiple MOSFETs connected in parallel to meet the voltage, current, and power requirements. Considering the need for current sharing among the parallel MOSFETs, MOSFETs with similar functions are usually placed together. This increases the average spacing between MOSFETs in the three-level circuit, lengthening the commutation loop and switching spike absorption loop, resulting in excessive switching spike voltage between the source and drain of the MOSFET. This increases the maximum drain-source withstand voltage (V) of the MOSFET. dss The maximum operating voltage of the components and related devices is required to be high; if a higher voltage is selected... dss Using high-voltage MOSFETs and higher-voltage absorption devices can lead to selection difficulties and increased costs. In addition, excessively high switching voltage spikes can generate strong interference, affecting the normal operation of the device itself or other equipment. Utility Model Content
[0004] The technical solution of this utility model is used to solve the problem of how to reduce the switching spike voltage between the source and drain of a MOS transistor in a three-level circuit.
[0005] This utility model solves the above-mentioned technical problems through the following technical solution:
[0006] A device for reducing the peak voltage of a three-level circuit, applied to an NPC1 type three-level circuit, includes a PCB board and a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a first diode, a second diode, an RC series snubber circuit, a positive half-cycle snubber capacitor, and a negative half-cycle snubber capacitor disposed on the PCB board; the positive half-cycle snubber capacitor includes multiple first snubber capacitors connected in parallel, and the negative half-cycle snubber capacitor includes multiple second snubber capacitors connected in parallel.
[0007] The first MOSFET, the first diode, the second MOSFET, the third MOSFET, the fourth MOSFET, and the second diode are arranged linearly in sequence. Multiple first absorption capacitors are respectively arranged adjacent to the first MOSFET, the first diode, and the second MOSFET. Multiple second absorption capacitors are respectively arranged adjacent to the third MOSFET, the fourth MOSFET, and the second diode. An RC series absorption circuit is provided between the source and drain of each of the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET.
[0008] Furthermore, the first MOSFET, the second MOSFET, the third MOSFET, the fourth MOSFET, the first diode, the second diode, the first absorption capacitor, and the second absorption capacitor are all disposed on the front side of the PCB board, and the RC series absorption circuit is disposed on the back side of the PCB board.
[0009] Furthermore, the source of the first MOSFET is connected to the positive terminal of the power supply, serving as the positive bus terminal. The drain of the first MOSFET is connected to the source of the second MOSFET, the drain of the second MOSFET is connected to the source of the third MOSFET, the drain of the third MOSFET is connected to the source of the fourth MOSFET, and the drain of the fourth MOSFET is connected to the negative terminal of the power supply, serving as the negative bus terminal. The common connection point of the second and third MOSFETs serves as the AC output terminal.
[0010] Furthermore, one end of the positive half-cycle absorption capacitor is connected to the source of the first MOS transistor, the other end of the positive half-cycle absorption capacitor is connected to one end of the negative half-cycle absorption capacitor, the other end of the negative half-cycle absorption capacitor is connected to the drain of the fourth MOS transistor, and the common connection point of the positive half-cycle absorption capacitor and the negative half-cycle absorption capacitor serves as the neutral point.
[0011] Furthermore, the cutoff terminal of the first diode is connected to the source of the second MOSFET, the on terminal of the first diode is connected to the cutoff terminal of the second diode, the on terminal of the second diode is connected to the drain of the third MOSFET, and the common connection point of the first diode and the second diode is connected to the neutral point.
[0012] Furthermore, the source and drain of the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET are respectively connected to the two ends of an RC series snubber circuit, which includes a snubber resistor and a snubber capacitor connected in series.
[0013] Furthermore, the positive bus voltage at the positive bus terminal is +1 / 2VDC, and the negative bus voltage at the negative bus terminal is -1 / 2VDC.
[0014] Furthermore, both the first and second absorption capacitors are non-inductive absorption capacitors.
[0015] The advantages of this utility model are:
[0016] In this invention, non-inductive absorption capacitors are placed near each MOSFET and diode, shortening the commutation path length in the NPC1 type three-level circuit and reducing the stray inductance of the commutation path. Simultaneously, an RC series absorption circuit is placed near the source and drain of each MOSFET, shortening the discharge loop path and significantly reducing the peak voltage during switching. During commutation in the three-level circuit, since the long commutation loop does not pass through the diode, placing the MOSFETs nearby significantly shortens the long commutation path, further reducing the stray inductance of the commutation path, thereby reducing the peak voltage experienced by the switching devices. Because the switching peak voltage on the MOSFETs is reduced, the dv / dt of the devices during switching is significantly reduced, improving system electromagnetic interference and enhancing system electromagnetic compatibility performance. The selection voltage requirements for MOSFETs and their absorption devices are also reduced, thereby reducing the difficulty of device selection and equipment cost, and expanding the range of MOSFET options. Attached Figure Description
[0017] Figure 1 This is a top front view of a device for reducing the peak voltage of a three-level circuit according to Embodiment 1 of this utility model;
[0018] Figure 2 This is a schematic diagram of the back of a device for reducing the peak voltage of a three-level circuit according to Embodiment 1 of this utility model;
[0019] Figure 3 This is a circuit diagram of the three-level circuit according to Embodiment 1 of this utility model;
[0020] Figure 4 This is a schematic diagram of the operation of the three-level circuit in Embodiment 1 of this utility model;
[0021] Reference numerals in the attached diagram: 1. First MOSFET; 2. Second MOSFET; 3. Third MOSFET; 4. Fourth MOSFET; 5. First diode; 6. Second diode; 7. RC series snubber circuit; 8. First snubber capacitor; 9. Second snubber capacitor; 10. Positive half-cycle snubber capacitor; 11. Negative half-cycle snubber capacitor. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below in conjunction with the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0023] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments:
[0024] Example 1
[0025] like Figure 1-2 As shown, specifically, a device for reducing the peak voltage of a three-level circuit is disclosed, applied to an NPC1 type three-level circuit, including a PCB board and a first MOSFET 1, a second MOSFET 2, a third MOSFET 3, a fourth MOSFET 4, a first diode 5, a second diode 6, an RC series absorption circuit 7, a positive half-cycle absorption capacitor 10, and a negative half-cycle absorption capacitor 11 disposed on the PCB board; the positive half-cycle absorption capacitor 10 includes multiple first absorption capacitors 8 connected in parallel, and the negative half-cycle absorption capacitor 11 includes multiple second absorption capacitors 9 connected in parallel;
[0026] The first MOSFET 1, the first diode 5, the second MOSFET 2, the third MOSFET 3, the fourth MOSFET 4, and the second diode 6 are arranged linearly in sequence. Multiple first absorption capacitors 8 are respectively arranged adjacent to the first MOSFET 1, the first diode 5, and the second MOSFET 2. Multiple second absorption capacitors 9 are respectively arranged adjacent to the third MOSFET 3, the fourth MOSFET 4, and the second diode 6. An RC series absorption circuit 7 is provided between the source and drain of each of the first MOSFET 1, the second MOSFET 2, the third MOSFET 3, and the fourth MOSFET 4.
[0027] The above describes the arrangement of various components on the PCB board. To better understand the technical principles of this invention, the electrical connections between the components are described in detail below; in this embodiment, Figure 1-2 This embodiment integrates multiple NPC1 type three-level circuits on a PCB board, specifically two sets of MOSFETs connected in parallel on the NPC1 type three-level circuit. This embodiment takes a single NPC1 type three-level circuit as an example to explain the electrical connection relationship between the components.
[0028] The source of the first MOSFET 1 is connected to the positive terminal of the power supply, serving as the positive bus terminal, with the positive bus voltage denoted as +1 / 2VDC. The drain of the first MOSFET 1 is connected to the source of the second MOSFET 2. The drain of the second MOSFET 2 is connected to the source of the third MOSFET 3. The drain of the third MOSFET 3 is connected to the source of the fourth MOSFET 4. The drain of the fourth MOSFET 4 is connected to the negative terminal of the power supply, serving as the negative bus terminal, with the negative bus voltage denoted as -1 / 2VDC. The common connection point of the second MOSFET 2 and the third MOSFET 3 serves as the AC output terminal.
[0029] One end of the positive half-cycle absorption capacitor 10 is connected to the source of the first MOS transistor 1, the other end of the positive half-cycle absorption capacitor 10 is connected to one end of the negative half-cycle absorption capacitor 11, the other end of the negative half-cycle absorption capacitor 11 is connected to the drain of the fourth MOS transistor 4, and the common connection point of the positive half-cycle absorption capacitor 10 and the negative half-cycle absorption capacitor 11 is used as the neutral point.
[0030] The cutoff terminal of the first diode 5 is connected to the source of the second MOSFET 2, the on terminal of the first diode 5 is connected to the cutoff terminal of the second diode 6, the on terminal of the second diode 6 is connected to the drain of the third MOSFET 3, and the common connection point of the first diode 5 and the second diode 6 is connected to the neutral point.
[0031] The source and drain of the first MOSFET 1, the second MOSFET 2, the third MOSFET 3, and the fourth MOSFET 4 are respectively connected to the two ends of the RC series absorption circuit 7, which includes an absorption resistor and an absorption capacitor connected in series.
[0032] Furthermore, the first MOSFET 1, the second MOSFET 2, the third MOSFET 3, the fourth MOSFET 4, the first diode 5, the second diode 6, the first absorption capacitor 8, and the second absorption capacitor 9 are all disposed on the front side of the PCB board, and the RC series absorption circuit 7 is disposed on the back side of the PCB board.
[0033] Furthermore, both the first absorption capacitor 8 and the second absorption capacitor 9 are non-inductive absorption capacitors.
[0034] In this embodiment, a high-frequency absorption capacitor is placed near each MOSFET and diode, and an RC series absorption circuit 7 is placed near the source-drain of each MOSFET. The gate of the MOSFET is connected to an external drive circuit or controller, and the switching of the MOSFET is controlled by receiving an external control signal. Since the high-frequency absorption capacitor is very close to the MOSFET or diode, the current path is shorter, which shortens the length of the commutation path in the three-level circuit, reduces the stray inductance of the commutation path, and reduces the induced voltage ΔV, thereby reducing the peak voltage that the switching device is subjected to. In addition, the RC series absorption circuit 7 provides a discharge loop for the induced voltage generated during the MOSFET turn-off process. Since the RC series absorption circuit 7 is also very close to the MOSFET, the discharge loop path is also very short, which greatly reduces the peak voltage during the switching process.
[0035] like Figure 4 As shown, when the three-level circuit operates as a DC-to-AC inverter, the positive and negative levels cannot be switched directly; a 0 level must be passed in between. Figure 4 As shown in (a), current flows out from the positive level of the bus through the first MOSFET 1 and the second MOSFET 2. When the second MOSFET 2 is turned off, as... Figure 4 As shown in (b), the current flow direction and commutation path change, and the inverse conversion current loop is as follows: Figure 4 (b)~ Figure 4 As shown in (c), when the reverse conversion circuit is a long commutation circuit, the commutation does not pass through the second diode 5. The position layout of the third MOSFET 3 and the fourth MOSFET 4 according to this embodiment will shorten the long commutation path, which will reduce the stray inductance of the commutation path and thus reduce the peak voltage borne by the switching device.
[0036] Through the above technical solutions, non-inductive absorption capacitors are set near each MOSFET and diode in this utility model, shortening the length of the commutation path in the three-level circuit and reducing the stray inductance of the commutation path. At the same time, an RC series absorption circuit 7 is set near the source and drain of each MOSFET, shortening the discharge loop path and greatly reducing the peak voltage during the switching process. In addition, when the three-level circuit is in the commutation process, since the long commutation loop does not pass through the diode, placing the MOSFET near it can significantly shorten the long commutation path, further reducing the stray inductance of the commutation path, thereby reducing the peak voltage borne by the switching device. By reducing the switching peak voltage on the MOSFET, the dv / dt of the device during the switching process is greatly reduced, the electromagnetic interference of the system is improved, the electromagnetic compatibility performance of the system is also improved, and the selection voltage requirements of the MOSFET and its absorption device are also reduced, thereby reducing the difficulty of device selection and equipment cost.
[0037] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.
Claims
1. An apparatus for reducing peak voltage in a three-level circuit, comprising: The circuit is applied to the NPC1 type three-level circuit, including a PCB board and a first MOSFET (1), a second MOSFET (2), a third MOSFET (3), a fourth MOSFET (4), a first diode (5), a second diode (6), an RC series absorption circuit (7), a positive half-cycle absorption capacitor (10), and a negative half-cycle absorption capacitor (11) disposed on the PCB board; the positive half-cycle absorption capacitor (10) includes multiple first absorption capacitors (8) connected in parallel, and the negative half-cycle absorption capacitor (11) includes multiple second absorption capacitors (9) connected in parallel; The first MOSFET (1), the first diode (5), the second MOSFET (2), the third MOSFET (3), the fourth MOSFET (4), and the second diode (6) are arranged linearly in sequence. Multiple first absorption capacitors (8) are respectively arranged adjacent to the first MOSFET (1), the first diode (5), and the second MOSFET (2). Multiple second absorption capacitors (9) are respectively arranged adjacent to the third MOSFET (3), the fourth MOSFET (4), and the second diode (6). An RC series absorption circuit (7) is provided between the source and drain of the first MOSFET (1), the second MOSFET (2), the third MOSFET (3), and the fourth MOSFET (4).
2. The apparatus of claim 1, wherein, The first MOSFET (1), the second MOSFET (2), the third MOSFET (3), the fourth MOSFET (4), the first diode (5), the second diode (6), the first absorption capacitor (8), and the second absorption capacitor (9) are all located on the front side of the PCB board, and the RC series absorption circuit (7) is located on the back side of the PCB board.
3. The device for reducing peak voltage in a three-level circuit according to claim 1, characterized in that, The source of the first MOSFET (1) is connected to the positive terminal of the power supply, serving as the positive bus terminal. The drain of the first MOSFET (1) is connected to the source of the second MOSFET (2). The drain of the second MOSFET (2) is connected to the source of the third MOSFET (3). The drain of the third MOSFET (3) is connected to the source of the fourth MOSFET (4). The drain of the fourth MOSFET (4) is connected to the negative terminal of the power supply, serving as the negative bus terminal. The common connection point of the second MOSFET (2) and the third MOSFET (3) serves as the AC output terminal.
4. The apparatus of claim 3, wherein the voltage reduction circuit is a three-level circuit. One end of the positive half-cycle absorption capacitor (10) is connected to the source of the first MOS transistor (1), the other end of the positive half-cycle absorption capacitor (10) is connected to one end of the negative half-cycle absorption capacitor (11), the other end of the negative half-cycle absorption capacitor (11) is connected to the drain of the fourth MOS transistor (4), and the common connection point of the positive half-cycle absorption capacitor (10) and the negative half-cycle absorption capacitor (11) is used as the neutral point.
5. The apparatus of claim 4, wherein the voltage reduction circuit is a three-level circuit. The cutoff end of the first diode (5) is connected to the source of the second MOS transistor (2), the on end of the first diode (5) is connected to the cutoff end of the second diode (6), the on end of the second diode (6) is connected to the drain of the third MOS transistor (3), and the common connection point of the first diode (5) and the second diode (6) is connected to the neutral point.
6. The apparatus of claim 5, wherein, The source and drain of the first MOS transistor (1), the second MOS transistor (2), the third MOS transistor (3) and the fourth MOS transistor (4) are respectively connected to the two ends of the RC series absorption circuit (7), which includes an absorption resistor and an absorption capacitor connected in series.
7. The apparatus of claim 3, wherein the voltage reduction circuit is a three-level circuit. The positive bus voltage at the positive bus terminal is +1 / 2VDC, and the negative bus voltage at the negative bus terminal is -1 / 2VDC.
8. The apparatus of claim 1, wherein, Both the first absorption capacitor (8) and the second absorption capacitor (9) are non-inductive absorption capacitors.