Failure analysis test structure with positioning function and test chip

Abstract

The utility model discloses a failure analysis test structure with a positioning function, which comprises an upper metal layer, a lower metal layer and a through hole layer, and is characterized in that the through hole layer is used for connecting the upper metal layer and the lower metal layer; a plurality of upper-layer metal wires are arranged in the upper-layer metal layer, and a plurality of lower-layer metal wires are arranged in the lower-layer metal layer; a plurality of through holes are formed in the through hole layer and are respectively used for connecting the upper-layer metal wire and the lower-layer metal wire; the plurality of through holes comprise at least one target through hole, and at least two test pins are arranged on the upper layer metal wire and / or the lower layer metal wire connected with the target through hole; and positioning the position of the target through hole based on a positioning identifier arranged on at least one upper-layer metal wire. According to the mode, the positioning mark is arranged in the upper metal layer, so that failure analysis personnel can be helped to quickly position the position of the target through hole to be detected.

Description

Technical Field

[0001] This utility model relates to the field of failure analysis testing structure and test chip with positioning function. Background Technology

[0002] In semiconductor process development, process issues are identified through slicing and failure analysis of test cells. When slicing test cells, they need to be located first. A common method for location is to use an optical microscope with a certain magnification to locate them based on pattern features.

[0003] Currently, many test units are not designed with easy location in mind, making it difficult to quickly locate the fault in subsequent failure analysis. For example, a conventional four-terminal test unit for testing via resistance has a design that includes not only the via used for testing, but also other dummy vias and metal wires. It is difficult to locate the via used for testing when viewed from above.

[0004] Conventional test unit design such as Figure 1 As shown, PinV1, PinV2, PinI1, and PinI2 are four test pins used for failure testing of the test via; the top view of the failure analysis only shows the upper metal layer, i.e. Figure 1 Only the horizontally arranged metal lines (upper metal) are visible in the top view; the vias and the vertical metal lines (lower metal) are not visible. Therefore, it is difficult to quickly locate the test vias when viewed from above, which causes great inconvenience to the work of failure analysts. Utility Model Content

[0005] To solve the above-mentioned technical problems, this utility model provides a failure analysis test structure and test chip with positioning function, which is used to solve the problem of being unable to quickly locate the test via position.

[0006] Firstly, this embodiment provides a failure analysis test structure with positioning function, including an upper metal layer, a lower metal layer and a through-hole layer, wherein the through-hole layer is used to connect the upper metal layer and the lower metal layer;

[0007] The upper metal layer has multiple upper metal wires, and the lower metal layer has multiple lower metal wires; the through-hole layer has multiple through holes, which are used to connect the upper metal wires and the lower metal wires respectively.

[0008] The plurality of vias includes at least one target via, and at least two test pins are provided on the upper metal line and / or the lower metal line connected to the target via;

[0009] A positioning mark is provided on at least one of the upper metal lines to locate the position of the target through hole.

[0010] In some embodiments, the positioning marker includes a break in the upper metal wire.

[0011] In some embodiments, multiple breaks are provided, and at least one of the upper metal lines adjacent to the upper test metal line is provided.

[0012] The upper test metal line is the upper metal line that is connected to the target via and is provided with test pins.

[0013] In some embodiments, the break is located at the overlap between the upper metal wire and the lower metal wire.

[0014] In some embodiments, a plurality of the positioning markers are arranged around the target through-hole.

[0015] In some embodiments, the upper metal layer includes multiple virtual upper metal lines in addition to the upper test metal lines;

[0016] The lower metal layer includes multiple virtual lower metal lines in addition to the lower test metal line; wherein, the lower test metal line is the lower metal line connected to the target via and provided with test pins;

[0017] The via layer includes multiple virtual vias other than the target via;

[0018] The virtual vias are used to connect the virtual upper metal wire and the virtual lower metal wire, respectively; the virtual vias, the virtual upper metal wire, and the virtual lower metal wire are not connected to the target via.

[0019] In some of these embodiments, the upper metal lines in the upper metal layer extend along a first direction;

[0020] The lower metal wires in the lower metal layer are provided to extend along the second direction;

[0021] Wherein, the first direction and the second direction are perpendicular to each other.

[0022] In some of these embodiments, the upper metal lines in the upper metal layer extend along a first direction;

[0023] The lower metal wires in the lower metal layer extend along a first direction.

[0024] In some of these embodiments, the upper metal lines in the upper metal layer extend along a first direction and / or a second direction;

[0025] The lower metal wires in the lower metal layer extend along a first direction and / or a second direction;

[0026] Wherein, the first direction and the second direction are perpendicular to each other.

[0027] In some embodiments, the through-hole is filled with a conductive metal including at least one of copper, aluminum, copper alloys, and tungsten.

[0028] Secondly, this embodiment provides a test chip, including the failure analysis test structure with positioning function described in the first aspect above.

[0029] The beneficial effects of this utility model are: the failure analysis test structure with positioning function of this utility model can help failure analysts quickly locate the position of the target through hole to be tested by setting positioning marks in the upper metal layer.

[0030] The test chip of this utility model has the effective effect of the aforementioned failure analysis test structure with positioning function. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of a conventional test unit in existing technology;

[0032] Figure 2 This is a schematic diagram of a failure analysis test structure with positioning function according to this utility model. Detailed Implementation

[0033] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention.

[0034] Please see Figure 2 The optimized test structure design of this utility model shown provides a failure analysis test structure with positioning function, including an upper metal layer, a lower metal layer and a through-hole layer, wherein the through-hole layer is used to connect the upper metal layer and the lower metal layer;

[0035] The upper metal layer has multiple upper metal wires, and the lower metal layer has multiple lower metal wires; the via layer has multiple vias for connecting the upper metal wires and the lower metal wires respectively.

[0036] The plurality of vias includes at least one target via, and at least two test pins are provided on the upper metal line and / or the lower metal line connected to the target via;

[0037] A positioning mark is provided on at least one of the upper metal lines to locate the position of the target through hole.

[0038] Specifically, in this embodiment, four test pins, namely PinV1, PinV2, PinI1, and PinI2, are provided on the upper and lower metal lines connected to the target via, enabling Kelvin four-terminal testing. PinV1 and PinI2 are located on the lower metal line (lower metal) connected to the target via, while PinV2 and PinI1 are located on the upper metal line (upper metal) connected to the target via. However, in other embodiments, only two test pins may be provided for two-terminal resistance testing; one pin is located on the lower metal line connected to the target via, and the other is located on the upper metal line connected to the target via. Furthermore, in some embodiments, multiple target vias may be provided, and after the entire test path passes through multiple target vias, the two test pins leading to the test can be located at the ends of the upper metal line and the ends of the lower metal line, respectively. The number and location of the test pins can be set according to the specific application scenario, and this application does not impose specific limitations.

[0039] The failure analysis test structure with positioning function described in this embodiment can help failure analysts quickly locate the position of the target through hole by setting a positioning mark in the upper metal layer for quick positioning of the target through hole.

[0040] In this embodiment, the positioning marker is a break in the upper metal wire. For example... Figure 2 The optimized test structure shown has ports set on the upper metal graphic to break the upper metal at that point. Since the failure analysis topview can only see the upper metal graphic, the graphic features at the break point can help failure analysts quickly locate the target via.

[0041] In other embodiments, the positioning marker can also be formed in other ways to quickly help failure analysts locate the test via. For example, the positioning marker can be implemented by pre-setting a special size, special spacing, or special structure of the upper metal wire. Any positioning marker design that can quickly locate the target via is within the protection scope of this application. In this embodiment, multiple breaks are provided, and at least one is provided on the upper metal wire adjacent to the upper test metal wire; the upper test metal wire is the upper metal wire connected to the target via and provided with test pins.

[0042] The break is located at the intersection of the upper metal wire and the lower metal wire.

[0043] Multiple positioning markers are arranged around the target through-hole.

[0044] For specific details, please refer to Figure 2 Two breaks are set on each of the two upper-layer metal lines adjacent to the upper-layer test metal line, allowing the target via to be quickly located at the center of the four breaks. However, in other embodiments, the break positions can be set according to the application scenario. For example, two breaks can be set, one on each of the two upper-layer metal lines adjacent to the upper-layer test metal line, with the center of the line connecting the two breaks used for quick target via location. Depending on different application scenario requirements, more breaks can be set, and their positions can be chosen to quickly locate the target via; this application does not impose specific limitations. In this embodiment, the upper-layer metal layer includes multiple virtual upper-layer metal lines other than the upper-layer test metal line.

[0045] The lower metal layer includes multiple virtual lower metal lines in addition to the lower test metal line; wherein, the lower test metal line is the lower metal line connected to the target via and provided with test pins;

[0046] The via layer includes multiple virtual vias other than the target via;

[0047] The virtual vias are used to connect the virtual upper metal wire and the virtual lower metal wire, respectively; the virtual vias, the virtual upper metal wire, and the virtual lower metal wire are not connected to the target via.

[0048] Specifically, in the design of failure analysis test structures, in addition to a target via for testing, there are other dummy vias and dummy metals. For example, sometimes in order to avoid the test structure pattern becoming a lithographic defect hotspot pattern, it is necessary to fill some dummy vias around it to optimize the original layout design before tape-out.

[0049] The lithographic defect hotspot patterns mentioned here actually refer to lithographic patterns that conform to design rules but have poor actual process windows. Currently, the mainstream lithography processes used in integrated circuit production maintain a wavelength of 193nm. Without updating the wavelength of the exposure equipment, the size of the exposed pattern continues to shrink, resulting in many lithographic patterns that conform to design rules but have poor actual process windows. These are called lithographic defect hotspot patterns, generally referring to patterns or combinations of patterns in the layout that have certain geometric features and feature sizes within a certain range and are prone to causing lithographic defects. In this embodiment, refer to... Figure 2 The upper metal line in the upper metal layer extends along a first direction (lateral); the lower metal line in the lower metal layer extends along a second direction (longitudinal); wherein the first direction and the second direction are perpendicular to each other.

[0050] However, in other embodiments, the upper metal lines in the upper metal layer extend along a first direction (horizontal or vertical); the lower metal lines in the lower metal layer extend along the first direction (horizontal or vertical). That is, in some integrated circuit layouts, the metal lines in both metal layers can be arranged along the same horizontal (or vertical) direction.

[0051] In other embodiments, the upper metal lines in the upper metal layer extend along a first direction and / or a second direction; the lower metal lines in the lower metal layer extend along a first direction and / or a second direction; wherein the first direction and the second direction are perpendicular to each other. That is, in some integrated circuit layouts, the metal lines in these two metal layers can each have metal lines arranged along both the horizontal and vertical directions.

[0052] In this embodiment, the conductive metal filling the via includes at least one of copper, aluminum, and tungsten. Specifically, the via layer includes an interlayer dielectric, and the conductive via is formed within the interlayer dielectric. The material of the interlayer dielectric includes silicon oxide or silicon nitride. The failure analysis test structure with positioning function in this embodiment is suitable for test structures where the target vias are made of different materials.

[0053] Based on the same inventive concept, this application also provides a test chip that can help failure analysts quickly locate the position of a target via. The solution provided by this test chip is similar to the solution described in the failure analysis test structure with positioning function described above, and will not be repeated here.

[0054] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A failure analysis test structure with a positioning function, characterized in that, It includes an upper metal layer, a lower metal layer, and a via layer, wherein the via layer is used to connect the upper metal layer and the lower metal layer; The upper metal layer has multiple upper metal wires, and the lower metal layer has multiple lower metal wires; the through-hole layer has multiple through holes, which are used to connect the upper metal wires and the lower metal wires respectively. The plurality of vias includes at least one target via, and at least two test pins are provided on the upper metal line and / or the lower metal line connected to the target via; A positioning mark is provided on at least one of the upper metal lines to locate the position of the target through hole.

2. The failure analysis test structure with positioning function according to claim 1, characterized in that, The positioning marker includes a break in the upper metal wire.

3. The failure analysis test structure with positioning function according to claim 2, characterized in that, The break point is provided in multiple ways, and at least one of the upper metal lines is provided on the upper test metal line; The upper test metal line is the upper metal line that is connected to the target via and is provided with test pins.

4. The failure analysis test structure with positioning function according to claim 3, characterized in that, The break is located at the overlap between the upper metal wire and the lower metal wire.

5. A failure analysis test structure with positioning function according to claim 4, characterized in that, Multiple positioning markers are arranged around the target through-hole.

6. The failure analysis test structure with positioning function according to claim 3, characterized in that, The upper metal layer includes multiple virtual upper metal lines in addition to the upper test metal lines; The lower metal layer includes multiple virtual lower metal lines in addition to the lower test metal line; wherein, the lower test metal line is the lower metal line connected to the target via and provided with test pins; The via layer includes multiple virtual vias other than the target via; The virtual vias are used to connect the virtual upper metal wire and the virtual lower metal wire, respectively; the virtual vias, the virtual upper metal wire, and the virtual lower metal wire are not connected to the target via.

7. The failure analysis test structure with positioning function according to claim 1, characterized in that, The upper metal wires in the upper metal layer extend along a first direction; The lower metal wires in the lower metal layer are provided to extend along the second direction; Wherein, the first direction and the second direction are perpendicular to each other.

8. The failure analysis test structure with positioning function according to claim 1, characterized in that, The upper metal wires in the upper metal layer extend along a first direction; The lower metal wires in the lower metal layer extend along a first direction.

9. A failure analysis test structure with positioning function according to claim 1, characterized in that, The through-hole is filled with a conductive metal including at least one of copper, aluminum, copper alloys, and tungsten.

10. A test chip, characterized in that, The failure analysis test structure with positioning function as described in any one of claims 1 to 9 is included.

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