Hardware circuit control device for LED display screen of subway train

Abstract

The utility model discloses a hardware circuit control device for an LED display screen of a subway train, and belongs to the field of LED display screen control design. The device comprises an external communication interface module, a signal isolator, an MCU (Microprogrammed Control Unit) processor, an FPGA (Field Programmable Gate Array), an LED driving board interface and a power supply module, the external communication interface module receives a multi-protocol control signal, the multi-protocol control signal is transmitted to the MCU processor through the signal isolator, the MCU processor transmits data to the FPGA through the 32-bit parallel interface, the FPGA converts the data into serial row-column scanning data and drives the display screen through the LED driving board interface, and the power supply module supplies power to the system through the DC / DC converter. According to the device, through cooperative processing of the MCU and the FPGA, the high-resolution display data processing speed is increased, and the device has the advantages of being high in interference resistance, stable in operation and free of flicker smear and is suitable for a subway train passenger information display system.

Description

Technical Field

[0001] This application relates to the field of LED display control design, and in particular to a hardware circuit control device for an LED display screen on a subway train. Background Technology

[0002] With the rapid development of urban rail transit systems, subway trains, as an important public transportation tool, have seen their Passenger Information System (PIS) gradually become a core component in improving the passenger travel experience. Modern subway trains widely use LED displays inside and outside the carriages to display important information such as station announcements, emergency notices, and arrival information. These LED displays typically employ a red-green dual-color dot matrix design, offering high resolution and meeting the diverse display needs during train operation.

[0003] However, with the increasing resolution of LED displays, existing control board technologies face significant challenges in terms of data processing capabilities and display stability. Currently, subway train LED display systems often employ control boards based on MCU processors (microcontroller units). The MCU processor receives control signals through an external interface (such as RS485), processes the data, and outputs it to the LED driver board. However, this approach exhibits a significant performance bottleneck at high-resolution displays (such as 512x32 resolution). Due to the large data volume and high row and column scanning frequency, the MCU processor becomes overloaded, easily leading to display flickering or ghosting, thus affecting display quality and product performance. While some existing technologies attempt to address this issue by increasing processor performance or improving hardware architecture, these solutions still suffer from drawbacks such as high cost, high power consumption, and complex design.

[0004] Therefore, a new solution is needed to effectively improve the display stability of subway LED displays, especially at high resolutions, to avoid flickering and ghosting, and to have wider adaptability. Utility Model Content

[0005] This application provides a hardware circuit control device for an LED display screen on a subway train to improve the display stability of the LED display screen at high resolution and avoid flickering and ghosting. The technical solution is as follows:

[0006] This application provides a hardware circuit control device for an LED display screen on a subway train, the device comprising:

[0007] An external communication interface module is used to receive control signals from different communication protocols;

[0008] A signal isolator is used to transmit signals from the external communication interface module to the MCU processor;

[0009] The MCU processor is used to process the received data and transmit the processed data to the FPGA through a 32-bit parallel interface.

[0010] Field-programmable gate arrays (FPGAs) are used to receive data transmitted by MCU processors and convert it into serial row and column scan data;

[0011] The LED driver board interface is used to receive control signals from the FPGA and drive the LED display screen.

[0012] The power module is used to convert external power into voltages compatible with MCU processors and FPGAs.

[0013] Optionally, the external communication interface module includes an Ethernet interface, a LON communication interface, a CANBUS interface, and an RS485 interface.

[0014] Optionally, the Ethernet interface, the LON communication interface, the CANBUS interface, and the RS485 interface are all connected to the MCU processor through the signal isolator.

[0015] Optionally, the MCU processor is connected to the FPGA using a 32-bit parallel interface.

[0016] Optionally, the FPGA controls the LED display screen of the LED driver board interface through the control signals S_CLK, S_CP, SD_R, SD_G, SH0, SH1, and SH2.

[0017] Optionally, the FPGA includes a dual-port RAM (DPRAM) for storing LED display data.

[0018] Optionally, the power module includes a DC / DC power converter for converting the DC voltage input at the power interface and supplying it to the MCU processor and the FPGA.

[0019] Optionally, the DC / DC power converter is used to convert DC5V voltage to DC3.3V voltage.

[0020] Optionally, the DPRAM has a data input bit width of 32 bits and an output bit width of 256 bits, and the storage space of the DPRAM is the same as the number of LEDs on the LED display screen.

[0021] Optionally, the FPGA internally implements the display control logic for three LED displays, which are connected in parallel.

[0022] This utility model discloses a hardware circuit control device for an LED display screen on a subway train. Through the rational configuration of an MCU processor, FPGA, external communication interface, and power supply module, it achieves efficient and stable control of the LED display screen. The external communication interface module supports multiple communication protocols, ensuring broad system compatibility and flexibility, and adapting to the needs of different devices and systems. The introduction of a signal isolator ensures electrical isolation between external signals and the MCU processor, improving the system's anti-interference capability and stability. The MCU processor processes the received data and transmits it to the FPGA via a 32-bit parallel interface. The FPGA, through its parallel processing capabilities, quickly converts the data into serial row and column scanning signals, ensuring stable output of the high-resolution LED display. The FPGA also precisely controls the display content of the LED display screen by controlling the interface signals of the LED driver board, avoiding display stuttering or flickering. The power supply module converts external power into a voltage suitable for the MCU processor and FPGA through a DC / DC converter, ensuring stable operation and high efficiency of the entire device. This improves the display quality and reliability of the LED display screen on the subway train, meeting the high-performance requirements of modern train information display. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the hardware circuit control device for an LED display screen on a subway train provided in an illustrative embodiment of this application;

[0024] Figure 2 This is an illustrative embodiment of an FPGA logic diagram provided in this application;

[0025] Figure 3 This is a schematic diagram of a logic design for a dual-back DPRAM on an FPGA, provided in an illustrative embodiment of this application.

[0026] Figure 4 This is a schematic diagram of a DPRAM design provided in an illustrative embodiment of this application;

[0027] Figure 5 An illustration of an application where all data is 1 and all LEDs are lit.

[0028] Figure 6 This diagram illustrates an application example where all data is 0 and all LEDs are off. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0030] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0031] The main technical problem this invention aims to solve is how to improve the display stability of LED displays at high resolutions and avoid flickering and ghosting. Specifically, traditional MCU processor control schemes, when handling high-resolution displays, cannot meet the high-frequency refresh requirements due to limitations in serial data processing capabilities, resulting in poor display quality. Existing technologies use microcontrollers based on the ARM Cortex-M4 core to process data, but due to the large amount of data processing, the MCU processor often cannot update the displayed content in a timely manner, causing display problems.

[0032] Therefore, addressing the problems existing in the background technology, this utility model proposes a hardware circuit control device for a subway train LED display screen based on FPGA (Field Programmable Gate Array) design. By combining an MCU processor and an FPGA, this solution fully utilizes the parallel processing capabilities of the FPGA to improve the data processing speed of high-resolution displays, while also enabling communication and data processing with external devices through the MCU processor. This new solution not only solves the shortcomings of existing technologies but also provides higher scalability and stability in different application scenarios, meeting the needs of multiple fields such as subways, buses, and building advertising. Subway train passenger information display systems (PIS) and terminal station displays play a crucial role in modern urban transportation. These displays are typically used to show important train arrival information, emergency notices, and other content, ensuring passengers can obtain information promptly. However, with the continuous improvement of display resolution, existing LED display control technologies are gradually revealing performance bottlenecks, especially at high resolutions, such as 512x32 LED display screens. Traditional MCU processor-based control boards often cause flickering or ghosting phenomena when processing large amounts of serial data, affecting the display quality and stability of the product. The following describes these issues through various embodiments.

[0033] Example 1

[0034] like Figure 1 As shown, a hardware circuit control device for an LED display screen on a subway train is provided, the device comprising:

[0035] An external communication interface module is used to receive control signals from different communication protocols;

[0036] A signal isolator is used to transmit signals from the external communication interface module to the MCU processor;

[0037] The MCU processor is used to process the received data and transmit the processed data to the FPGA through a 32-bit parallel interface.

[0038] Field-programmable gate arrays (FPGAs) are used to receive data transmitted by MCU processors and convert it into serial row and column scan data;

[0039] The LED driver board interface is used to receive control signals from the FPGA and drive the LED display screen.

[0040] The power module is used to convert external power into voltages compatible with MCU processors and FPGAs.

[0041] The hardware control unit mainly consists of several modules. First, the external communication interface module includes an Ethernet interface, a LON communication interface, a CANBUS interface, and an RS485 interface. These interfaces are used to receive control signals from external devices. These signals are transmitted to the MCU processor through a signal isolator to ensure signal stability and security.

[0042] The MCU processor handles these signals and transmits the processed data to the FPGA via a 32-bit parallel interface. The FPGA receives this data and converts it into serial row and column scan data suitable for LED displays. The FPGA's parallel processing capabilities ensure stable and smooth high-resolution display effects.

[0043] The MCU processor and FPGA communicate via a 32-bit parallel interface, enabling efficient transmission of processed data to the FPGA for display control. The FPGA controls the LED array on the LED display screen via multiple control signals (such as S_CLK, S_CP, SD_R, SD_G, SH0, SH1, and SH2). The FPGA's parallel processing capabilities ensure smooth and stable display even on high-resolution LED screens.

[0044] The LED driver board interface is used to transmit control signals output from the FPGA to the LED driver board, thereby driving the LED array display. The power supply module is responsible for converting external power (such as DC power) into 5V and 3.3V voltages to power the MCU processor and FPGA.

[0045] This application employs an MCU+FPGA solution. The MCU selected is the NXP K64 series microcontroller chip MK64FN1M0VMD12, which is responsible for external data communication. Its external interfaces include isolated Ethernet, isolated LON communication, isolated CANBUS, and isolated RS485. The MCU receives external data, processes it, and converts it into display data, then serializes the data to the FPGA via a 32-bit high-speed parallel interface. The FPGA selected is the Intel CYCLONE iVE series FPGA chip EP4CE6F17I7, which receives LED display data output from the MCU via a 32-bit high-speed parallel interface and stores it in its internal dual-port DPRAM.

[0046] like Figure 2 The FPGA logic diagram shown illustrates that the FPGA's internal data processing and control logic reads the stored LED display data in real time via a 256-bit bus, converts the data into serial row and column scan data, and outputs it to the LED driver board to drive the LEDs to light up.

[0047] The external communication interface module features multiple standard communication interfaces (including Ethernet, LON communication, CANBUS, and RS485), which can flexibly adapt to the needs of different external devices. Each interface is connected to the MCU processor via a signal isolator, ensuring the isolation and electrical protection of communication signals and preventing external electrical interference from affecting system stability.

[0048] Furthermore, such as Figure 3 The diagram illustrates a logic design of a dual-port DPRAM for an FPGA. The FPGA includes a dual-port RAM (DPRAM) for storing LED display data.

[0049] The FPGA integrates a dual-port RAM (DPRAM) for caching and storing LED display data. This dual-port RAM design allows the FPGA to read and write data without conflicts, thus improving data transmission and processing speed. In this way, the FPGA can read and process LED display data in real time, ensuring that the high-resolution LED display can smoothly and flicker-free display the required content.

[0050] In one possible implementation, the FPGA internally implements a dual-output DPRAM for LED screen display data buffering. The DPRAM data input width is 32 bits, and the output width is 256 bits. The DPRAM storage space is the same as the number of LEDs on the LED screen. For example, if there are 256x32 LEDs on the LED screen, the DPRAM space is 256x32 (bits), with a data width of 256 bits and an address width of 32 bits, corresponding to 256 (columns) x 32 (rows) of LEDs. The corresponding data is 1 for an LED to be on and 0 for an LED to be off.

[0051] In one example, such as Figure 4 As shown, if the DPRAM output data width is 64 bits and the address is 16, it corresponds to 64 columns and 16 rows of LEDs on the LED board; in one example, such as Figure 5 The diagram shown illustrates an application example where all data points are 1 and all LEDs are lit; in one example, such as... Figure 6 The diagram shown illustrates an application example where all data is 0 and all LEDs are off.

[0052] Optionally, the power module includes a DC / DC power converter for converting the DC voltage input at the power interface and supplying it to the MCU processor and the FPGA.

[0053] The power module is responsible for converting externally input DC voltage (e.g., 12V) into 5V and 3.3V voltages via a DC / DC power converter, supplying power to the MCU processor and FPGA. This power module design ensures stable operation of all parts of the system under different voltage requirements and features overcurrent and overvoltage protection, ensuring the safety and stability of the entire device.

[0054] In addition, this application also provides extended application solutions, such as Figure 6 The diagram shows the control logic for the three LED screens. Optionally, the FPGA internally implements the control logic for the three LED screens, which are then connected in parallel. This allows for modification of the FPGA control logic to achieve different applications based on actual project needs. For example, by implementing the control logic for the three LED screens internally within the FPGA, one control board can simultaneously control the display of all three LED screens, enabling parallel display of the three LED screens.

[0055] Therefore, the hardware circuit control device for a subway train LED display screen of this application achieves efficient and stable LED display screen control through the reasonable configuration of the MCU processor, FPGA, external communication interface, and power supply module. The external communication interface module supports multiple communication protocols, ensuring broad system compatibility and flexibility, and adapting to the needs of different devices and systems. The introduction of a signal isolator ensures electrical isolation between external signals and the MCU processor, improving the system's anti-interference capability and stability. The MCU processor is responsible for processing the received data and transmitting it to the FPGA through a 32-bit parallel interface. The FPGA, through its parallel processing capabilities, quickly converts the data into serial row and column scanning signals, ensuring stable output of the high-resolution LED display. The FPGA also precisely controls the display content of the LED display screen by controlling the interface signals of the LED driver board, avoiding display stuttering or flickering. The power supply module converts external power into a voltage suitable for the MCU processor and FPGA through a DC / DC converter, ensuring stable operation and high efficiency of the entire device. This improves the display quality and reliability of the subway train LED display screen, meeting the high-performance requirements of modern train information display.

[0056] In addition, this application also provides the FPGA top-level source code corresponding to the device hardware design:

[0057] module fpga_top(

[0058] nRst, / / Input nReset signal

[0059] clk, / / Input Main Clock: 50MHz

[0060] / / ARM could read the key value from FPGA.

[0061] cs4, / / ARM - nCS4 signal

[0062] key, / / Input key switch

[0063] / / ARM could write LED Array datas to FPGA.

[0064] nWr, / / ARM - Local Bus Wr signal

[0065] cs, / / ARM - nCS0 signal

[0066] LA, / / ARM - Local Bus LA signal

[0067] LD, / / Inout: ARM - Local Bus LD signal

[0068] / / Output signals for Chip595.

[0069] ST_CK, / / Out: Chip595's STCP

[0070] SD_R1, / / Out: Chip595's DS

[0071] SCK_R1, / / Out: Chip595's SHCP

[0072] SD_R2, / / Out: Chip595's DS

[0073] SCK_R2, / / Out: Chip595's SHCP

[0074] SD_G1, / / Out: Chip595's DS

[0075] SCK_G1, / / Out: Chip595's SHCP

[0076] SD_G2, / / Out: Chip595's DS

[0077] SCK_G2, / / Out: Chip595's SHCP

[0078] / / Output signals for Chip138.

[0079] IN1_OE, / / Out: Chip138's / E1

[0080] IN1_H, / / Out: Chip138's ABC signal

[0081] LED / / Out: FPGA's RUN indication LED );

[0083] input nRst;

[0084] input clk;

[0085] input cs4;

[0086] input [ 7:0]key;

[0087] input nWr;

[0088] input cs;

[0089] input [ 8:0]LA;

[0090] inout [31:0]LD;

[0091] / / input [31:0]LD;

[0092] output ST_CK;

[0093] output SD_R1;

[0094] output SCK_R1;

[0095] output SD_R2;

[0096] output SCK_R2;

[0097] output SD_G1;

[0098] output SCK_G1;

[0099] output SD_G2;

[0100] output SCK_G2;

[0101] output IN1_OE;

[0102] output [ 2:0]IN1_H;

[0103] output LED;

[0104] / / wire adjust;

[0105] wire sclk;

[0106] wire shift;

[0107] wire Wr;

[0108] wire clk10m,clk50m,clk100m;

[0109] wire stcp_r1,stcp_r2;

[0110] wire hsoe_r1,hsoe_r2;

[0111] wire hsoe_t;

[0112] wire [ 4:0]rdaddr;

[0113] wire [ 31:0]LD_in;

[0114] wire [ 31:0]LData;

[0115] wire [255 :0]pdata_r2_low64;

[0116] wire [255 :0]pdata_r1_low64;

[0117] wire [255:0]ram_data;

[0118] / / reg [255:0]ram_data;

[0119] wire [255:0]pdata_r1,pdata_r2;

[0120] assign SCK_G1 = 1'b0;

[0121] assign SCK_G2 = SCK_R2;

[0122] / / assign SD_G1 = 1'b1;

[0123] / / assign SD_G2 = 1'b1;

[0124] assign ST_CK = stcp_r1&stcp_r2;

[0125] / / assign IN1_OE = adjust | shift;

[0126] / / assign IN1_OE = hsoe_t | shift;

[0127] assign pdata_r2_low64 = pdata_r2[255:0];

[0128] assign pdata_r1_low64 = pdata_r1[255:0];

[0129] assign shift = hsoe_r1 | hsoe_r2;

[0130] / / assign shift = hsoe_r1;

[0131] assign Wr = ~nWr;

[0132] / * Output: clk50m, clk10m, clk100m. * /

[0133] pll pll(

[0134] .inclk0 ( clk ),

[0135] .c0 ( clk50m ),

[0136] .c1 ( clk10m ),

[0137] .c2 ( clk100m ) );

[0139] tosy tosy(

[0140] .cs4 ( cs4 ),

[0141] .key ( key ),

[0142] .LD ( LD ),

[0143] .data ( LD_in ) );

[0145] lvc16244 lvc16244(

[0146] .EN ( cs ),

[0147] .A ( LD_in ),

[0148] / / .A ( LD ),

[0149] .Y ( LData ) );

[0151] reg wr_reg;

[0152] reg[31:0] LData_reg;

[0153] reg[8:0] LA_reg;

[0154] ram ram32x256(

[0155] .wren ( Wr ),

[0156] / / .wren ( 1'b1 ), / / grb test

[0157] .clock ( clk100m ),

[0158] .data ( LData ),

[0159] / / .data ( LData_test ), / / grb test

[0160] .rdaddress( rdaddr ),

[0161] .wraddress( LA ),

[0162] / / .wraddress( LA_test ), / / grb test

[0163] .q ( ram_data ) );

[0165] read_mem read_mem(

[0166] .clk ( clk100m ),

[0167] .nRst ( nRst ),

[0168] .shift ( shift ),

[0169] .data ( ram_data ),

[0170] .addr ( rdaddr ),

[0171] .data_r1 ( pdata_r1 ),

[0172] .data_r2 ( pdata_r2 ) );

[0174] clkgen clkgen(

[0175] .clk ( clk100m ),

[0176] .nRst ( nRst ),

[0177] .clkseries ( sclk ),

[0178] .sta_led ( LED ) );

[0180] par2ser par2ser_r1(

[0181] .SCLK ( sclk ),

[0182] .NRST ( nRst ),

[0183] .PDATA_R ( pdata_r1_low64),

[0184] .PDATA_G ( 64'h0 ),

[0185] .DS_R ( SD_R1 ),

[0186] .DS_G ( SD_G1 ),

[0187] .SHCP ( SCK_R1 ),

[0188] .STCP ( stcp_r1 ),

[0189] / / .stcp_r1 ( ),

[0190] .HSOE ( hsoe_r1 ),

[0191] .hsoe_t ( hsoe_t ) );

[0193] par2ser par2ser_r2(

[0194] .SCLK ( sclk ),

[0195] .NRST ( nRst ),

[0196] .PDATA_R ( pdata_r2_low64),

[0197] .PDATA_G ( 64'h0 ),

[0198] .DS_R ( SD_R2 ),

[0199] .DS_G ( SD_G2 ),

[0200] .SHCP ( SCK_R2 ),

[0201] .STCP ( stcp_r2 ),

[0202] .HSOE ( hsoe_r2 ),

[0203] .hsoe_t ( ) );

[0205] scanline scanline(

[0206] .nRst ( nRst ),

[0207] .shift ( shift ),

[0208] .HS_OE1 ( IN1_OE ),

[0209] .HS_OE2 ( ),

[0210] .IN1_H ( IN1_H ) );

[0212] On the other hand, a hardware circuit control method for an LED display screen on a subway train is provided, the method comprising:

[0213] Hardware design architecture that combines MCU processor and FPGA;

[0214] The MCU processor processes external data and generates the display data required for the LED display.

[0215] The FPGA receives the screen display data processed by the MCU processor and converts the screen display data into a format suitable for LED driver board control.

[0216] The MCU processor (e.g., NXP's K64 series chips) is responsible for communicating with external data sources, receiving and processing data from inside and outside the subway train, and converting the data into a format suitable for display. The FPGA (e.g., Intel's Cyclone series FPGA chips) receives this data and processes it into a serial data format suitable for LED displays. Data transmission between the MCU processor and the FPGA occurs via a high-speed parallel interface. The FPGA's internal data processing and control logic generates the serial data, driving the individual LED arrays on the display screen. This high parallel processing capability of the FPGA ensures stable display performance even on high-resolution LED displays.

[0217] Optionally, the FPGA is used for parallel data processing and provides high-frequency row and column scan control.

[0218] Among them, FPGAs can perform parallel processing on LED displays, especially when dealing with high-resolution LED displays (such as 512x32, 1024x64, etc.). FPGAs significantly improve data processing efficiency through parallel computing, eliminating the problem that a single MCU processor cannot meet the high-frequency row and column scanning requirements. The parallel data processing capability of FPGAs can ensure the refresh rate of high-resolution displays, avoid image flickering and ghosting, and improve the stability and visual effect of LED displays.

[0219] Optionally, the MCU processor is responsible for communicating with external data, receiving external data, processing the data, and converting it into display data for the LED display screen.

[0220] Optionally, the hardware design architecture also includes communication interfaces, including RS485, Ethernet, and CANBUS.

[0221] The system supports multiple communication interfaces, enabling a wider range of applications. For example, the RS485 interface can be used for data communication between different devices within a subway train; the Ethernet interface is suitable for applications with high data transmission requirements; and the CANBUS interface can be used in the control and data acquisition systems of subway systems. The introduction of these communication interfaces not only enhances the system's scalability but also ensures compatibility with various devices and communication protocols, guaranteeing the system's flexibility and applicability.

[0222] Optionally, the FPGA uses dual-port RAM (DPRAM) to store LED display data and reads the data in real time via a 256-bit bus.

[0223] The FPGA integrates a dual-port RAM (DPRAM) for caching and storing LED display data. The DPRAM has a 32-bit data input width and a 256-bit output width. Through a 256-bit bus, the FPGA can read the stored data in real time and perform row and column scanning control output to the LED driver board. The dual-port design of the DPRAM allows the FPGA to perform read and write operations simultaneously, greatly improving data processing speed and efficiency. This design solves the display stuttering or latency problems caused by insufficient data caching in traditional solutions.

[0224] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A hardware circuit control device for an LED display screen on a subway train, characterized in that, The device includes: An external communication interface module is used to receive control signals from different communication protocols; A signal isolator is used to transmit signals from the external communication interface module to the MCU processor; The MCU processor is used to process the received data and transmit the processed data to the FPGA through a 32-bit parallel interface. Field-programmable gate arrays (FPGAs) are used to receive data transmitted by MCU processors and convert it into serial row and column scan data; The LED driver board interface is used to receive control signals from the FPGA and drive the LED display screen. The power module is used to convert external power into voltages compatible with MCU processors and FPGAs.

2. The apparatus according to claim 1, characterized in that, The external communication interface module includes an Ethernet interface, a LON communication interface, a CANBUS interface, and an RS485 interface.

3. The apparatus according to claim 2, characterized in that, The Ethernet interface, the LON communication interface, the CANBUS interface, and the RS485 interface are all connected to the MCU processor through the signal isolator.

4. The apparatus according to claim 1, characterized in that, The MCU processor is connected to the FPGA via a 32-bit parallel interface.

5. The apparatus according to claim 1, characterized in that, The FPGA controls the LED display screen of the LED driver board interface through the control signals S_CLK, S_CP, SD_R, SD_G, SH0, SH1, and SH2.

6. The apparatus according to claim 1, characterized in that, The FPGA includes a dual-port RAM (DPRAM) for storing LED display data.

7. The apparatus according to claim 1, characterized in that, The power module includes a DC / DC power converter for converting the DC voltage input at the power interface and supplying it to the MCU processor and the FPGA.

8. The apparatus according to claim 7, characterized in that, The DC / DC power converter is used to convert DC5V voltage to DC3.3V voltage.

9. The apparatus according to claim 6, characterized in that, The DPRAM has a data input width of 32 bits and an output width of 256 bits. The storage space of the DPRAM is the same as the number of LEDs on the LED display screen.

10. The apparatus according to any one of claims 1 to 9, characterized in that, The FPGA internally implements the display control logic for three LED displays, which are connected in parallel.

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