Low-side switch driving control circuit, battery management system and control circuit thereof

Abstract

The utility model discloses a low-side switch driving control circuit, a battery management system and a control circuit of the low-side switch driving control circuit, and the low-side switch driving control circuit comprises a control chip, an analog signal processing chip and a driving control module, the second control end of the control chip is connected with the first input end of the drive control module, the output end of the analog signal processing chip is connected with the second input end of the drive control module, and the first output end of the drive control module is connected with the control end of a low-side drive switch of the battery discharge loop. The second output end of the driving control module is connected with the input end of the low-side driving switch; and the driving control module is used for controlling the connection between the first output end of the driving control module and the second output end of the driving control module according to a first driving signal sent by the control chip and a second driving signal sent by the analog signal processing chip, so that the low-side driving switch is kept in an off state before the self-inspection of the control chip is completed.

Description

Technical Field

[0001] This utility model relates to the field of battery technology, and in particular to a low-side switch drive control circuit and a battery management system and its control circuit. Background Technology

[0002] In existing battery discharge circuit low-side switch drive control circuits, an analog signal processing chip directly sends a drive signal to the low-side drive switch to control its conduction. The drawback of this circuit is that each time discharge is activated, the analog signal processing chip prepares and turns on the low-side drive switch. Then, after the control chip powers on, the initialization program turns the low-side drive switch off. Only after initialization and self-test are complete, and discharge is confirmed, is the low-side drive switch turned on again. During this process, there is a risk that the control chip may control the low-side drive switch to close before completing its self-test, leading to an accidental start of the battery discharge circuit and incomplete protection of the battery cell. This could potentially affect cell lifespan and product functionality. Summary of the Invention

[0003] This utility model provides a low-side switch drive control circuit and a battery management system and its control circuit to solve the problem in existing control circuits where the control chip controls the low-side drive switch before completing its self-test, causing the battery discharge circuit to discharge prematurely and reducing battery life.

[0004] In one embodiment, a low-side switch drive control circuit for a battery discharge circuit includes:

[0005] The system comprises a control chip, an analog signal processing chip, and a drive control module. The first control terminal of the control chip is electrically connected to the input terminal of the analog signal processing chip, the second control terminal of the control chip is electrically connected to the first input terminal of the drive control module, the output terminal of the analog signal processing chip is electrically connected to the second input terminal of the drive control module, the first output terminal of the drive control module is electrically connected to the control terminal of the low-side drive switch of the battery discharge circuit, and the second output terminal of the drive control module is electrically connected to the input terminal of the low-side drive switch.

[0006] The drive control module is used to control the connection between the first output terminal and the second output terminal of the drive control module according to the first drive signal sent by the control chip and the second drive signal sent by the analog signal processing chip, so as to keep the low-side drive switch in the off state before the control chip completes its self-test.

[0007] In one embodiment, the drive control module includes:

[0008] A first driving branch and a second driving branch, wherein the input terminal of the first driving branch is electrically connected to the output terminal of the analog signal processing chip, and the input terminal of the first driving branch serves as the second input terminal of the driving control module; the output terminal of the first driving branch serves as the first output terminal of the driving control module.

[0009] The input terminal of the second drive branch is electrically connected to the second control terminal of the control chip, and the input terminal of the second drive branch serves as the first input terminal of the drive control module; the output terminal of the second drive branch is electrically connected to the input terminal of the low-side drive switch, and the output terminal of the second drive branch serves as the second output terminal of the drive control module.

[0010] In one embodiment, the first driving branch includes:

[0011] The first resistor has its input terminal electrically connected to the output terminal of the analog signal processing chip, and its output terminal electrically connected to the control terminal of the low-side drive switch of the battery discharge circuit.

[0012] In one embodiment, the second driving branch includes:

[0013] A first switch and a second switch, wherein the control terminal of the first switch is used to acquire the transmitted second drive signal, the input terminal of the first switch is connected to the output terminal of the first resistor, the output terminal of the first switch is electrically connected to the input terminal of the low-side drive switch, and the output terminal of the first switch serves as the output terminal of the second drive branch.

[0014] The control terminal of the second switch is used to acquire the first drive signal sent by the control chip. The input terminal of the second switch is electrically connected to the control terminal of the first switch, and the output terminal of the second switch is electrically connected to the input terminal of the low-side drive switch.

[0015] In one embodiment, the second driving branch further includes:

[0016] The second resistor has its input terminal electrically connected to the output terminal of the analog signal processing chip, its output terminal electrically connected to the control terminal of the first switching transistor, and its output terminal electrically connected to the input terminal of the second switching transistor.

[0017] In one embodiment, the second driving branch further includes:

[0018] The third resistor has its input terminal electrically connected to the second control terminal of the control chip, and its output terminal connected to the control terminal of the second switching transistor.

[0019] In one embodiment, the second driving branch further includes:

[0020] A fourth resistor, the input terminal of which is connected to the output terminal of the third resistor, and the output terminal of which is electrically connected to the input terminal of the low-side drive switch.

[0021] In one embodiment, the control chip is used to send the first drive signal to the control terminal of the second switch during self-test to control the second switch to turn off, so that the control terminal of the first switch can obtain the second drive signal sent by the analog signal processing chip to control the first switch to turn on, thereby controlling the connection between the first output terminal and the second output terminal of the drive control module, so that the low-side drive switch remains in the off state.

[0022] In one embodiment, a control circuit for a battery management system includes a battery charging circuit and a low-side switch drive control circuit as described in any of the preceding embodiments.

[0023] In one embodiment, a battery management system includes the control circuit described in the preceding embodiments.

[0024] This utility model embodiment provides a low-side switch drive control circuit and a battery management system and its control circuit. By electrically connecting one input terminal of the drive control module to the control terminal of an analog signal processing chip, and another input terminal of the drive control module to the control terminal of the control chip, and further electrically connecting one output terminal of the drive control module to the control terminal of the low-side drive switch in the battery discharge circuit, and another output terminal of the drive control module to the input terminal of the low-side drive switch, the drive control module simultaneously controls the connection between the two output terminals based on a first drive signal sent by the control chip and a second drive signal sent by the analog signal processing chip. This keeps the low-side drive switch in an open state until the control chip completes its self-test, avoiding the problem in existing control circuits where the control chip controls the low-side drive switch before completing its self-test, causing premature discharge of the battery discharge circuit and reducing battery life. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1This is a low-side switch drive control circuit diagram of the battery discharge circuit in one embodiment of this utility model.

[0027] The labeling is explained as follows:

[0028] 10. Control chip; 20. Analog signal processing chip; 30. Drive control module; 40. Battery discharge circuit; 31. First drive branch; 32. Second drive branch. Detailed Implementation

[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0030] It should be understood that this invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this invention to those skilled in the art. In the drawings, for clarity, the dimensions of layers and regions, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] To fully understand this utility model, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this utility model. Preferred embodiments of this utility model are described in detail below; however, in addition to these detailed descriptions, this utility model may have other embodiments.

[0035] In one embodiment, such as Figure 1 As shown, a low-side switch drive control circuit for a battery discharge circuit includes:

[0036] The system comprises a control chip 10, an analog signal processing chip 20, and a drive control module 30. The first control terminal of the control chip 10 is electrically connected to the input terminal of the analog signal processing chip 20, the second control terminal of the control chip 10 is electrically connected to the first input terminal of the drive control module 30, the output terminal of the analog signal processing chip 20 is electrically connected to the second input terminal of the drive control module 30, the first output terminal of the drive control module 30 is electrically connected to the control terminal of the low-side drive switch DFET of the battery discharge circuit 40, and the second output terminal of the drive control module 30 is electrically connected to the input terminal of the low-side drive switch DFET.

[0037] The drive control module 30 is used to control the connection between the first output terminal and the second output terminal of the drive control module 30 according to the first drive signal sent by the control chip 10 and the second drive signal sent by the analog signal processing chip 20, so as to keep the low-side drive switch DFET in the off state before the control chip 10 completes its self-test.

[0038] The control process of the low-side switch drive control circuit includes:

[0039] The control chip 10 sends an activation signal to the analog signal processing chip 20 through the first control terminal. When the analog signal processing chip 20 is activated for charging, the analog signal processing chip 20 sends a second drive signal to the drive control module 30. The second drive signal is a high-level signal. At this time, the control chip 10 is in the self-test period, and the first drive signal sent to the drive control module 30 is a low-level signal. Therefore, the first output terminal and the second output terminal of the drive control module 30 are connected. The control terminal and the input terminal of the low-side drive switch DFET are at the same potential, so that the low-side drive switch DFET is kept in the off state and the battery discharge circuit 40 does not work.

[0040] After the control chip 10 completes its self-test, it sends a high-level first drive signal to the drive control module 30, which disconnects the first output terminal and the second output terminal of the drive control module 30. The control terminal of the low-side drive switch DFET receives the high-level signal output from the first output terminal of the drive control module 30. There is a potential difference between the control terminal and the input terminal of the low-side drive switch DFET, which turns on the low-side drive switch DFET, and the battery discharge circuit 40 starts discharging.

[0041] In this embodiment, the low-side switch drive control circuit electrically connects one input terminal of the drive control module 30 to the control terminal of the analog signal processing chip 20, and another input terminal of the drive control module 30 to the control terminal of the control chip 10. Furthermore, it electrically connects one output terminal of the drive control module 30 to the control terminal of the low-side drive switch DFET of the battery discharge circuit 40, and another output terminal of the drive control module 30 to the input terminal of the low-side drive switch DFET. This allows the drive control module 30 to simultaneously connect its two output terminals based on the first drive signal sent by the control chip 10 and the second drive signal sent by the analog signal processing chip 20. This keeps the low-side drive switch DFET in an open state until the control chip 10 completes its self-test, thus avoiding the problem in existing control circuits where the control chip 10 closes the low-side drive switch DFET before completing its self-test, causing the battery discharge circuit 40 to prematurely discharge and reducing battery life.

[0042] In one embodiment, such as Figure 1 As shown, the drive control module 30 includes:

[0043] A first driving branch 31 and a second driving branch 32 are provided. The input terminal of the first driving branch 31 is electrically connected to the output terminal of the analog signal processing chip 20. The input terminal of the first driving branch 31 serves as the second input terminal of the driving control module 30. The output terminal of the first driving branch 31 serves as the first output terminal of the driving control module 30.

[0044] The input terminal of the second drive branch 32 is electrically connected to the second control terminal of the control chip 10, and the input terminal of the second drive branch 32 serves as the first input terminal of the drive control module 30; the output terminal of the second drive branch 32 is electrically connected to the input terminal of the low-side drive switch DFET, and the output terminal of the second drive branch 32 serves as the second output terminal of the drive control module 30.

[0045] The first drive branch 31 is used to acquire the second drive signal sent by the analog signal processing chip 20; the second drive branch 32 is used to acquire the first drive signal sent by the control chip 10. The first drive signal is used to control the connection between the output terminal of the second drive branch 32 and the output terminal of the first drive branch 31. For example, when the control chip 10 is in self-test mode, the first drive signal acquired by the second drive branch 32 is a low-level signal, which controls the connection between the output terminal of the second drive branch 32 and the output terminal of the first drive branch 31. The control terminal and input terminal of the low-side drive switch DFET are at the same potential, keeping the low-side drive switch DFET in the off state, and the battery discharge circuit 40 does not work.

[0046] When the control chip 10 completes its self-test, the first drive signal acquired by the second drive branch 32 is a high-level signal, which disconnects the output terminal of the second drive branch 32 from the output terminal of the first drive branch 31. The first drive branch 31 outputs a high-level signal from its output terminal to the control terminal of the low-side drive switch DFET according to the acquired second drive signal. There is a potential difference between the control terminal and the input terminal of the low-side drive switch DFET, which turns on the low-side drive switch DFET, and the battery discharge circuit 40 starts discharging.

[0047] In one embodiment, such as Figure 1 As shown, the first drive branch 31 includes:

[0048] The first resistor R1 has its input terminal electrically connected to the output terminal of the analog signal processing chip 20, and its output terminal electrically connected to the control terminal of the low-side drive switch DFET of the battery discharge circuit 40.

[0049] The first resistor R1 is used to condition the voltage of the second drive signal input from the first drive branch 31 and output a high-level signal for controlling the control terminal of the low-side drive switch DFET.

[0050] In one embodiment, such as Figure 1 As shown, the second drive branch 32 includes:

[0051] A first switch Q1 and a second switch Q2 are used. The control terminal of the first switch Q1 is used to acquire the transmitted second drive signal. The input terminal of the first switch Q1 is connected to the output terminal of the first resistor R1. The output terminal of the first switch Q1 is electrically connected to the input terminal of the low-side drive switch DFET. The output terminal of the first switch Q1 serves as the output terminal of the second drive branch 32.

[0052] The control terminal of the second switch Q2 is used to acquire the first drive signal sent by the control chip 10. The input terminal of the second switch Q2 is electrically connected to the control terminal of the first switch Q1, and the output terminal of the second switch Q2 is electrically connected to the input terminal of the low-side drive switch DFET.

[0053] During the self-test period of the control chip 10, the control terminal of the second switch Q2 receives a low-level signal from the control chip 10, keeping the second switch Q2 in the off state. At the same time, the control terminal of the first switch Q1 receives a high-level signal from the analog signal processing chip 20, driving the first switch Q1 to turn on, connecting the output terminal of the first switch Q1 with the output terminal of the first resistor R1. This is equivalent to connecting the output terminal of the second drive branch 32 with the output terminal of the first drive branch 31. The control terminal and input terminal of the low-side drive switch DFET are at the same potential, keeping the low-side drive switch DFET in the off state, and the battery discharge circuit 40 does not work.

[0054] After the control chip 10 completes its self-test, the control terminal of the second switch Q2 receives a high-level signal from the first drive signal sent by the control chip 10, which turns on the second switch Q2. This is equivalent to connecting the control terminal and the output terminal of the first switch Q1, making the control terminal and the output terminal of the first switch Q1 at the same potential. Even if the control terminal of the first switch Q1 receives a second drive signal sent from the analog signal processing chip 20, the first switch Q1 cannot be turned on. This is equivalent to disconnecting the output terminal of the second drive branch 32 from the output terminal of the first drive branch 31. The first drive branch 31 outputs a high-level signal from its output terminal to the control terminal of the low-side drive switch DFET according to the acquired second drive signal. There is a potential difference between the control terminal and the input terminal of the low-side drive switch DFET, which turns on the low-side drive switch DFET, and the battery discharge circuit 40 starts discharging.

[0055] In one embodiment, such as Figure 1 As shown, the second drive branch 32 further includes:

[0056] The second resistor R2 has its input terminal electrically connected to the output terminal of the analog signal processing chip 20, its output terminal electrically connected to the control terminal of the first switch Q1, and its output terminal electrically connected to the input terminal of the second switch Q2.

[0057] The second resistor R2 is used to condition the voltage of the second drive signal input from the first drive branch 31 during the self-test of the control chip 10, output a high-level signal to the control terminal of the first switch Q1, drive the first switch Q1 to conduct, so as to connect the output terminal of the second drive branch 32 and the output terminal of the first drive branch 31. The control terminal and input terminal of the low-side drive switch DFET are at the same potential, so that the low-side drive switch DFET is kept in the off state and the battery discharge circuit 40 does not work.

[0058] In one embodiment, such as Figure 1 As shown, the second drive branch 32 further includes:

[0059] The third resistor R3 has its input terminal electrically connected to the second control terminal of the control chip 10, and its output terminal connected to the control terminal of the second switch Q2.

[0060] The third resistor R3 is used to condition the voltage of the first drive signal input from the second drive branch 32 after the control chip 10 completes its self-test, output a high-level signal to the control terminal of the second switch Q2, drive the second switch Q2 to conduct, connect the control terminal and output terminal of the first switch Q1, turn off the first switch Q1, and then disconnect the output terminal of the second drive branch 32 from the output terminal of the first drive branch 31. The low-side drive switch DFET is turned on, and the battery discharge circuit 40 starts discharging.

[0061] In one embodiment, such as Figure 1 As shown, the second drive branch 32 further includes:

[0062] The fourth resistor R4 is connected to the output of the third resistor R3, and the output of the fourth resistor R4 is electrically connected to the input of the low-side drive switch DFET.

[0063] In this process, when the control chip 10 adjusts the voltage of the first drive signal input from the second drive branch 32 after completing its self-test, the two ends of the fourth resistor R4 are connected in parallel to the control terminal and the output terminal of the second switch Q2. The fourth resistor R4 is connected in series with the third resistor R3, thus playing a voltage divider role.

[0064] In one embodiment, the control chip 10 is used to send the first drive signal to the control terminal of the second switch Q2 during self-test to control the second switch Q2 to turn off, so that the control terminal of the first switch Q1 receives the second drive signal sent by the analog signal processing chip 20 to control the first switch Q1 to turn on, thereby controlling the connection between the first output terminal and the second output terminal of the drive control module 30, so that the low-side drive switch DFET remains in the off state.

[0065] During the self-test, the first drive signal sent by the control chip 10 to the control terminal of the second switch Q2 is a low-level signal. The second switch Q2 is an N-type switch. When the signal received by the control terminal of the second switch Q2 is a low-level signal, the second switch Q2 is turned off.

[0066] In one embodiment, a control circuit for a battery management system includes a battery charging circuit and a low-side switch drive control circuit as described in any of the preceding embodiments.

[0067] The battery discharge circuit 40 includes a cell module, a positive discharge branch, and a negative discharge branch. One end of the positive discharge branch is connected to the positive terminal of the cell module, and the other end is connected to the positive terminal of the load. One end of the negative discharge branch is connected to the negative terminal of the cell module, and the other end is connected to the negative terminal of the load. A low-side drive switch (DFET) is connected in series on the negative discharge branch. When the control chip 10 completes its self-test, the control terminal of the low-side drive switch (DFET) receives a control signal (i.e., a high-level signal output from the first drive branch 31) from the drive control module 30. The DFET then conducts, initiating the discharge operation of the battery discharge circuit 40 on the load.

[0068] In one embodiment, a battery management system includes the control circuit described in the preceding embodiment. The battery management system may further include a signal acquisition module and a protection module electrically connected to the control chip 10. The signal acquisition module is used to acquire the discharge voltage and discharge current in the battery discharge circuit 40, and the protection module is used to determine whether there is an overvoltage based on the discharge voltage and whether there is an overcurrent based on the discharge current, and to trigger over-discharge protection.

[0069] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. A low-side switch drive control circuit for a battery discharge circuit, characterized in that, The low-side switch drive control circuit includes: The system comprises a control chip, an analog signal processing chip, and a drive control module. The first control terminal of the control chip is electrically connected to the input terminal of the analog signal processing chip, the second control terminal of the control chip is electrically connected to the first input terminal of the drive control module, the output terminal of the analog signal processing chip is electrically connected to the second input terminal of the drive control module, the first output terminal of the drive control module is electrically connected to the control terminal of the low-side drive switch of the battery discharge circuit, and the second output terminal of the drive control module is electrically connected to the input terminal of the low-side drive switch. The drive control module is used to control the connection between the first output terminal and the second output terminal of the drive control module according to the first drive signal sent by the control chip and the second drive signal sent by the analog signal processing chip, so as to keep the low-side drive switch in the off state before the control chip completes its self-test.

2. The low-side switch drive control circuit according to claim 1, characterized in that, The drive control module includes: A first driving branch and a second driving branch, wherein the input terminal of the first driving branch is electrically connected to the output terminal of the analog signal processing chip, and the input terminal of the first driving branch serves as the second input terminal of the driving control module; the output terminal of the first driving branch serves as the first output terminal of the driving control module. The input terminal of the second drive branch is electrically connected to the second control terminal of the control chip, and the input terminal of the second drive branch serves as the first input terminal of the drive control module; the output terminal of the second drive branch is electrically connected to the input terminal of the low-side drive switch, and the output terminal of the second drive branch serves as the second output terminal of the drive control module.

3. The low-side switch drive control circuit according to claim 2, characterized in that, The first driving branch includes: The first resistor has its input terminal electrically connected to the output terminal of the analog signal processing chip, and its output terminal electrically connected to the control terminal of the low-side drive switch of the battery discharge circuit.

4. The low-side switch drive control circuit according to claim 3, characterized in that, The second drive branch includes: A first switch and a second switch, wherein the control terminal of the first switch is used to acquire the transmitted second drive signal, the input terminal of the first switch is connected to the output terminal of the first resistor, the output terminal of the first switch is electrically connected to the input terminal of the low-side drive switch, and the output terminal of the first switch serves as the output terminal of the second drive branch. The control terminal of the second switch is used to acquire the first drive signal sent by the control chip. The input terminal of the second switch is electrically connected to the control terminal of the first switch, and the output terminal of the second switch is electrically connected to the input terminal of the low-side drive switch.

5. The low-side switch drive control circuit according to claim 4, characterized in that, The second drive branch also includes: The second resistor has its input terminal electrically connected to the output terminal of the analog signal processing chip, its output terminal electrically connected to the control terminal of the first switching transistor, and its output terminal electrically connected to the input terminal of the second switching transistor.

6. The low-side switch drive control circuit according to claim 5, characterized in that, The second drive branch also includes: The third resistor has its input terminal electrically connected to the second control terminal of the control chip, and its output terminal connected to the control terminal of the second switching transistor.

7. The low-side switch drive control circuit according to claim 6, characterized in that, The second drive branch also includes: A fourth resistor, the input terminal of which is connected to the output terminal of the third resistor, and the output terminal of which is electrically connected to the input terminal of the low-side drive switch.

8. The low-side switch drive control circuit according to claim 4, characterized in that, The control chip is used to send the first drive signal to the control terminal of the second switch during self-test to control the second switch to turn off, so that the control terminal of the first switch can obtain the second drive signal sent by the analog signal processing chip to control the first switch to turn on, thereby controlling the connection between the first output terminal and the second output terminal of the drive control module, so that the low-side drive switch remains in the off state.

9. A control circuit for a battery management system, characterized in that, It includes a battery charging circuit and a low-side switch drive control circuit according to any one of claims 1 to 8.

10. A battery management system, characterized in that, Includes the control circuit as described in claim 9.

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