Central domain controller of three-chip architecture
The central domain controller with a three-chip architecture solves the problems of system failure and architectural complexity caused by chip failure in existing technologies, achieves efficient function integration and reliability improvement, reduces costs and enhances compatibility and scalability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN KING LONG UNITED AUTOMOTIVE IND CO LTD
- Filing Date
- 2025-05-07
- Publication Date
- 2026-05-01
AI Technical Summary
Existing central domain controllers suffer from system failures due to chip malfunctions, electromagnetic interference, and increased heat density. Furthermore, their traditional architecture is complex, costly, and has poor compatibility.
It adopts a three-chip architecture, namely the vehicle electronic unit, the intelligent driving assistance unit, and the intelligent drive-by-wire chassis. They communicate through the SPI to CANFD circuit module or the vehicle CAN line. Each chip has a 32-bit automotive-grade microcontroller with dual-core lock-step function, which enables flexible configuration and redundancy backup of hardware and software.
It achieves efficient cross-domain function integration, reduces the number of controllers and wiring harnesses, improves reliability, compatibility and scalability, reduces costs, and enhances functional safety level and competitiveness.
Smart Images
Figure CN224190413U_ABST
Abstract
Description
A three-chip architecture central domain controller Technical Field
[0001] This utility model relates to the field of vehicle domain controller technology, specifically to a central domain controller with a three-chip architecture. Background Technology
[0002] To address the problems inherent in traditional vehicle electronic architectures, domain controllers were developed. They integrate multiple ECUs (Electronic Control Units) with related functions into a single controller, categorized by functional domains such as powertrain, chassis, body, intelligent driving, and intelligent cockpit. This integrated architecture reduces the number of ECUs, optimizes the vehicle's electronic and electrical wiring, lowers costs and overall vehicle weight, and simultaneously improves system scalability and reliability.
[0003] Existing central domain controllers mostly use a single multi-core chip to complete all calculations and executions. Once the chip fails, such as due to hardware damage, overheating, or electromagnetic interference, it may cause the entire central domain controller and even the related vehicle system to fail, affecting the vehicle's safety and reliability. Moreover, chips with more cores are usually more expensive.
[0004] In addition, there is another type of central domain controller that physically integrates various functional modules and places them into a central domain controller. Each module operates independently, and the coexistence of multiple modules leads to an increase in local heat density, requiring a customized heat dissipation solution. At the same time, the physical integration of different functional modules may cause electromagnetic interference. This architecture is complex and does not achieve complete integration.
[0005] Another approach is to use a single multi-core chip to perform all the calculations, while having multiple executors to execute them. Although this approach has the dual advantages of integrated computing power and execution flexibility, a single chip carrying multi-domain computing tasks may fail due to overheating, electromagnetic interference, or other issues, potentially triggering a chain reaction of failures in multiple executors. Summary of the Invention
[0006] The purpose of this invention is to provide a central domain controller with a three-chip architecture, which optimizes the system architecture and uses a multi-core processor to improve the computing power of the controller.
[0007] The present invention adopts the following technical solution:
[0008] A central domain controller with a three-chip architecture includes a first chip for controlling the vehicle's electronic units, a second chip for assisting intelligent driving, and a third chip for intelligent drive-by-wire chassis. The three chips communicate through an SPI-to-CANFD circuit module or directly through the vehicle's CAN bus.
[0009] Furthermore, the first chip also includes a 3-channel SPI interface. The first channel of the SPI interface is connected to a first EEPROM chip for data storage, the second channel is connected to a FLASH chip for program upgrades, and the third channel is connected to the SPI-to-CANFD circuit module for communication.
[0010] Furthermore, the first chip also includes an eT0ETC module and an eT1ETC module for PWM signal output, several GPIO interfaces for controlling the opening and closing of various relays and signal feedback, an ADC data acquisition interface, and a CAN interface for connecting to the vehicle network.
[0011] Furthermore, the second chip also includes a 3-channel SPI interface. The first channel of the SPI interface is connected to an SPI-to-CANFD circuit module for communication, the second channel is connected to a second EEPROM chip for data storage, and the third channel is connected to a FLASH chip for program upgrades.
[0012] Furthermore, the second chip also includes a CANFD interface and a reserved SPI-to-CANFD interface for increasing CANFD output resources.
[0013] Furthermore, the third chip also includes three SPI interfaces. The first SPI interface is connected to an SPI-to-CANFD circuit module for communication, the second is connected to a third EEPROM chip for data storage, and the third is connected to a FLASH chip for program upgrades.
[0014] Furthermore, the third chip also includes an in-vehicle Ethernet interface, a CANFD interface, an eMIOS0_G_CH module for signal acquisition, a GPIO interface, an ADC data acquisition interface for analog signal input detection, a reserved SPI to CANFD circuit module, and an SPI communication interface.
[0015] Furthermore, the SPI to CANFD circuit module also has an external interface for real-time monitoring via a CAN card device.
[0016] Furthermore, all three chips are 32-bit automotive-grade microcontroller chips with dual-core lockstep functionality.
[0017] As can be seen from the above description of the structure of this utility model, compared with the prior art, this utility model has the following advantages:
[0018] 1. This utility model is a central domain controller using a three-chip architecture. It uses three main chips to complete various functions and can be flexibly configured. Compared with the existing technology, this integrated architecture solves the problem of fragmented computing power in traditional architectures. Structurally, it does not have a multi-layer structure and necessary heat dissipation devices, and achieves efficient integration of cross-domain functions. It can realize the high integration of multiple controllers in traditional vehicles, reduce the number of vehicle controllers and the number and length of wiring harnesses, and has higher software and hardware integration, stronger compatibility, stronger scalability, and higher reliability. It also reserves space for subsequent product upgrades and iterations, and improves product scalability.
[0019] 2. Both the hardware and software of this utility model can be flexibly configured. Compared with the existing technology, different resources can be selected and used according to different vehicle needs, thereby matching the development of various types of vehicles, maximizing compatibility with the development requirements of various platforms, improving competitiveness, and enhancing differentiated advantages.
[0020] 3. The chips of this utility model can be mutually redundant and backed up, and various functional circuit resources can be configured to achieve mutual redundancy and backup, thereby improving the functional safety level and reliability. Attached Figure Description
[0021] Figure 1 is a schematic diagram of the three-chip architecture of this utility model.
[0022] Figure 2 is a schematic diagram of the structure of the first chip of this utility model.
[0023] Figure 3 is a schematic diagram of the structure of the second chip of this utility model.
[0024] Figure 4 is a schematic diagram of the structure of the third chip of this utility model.
[0025] Figure 5 is a schematic diagram of the program upgrade structure of this utility model.
[0026] The components in the diagram are labeled as follows: first chip 10, second chip 20, third chip 30, external interface 40, and program upgrade sequence allocation module 50. Detailed Implementation
[0027] The specific implementation of the present invention will now be described with reference to the accompanying drawings.
[0028] Referring to Figure 1, a three-chip architecture central domain controller includes a first chip 10 for controlling the vehicle's electronic units, a second chip 20 for assisting intelligent driving, and a third chip 30 for intelligent drive-by-wire chassis. The three chips communicate through an SPI to CANFD circuit module or directly through the vehicle's CAN bus.
[0029] Referring to Figures 1 and 2, the first chip 10 also includes three SPI interfaces, wherein the first SPI interface is connected to two first EEPROM chips for data storage; the second SPI interface is connected to a FLASH chip for program upgrade; and the third SPI interface is connected to an SPI-to-CANFD circuit module for communication between the three types of chips.
[0030] The first chip 10 also includes an eT0ETC module and an eT1ETC module for PWM signal output, with a total of 12 channels for 12 PWM signal outputs, of which 2 channels can be selected to be output by the third main chip by configuring a 0-ohm resistor.
[0031] The first chip 10 also includes 58 GPIO interfaces for controlling various relay opening and closing and various signal feedback, including 10 high-side drive outputs, 11 low-side drive outputs, 27 active high-signal inputs and 10 active low-signal inputs. Among them, 5 high-side drive outputs and 5 low-side drive outputs can be selected to be output by the third main chip by configuring a 0-ohm resistor, and 5 active high-signal inputs and 5 active low-signal inputs can also be detected by the third main chip at the same time.
[0032] The first chip 10 also includes 16 ADC data acquisition interfaces, of which 7 are used for tri-state signal input detection, and the other 9 can be selected to detect 5V analog signal input by configuring a 0-ohm resistor.
[0033] The first chip 10 also includes three CAN interfaces, which connect to the vehicle's TCAN, HCAN, and ICAN networks. TCAN and HCAN are also connected to the second chip 20 and the third chip 30 simultaneously to facilitate the receiving and sending of data. At the same time, TCAN and HCAN can also serve as communication channels between the three chips.
[0034] Referring to Figures 1 and 3, the second chip 20 also includes three SPI interfaces, wherein the first SPI interface is connected to an SPI-to-CANFD circuit module for communication; the second SPI interface is connected to a second EEPROM chip for data storage; and the third SPI interface is connected to a FLASH chip for program upgrades.
[0035] The second chip 20 also includes 4 CANFD interfaces for connecting radar, cameras and other CAN bus networks; it also includes a reserved 3-channel SPI to CANFD circuit module to increase CANFD interface output resources.
[0036] Referring to Figures 1 and 4, the third chip 30 also includes three SPI interfaces, wherein the first SPI interface is connected to an SPI-to-CANFD circuit module for communication; the second SPI interface is connected to a third EEPROM chip for data storage; and the third SPI interface is connected to a FLASH chip for program upgrades.
[0037] The third chip 30 also includes a 100Mbit / s automotive Ethernet interface for transmitting large amounts of data.
[0038] The third chip 30 also includes four CANFD interfaces for connecting to other CAN bus networks in the vehicle. It can be flexibly configured with hardware to interconnect with the four CANFD interfaces of the second chip 20, and can be freely combined according to actual application requirements.
[0039] The third chip 30 also includes an eMIOS0_G_CH module for signal acquisition, which supports 4-channel 5V PWM signal input and 2-channel PWM signal output.
[0040] The third chip 30 also includes 20 GPIO interfaces, including 5 high-side drive outputs, 5 low-side drive outputs, 5 active high-level digital inputs, and 5 active low-level digital inputs.
[0041] The third chip 30 also includes a 4-channel ADC data acquisition interface for 5V analog signal input detection.
[0042] The third chip 30 also includes a reserved 1-channel SPI to CANFD circuit module and a 1-channel SPI communication interface.
[0043] Referring to Figures 1 and 5, the SPI-to-CANFD circuit module, which enables direct communication between the first chip 10, the second chip 20, and the third chip 30, also exposes an external interface 40. This interface allows for real-time monitoring via a CAN card device. Furthermore, the three chips undergo program upgrades using the same FLASH chip. The FLASH chip controls the program upgrade sequence allocation module 50. During program upgrades, the program to be upgraded is first written into the FLASH chip via the CAN bus or Ethernet. Then, the three chips sequentially read the upgrade program to complete the chip program upgrade. Simultaneously, the central domain controller of the three-chip architecture also features two 12V / 1A power outputs to power the equipment. The central domain controller of the three-chip architecture boasts abundant hardware resources, meeting the development needs of various vehicle types.
[0044] In addition, all three chips are 32-bit automotive-grade microcontrollers with dual-core lockstep functionality. The first chip 10 uses a PowerPC architecture and integrates a 16MHz crystal oscillator, supporting a maximum internal clock frequency of 200MHz to improve data exchange speed; the second chip 20 and the third chip 30 use an ARM architecture and can support a 160MHz main frequency.
[0045] The above are merely specific embodiments of this utility model, but the design concept of this utility model is not limited thereto. Any non-substantial modifications made to this utility model using this concept shall be considered as an infringement of the protection scope of this utility model.
Claims
1. A central domain controller of a three-chip architecture, characterized by: It includes a first chip for controlling the vehicle's electronic unit, a second chip for assisting intelligent driving, and a third chip for intelligent drive-by-wire chassis. The three chips communicate through an SPI to CANFD circuit module or directly through the vehicle's CAN bus.
2. The central domain controller of a three-chip architecture according to claim 1, wherein: The first chip also includes a 3-channel SPI interface. The first channel of the SPI interface is connected to a first EEPROM chip for data storage, the second channel is connected to a FLASH chip for program upgrades, and the third channel is connected to the SPI-to-CANFD circuit module for communication.
3. The three-chip architecture central domain controller of claim 2, wherein: The first chip also includes an eT0ETC module and an eT1ETC module for PWM signal output, several GPIO interfaces for controlling the opening and closing of various relays and signal feedback, an ADC data acquisition interface, and a CAN interface for connecting to the vehicle network.
4. The three-chip architecture central domain controller of claim 1, wherein: The second chip also includes a 3-channel SPI interface. The first channel of the SPI interface is connected to an SPI-to-CANFD circuit module for communication, the second channel is connected to a second EEPROM chip for data storage, and the third channel is connected to a FLASH chip for program upgrades.
5. The three-chip architecture central domain controller of claim 4, wherein: The second chip also includes a CANFD interface and a reserved SPI-to-CANFD interface for increasing CANFD output resources.
6. The three-chip architecture central domain controller of claim 1, wherein: The third chip also includes three SPI interfaces. The first SPI interface is connected to an SPI-to-CANFD circuit module for communication, the second is connected to a third EEPROM chip for data storage, and the third is connected to a FLASH chip for program upgrades.
7. The three-chip architecture central domain controller of claim 6, wherein: The third chip also includes an in-vehicle Ethernet and CANFD interface, an eMIOS0_G_CH module for signal acquisition, a GPIO interface, an ADC data acquisition interface for analog signal input detection, a reserved SPI to CANFD circuit module, and an SPI communication interface.
8. The three-chip architecture central domain controller of claim 1, wherein: The SPI to CANFD circuit module also has an external interface for real-time monitoring via a CAN card device.
9. The three-chip architecture central domain controller of claim 1, wherein: All three chips are 32-bit automotive-grade microcontroller chips with dual-core lockstep functionality.