Integrated circuit and semiconductor device

Abstract

An integrated circuit and a semiconductor device are provided. The integrated circuit includes a series of delay cells coupled in series and a logic gate circuit. Each of the delay units includes an inverter and a switch. The inverter generates an output signal according to an input signal. The switch is coupled between a first supply voltage and the inverter. The switch provides a first supply voltage to the inverter according to a first control signal. The logic gate circuit transmits an output signal of the last delay unit in the string to the first delay unit in the string as an input signal. Finally, the frequency of the output signal of the delay unit indicates the carrier mobility of the circuit.

Description

Integrated circuits and semiconductor devices Technical Field

[0001] This disclosure relates to an integrated circuit and a semiconductor device, and more particularly to an integrated circuit and a semiconductor device for detecting internal stress. Background Technology

[0002] For three-dimensional integrated circuits (3DICs), variations in internal stress within the wafer lead to changes in carrier mobility, a key factor affecting wafer performance. Due to the uncertainty of internal stress, detecting internal stress and / or carrier mobility is crucial for optimizing 3DIC performance. Summary of the Invention

[0003] In some embodiments, an integrated circuit is provided. The integrated circuit includes a series-coupled array of multiple delay cells and logic gates. Each delay cell includes an inverter and a switch. The inverter generates an output signal based on an input signal. The switch is coupled between a first supply voltage and the inverter. The switch provides the first supply voltage to the inverter based on a first control signal. The logic gates transmit the output signal of the last delay cell in the series to the first delay cell in the series as an input signal. A frequency of the output signal of the last delay cell indicates a carrier mobility of the circuit.

[0004] In some embodiments, a semiconductor device is provided. The semiconductor device includes a delay unit. The delay unit includes an inverter and a ratio inverter. The inverter includes a first pull-up circuit and a first pull-down circuit. The first pull-up circuit is coupled between a first supply voltage and an output terminal. The first pull-down circuit is coupled between a second supply voltage and an output terminal. The ratio inverter includes a first transistor coupled to an input terminal of the inverter and has a gate terminal coupled to a first signal. The delay unit generates a second signal at the output terminal based on the first signal. The frequency of the second signal indicates the carrier mobility of the semiconductor device.

[0005] In some embodiments, an integrated circuit is provided. The integrated circuit includes a series of multiple delay units coupled in series and logic gates. Each delay unit includes an inverter and a switch. The inverter generates an output signal based on an input signal. The switch is coupled between a first supply voltage and the inverter. The switch provides the first supply voltage to the inverter based on a first control signal. The logic gates transmit the output signal of the last delay unit in the series to the first delay unit in the series as an input signal. A frequency of the output signal of the last delay unit indicates a carrier mobility of the circuit. The inverter includes a first transistor and a second transistor coupled in series between the switch and a second supply voltage, the gate terminals of the first transistor and the second transistor being coupled to the input signal, wherein the delay unit further includes a third transistor having a gate terminal coupled to the switch, wherein the third transistor is turned on to forward the output signal. Attached Figure Description

[0006] The embodiments disclosed herein are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In practice, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 is a schematic diagram showing circuits according to various embodiments of the present disclosure;

[0008] Figure 2A is a schematic diagram showing the delay unit configuration relative to the circuit 10 in Figure 1 according to various embodiments of the present disclosure;

[0009] Figure 2B is a schematic diagram showing the delay unit configuration relative to the delay unit configurations in Figures 1 and 2A according to various embodiments of the present disclosure;

[0010] Figure 3A is a schematic diagram showing the delay unit configuration relative to the delay unit configurations in Figures 1 and 2A according to various embodiments of the present disclosure;

[0011] Figure 3B is a schematic diagram showing the delay unit configuration relative to the delay unit configurations in Figures 1, 2A to 2B, and 3A according to various embodiments of the present disclosure;

[0012] Figure 4A is a schematic diagram showing an example of an n-type sensor circuit of the delay unit in Figures 2A and 3A according to various embodiments of the present disclosure;

[0013] Figure 4B is a schematic diagram showing an n-type sensor circuit according to various embodiments of the present disclosure, relative to the n-type sensor circuit configuration in Figure 4A.

[0014] Figure 4C is a schematic diagram showing an n-type sensor circuit according to various embodiments of the present disclosure, relative to the n-type sensor circuit configuration in Figure 4A.

[0015] Figure 5 is a schematic diagram illustrating an example of an n-type sensor circuit in Figure 3A according to various embodiments of the present disclosure;

[0016] Figure 6 is a schematic diagram showing an example of a p-type sensor circuit of the delay unit in Figures 2B and 3B according to various embodiments of the present disclosure;

[0017] Figure 7 is a schematic diagram showing an example of a p-type sensor circuit in Figure 3B according to various embodiments of the present disclosure;

[0018] Figure 8 is a layout diagram of the delay units relative to the delay unit configurations of Figures 3A to 3B, 4A to 4C, and 6 according to various embodiments of the present disclosure.

[0019] Figure 9 is a layout diagram of delay units according to various embodiments of the present disclosure, relative to the delay unit configurations corresponding to Figures 3A to 3B, 4A to 4C, and 5 to 8.

[0020] Figure 10 is a layout diagram of delay cells relative to the delay cell configuration in Figure 9 according to various embodiments of the present disclosure;

[0021] Figure 11 is a schematic diagram showing an example of an n-type sensor circuit of the delay unit in Figures 2A and 3A according to various embodiments of the present disclosure;

[0022] Figure 12 is a schematic diagram showing examples of n-type sensor circuits according to various embodiments of the present disclosure, relative to the n-type sensor circuit configuration in Figure 11.

[0023] Figure 13 is a schematic diagram showing examples of n-type sensor circuits according to various embodiments of the present disclosure, relative to the n-type sensor circuit configurations in Figures 11 and 12.

[0024] Figure 14 is a schematic diagram showing examples of n-type sensor circuits according to various embodiments of the present disclosure, relative to the n-type sensor circuit configurations in Figures 11 to 13.

[0025] Figure 15 is a schematic diagram showing an example of a p-type sensor circuit of the delay unit in Figures 2B and 3B according to various embodiments of the present disclosure;

[0026] Figure 16 is a schematic diagram showing examples of p-type sensor circuits according to various embodiments of the present disclosure, relative to the p-type sensor circuit configuration in Figure 15.

[0027] Figure 17 is a layout diagram of the delay cells relative to the delay cell configurations of Figures 3A to 3B and Figures 11 to 16 according to various embodiments of the present disclosure;

[0028] Figure 18 is a layout diagram of delay cells relative to the delay cell configuration in Figure 17 according to various embodiments of the present disclosure;

[0029] Figure 19 is a layout diagram of the standard cell of the inverter relative to the inverter configuration corresponding to Figures 11 to 18.

[0030] Figure 20 is a schematic diagram showing a standard cell of a delay cell circuit according to various embodiments of the present disclosure, including the circuits and delay cell configurations relative to Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, and 5 to 19.

[0031] Figures 21A to 21C are schematic diagrams illustrating examples of delay units configured relative to the delay unit configurations of Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, and 5 to 20 according to various embodiments of the present disclosure.

[0032] Figures 22A to 22C are schematic diagrams showing examples of delay units in Figures 21A to 21C according to various embodiments of the present disclosure;

[0033] Figures 23A to 23C are schematic diagrams of standard cells in the delay cell configuration relative to Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, 5 to 20, 21A to 21C, and 22A to 22C, according to various embodiments of the present disclosure.

[0034] Figure 24 is a schematic diagram of a standard cell with respect to the delay cell configuration of Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, 5 to 20, 21A to 21C, 22A to 22C, and 23A to 23C according to various embodiments of the present disclosure;

[0035] Figure 25A is a schematic diagram of a standard cell configuration relative to the delay cell configurations of Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, 5 to 20, 21A to 21C, 22A to 22C, 23A to 23C, and 24, according to various embodiments of the present disclosure.

[0036] Figure 25B is a schematic diagram of a standard cell configuration relative to the delay cell configurations of Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, 5 to 20, 21A to 21C, 22A to 22C, 23A to 23C, and 24 according to various embodiments of the present disclosure.

[0037] Figure 26 is a flowchart of a method for detecting carrier mobility or internal stress according to some embodiments of the present disclosure;

[0038] Figure 27 is a block diagram of an electronic design automation (EDA) system for designing integrated circuit layout designs according to some embodiments of the present disclosure;

[0039] Figure 28 is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments.

[0040] [Symbol Explanation]

[0041] 10: Circuit

[0042] 100: Delay Unit

[0043] 100a~100d: Delay unit

[0044] 110: Ratio Inverter

[0045] 120: Inverter

[0046] 121: Pull-up circuit

[0047] 122: Pull-down circuit

[0048] 130: Ratio Inverter

[0049] 200: Buffer circuit

[0050] 300: Logic gate circuits

[0051] 800: Delay Unit

[0052] 801~811: Gate structure

[0053] 821~832: Conductive Structure

[0054] 900: Delay Unit

[0055] 1000: Delay Unit

[0056] 1700: Delay Unit

[0057] 1800: Delay Unit

[0058] 1900: Inverter

[0059] 2000: Standard Unit

[0060] 2001-2002: Tap switch unit

[0061] 2010: Delay Unit Circuit

[0062] 2020:Substrate

[0063] 2100: Delay Unit

[0064] 2300a~2300c: Standard Unit

[0065] 2400: Standard Unit

[0066] 2401: Filler

[0067] 2500a~2500b: Standard Unit

[0068] 2501~2502: Filler

[0069] 2600: Method

[0070] 2601~2605: Operation

[0071] 2700: EDA System

[0072] 2710: I / O Interface

[0073] 2720: Hardware Processor

[0074] 2730: Network Interface

[0075] 2740: Network

[0076] 2750: Bus

[0077] 2760: Non-transitory computer-readable storage media

[0078] 2761: Instruction

[0079] 2762: Standard Unit Library

[0080] 2763:UI

[0081] 2770: Manufacturing Tools

[0082] 2800: IC Manufacturing System

[0083] 2810: Design Studio

[0084] 2811: IC Design Layout Diagram

[0085] 2820: Shielded Room

[0086] 2821: Data Preparation

[0087] 2822: Mask Manufacturing

[0088] 2823: Mask

[0089] 2830: Wafer Fab

[0090] 2831: Wafer Manufacturing

[0091] 2832: Semiconductor wafer

[0092] 2840: IC device

[0093] CPO:CPO

[0094] EN: Control signal

[0095] FOUT: Signal

[0096] I: Input terminal

[0097] M01~M06: Metal Wire

[0098] M11~M13: Metal wire

[0099] M15: Metal Wire

[0100] N1: Node

[0101] NS: n-type sensor circuit

[0102] NSL: Control Signal

[0103] O: Output terminal

[0104] OD1~OD3: Active Region

[0105] P1~P2: Power grid

[0106] PS: P-type sensor circuit

[0107] SL: Control signal

[0108] SW1~SW2: Switches

[0109] VDD: Supply voltage

[0110] VSS: Supply Voltage

[0111] W1~W2: Well Detailed Implementation

[0112] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, configurations, or the like are described below to simplify the embodiments disclosed herein. These are, of course, merely examples and are not intended to be limiting. Other components, materials, values, steps, configurations, or the like are also contemplated. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact.

[0113] The terms used throughout the following description and the scope of the claims generally have their common meanings clearly established in the art or in the specific context in which the terms are used. Those skilled in the art will understand that components or processes may be referred to by different names. The many different embodiments described in detail in this specification are merely illustrative and are in no way intended to limit the scope and spirit of the disclosed embodiments or any illustrative terminology.

[0114] It is worth noting that terms such as “first” and “second” used herein to describe various elements or processes are intended to distinguish one element or process from another. However, elements, processes, and their order should not be limited by these terms. For example, without departing from the scope of the embodiments disclosed herein, a first element may be referred to as a second element, and a second element may similarly be referred to as a first element.

[0115] In the following discussion and the scope of the patent application, the terms “comprising,” “including,” “containing,” “having,” “involving,” and the like shall be understood as open-ended, that is, to mean including but not limited to. As used herein, the term “and / or” includes any of the associated listed items and all combinations of one or more of the associated listed items, and is not mutually exclusive.

[0116] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly. The terms mask, optical lithography mask, photomask, and master photomask are used to refer to the same item.

[0117] The performance of a wafer is related to the carrier mobility of the semiconductor devices within the wafer, which is affected by the internal stress within the wafer. However, in three-dimensional integrated circuit (3DIC) wafers, the internal stress is uncertain, and therefore the carrier mobility is also uncertain. To maintain or monitor the performance of 3DIC wafers, it is necessary to detect the internal stress and / or carrier mobility. According to some methods, inaccurate measurements may occur during detection when the detection sensitivity is insufficient. Therefore, circuits and semiconductor devices with improved sensitivity are provided to address this problem.

[0118] Referring now to FIG1. ​​FIG1 is a schematic diagram showing a circuit 10 according to various embodiments of the present disclosure. For ease of understanding, the same notes and reference numerals are used to designate the same elements throughout the various views and illustrative embodiments. In some embodiments, circuit 10 is an integrated circuit. In some embodiments, circuit 10 is a semiconductor device. In some embodiments, circuit 10 is on a wafer. In some embodiments, circuit 10 is an on-wafer stress sensor.

[0119] For illustration, circuit 10 includes one or more delay units 100, buffer circuit 200, and logic gate circuit 300. In some embodiments, the delay units 100 are connected in series to form a series. The buffer circuit 200 is coupled to the end of the series. The logic gate circuit 300 is coupled to the beginning and end of the series to form a ring structure.

[0120] In some embodiments, the delay unit 100, buffer circuit 200, and logic gate circuit 300 are configured as a ring oscillator that generates the signal FOUT. The oscillation frequency of the signal FOUT reflects the carrier mobility and internal stress. In some embodiments, an increase in carrier mobility leads to an increase in the oscillation frequency. Conversely, a decrease in carrier mobility leads to a decrease in the oscillation frequency. As a result, carrier mobility and internal stress can be monitored by observing the oscillation frequency.

[0121] As shown in Figure 1, logic gate 300 receives a control signal EN and a signal from node N1 at the end of the serial array of delay units 100. The control signal enables circuit 10 to generate signal FOUT. For example, circuit 10 generates signal FOUT when the control signal EN has a first voltage level (e.g., logic high) indicating the generation of signal FOUT. When the control signal EN has a second voltage level (e.g., logic low) indicating the generation of signal FOUT disabled, circuit 10 stops generating signal FOUT. In some embodiments, when the control signal EN indicates disabled, circuit 10 outputs a constant voltage (e.g., logic low).

[0122] In some embodiments, logic gate 300 includes one or more logic gates that generate signals to the beginning of the sequence of delay units 100. In some embodiments, logic gate 300 is a NAND gate that receives a control signal EN and a signal from node N1 to generate signals to the beginning of the sequence.

[0123] In some embodiments, to generate an oscillating signal FOUT, logic gate 300 generates a signal that is inversely proportional to the signal at node N1. Then, logic gate 300 outputs the generated signal to the serial array of delay unit 100. For example, when control signal EN indicates enable as described above, logic gate 300 receives a signal with a first voltage level (e.g., logic high) from node N1 and generates a signal with a second voltage level (e.g., logic low) to the serial array of delay unit.

[0124] In some embodiments, the buffer circuit 200 includes one or more buffers connected in series, which receive a signal from node N1 and generate a signal FOUT. In some embodiments, the logic value of the signal from node N1 is equal to the logic value of the signal FOUT. In some embodiments, the buffer circuit 200 is used to amplify the signal from node N1 to generate the signal FOUT.

[0125] In some embodiments, each delay unit 100 includes an input terminal I and an output terminal O. In a series of delay units 100, the output terminal O of the previous stage of delay unit 100 is coupled to the input terminal I of the next stage of delay unit 100. The series of delay units 100 propagates signals from logic gate circuit 300 to node N1.

[0126] In some embodiments, the configuration of the delay unit 100 affects the frequency of the signal FOUT, thereby affecting the sensitivity of stress or carrier mobility detection via the frequency of the signal FOUT. Further details of the delay unit 100 will be described in the following paragraphs.

[0127] Referring now to FIG. 2A. FIG. 2A is a schematic diagram showing a delay unit 100a configured relative to the delay unit 100 in the circuit 10 of FIG. 1 according to various embodiments of the present disclosure. For simplicity, specific operations of similar elements previously discussed in detail have been omitted.

[0128] As shown in Figure 2A, in some embodiments, the delay unit 100a includes an n-type sensor circuit NS. In some embodiments, the n-type sensor circuit NS is used to detect the carrier mobility of an n-type semiconductor device, such as an n-type metal-oxide-semiconductor field-effect transistor (NMOS).

[0129] The n-type sensor circuit NS is coupled to input terminal I, output terminal O, supply voltage VDD, and supply voltage VSS. According to some embodiments, the supply voltage VDD is higher than the supply voltage VSS. In some embodiments, the supply voltage VSS is the ground voltage.

[0130] The n-type sensor circuit NS uses the supply voltages VDD and VSS as its power source. The n-type sensor circuit NS generates a signal to the output terminal O based on the signal from the input terminal I.

[0131] Referring now to FIG2B. FIG2B is a schematic diagram showing a delay unit 100b configured relative to the delay unit 100a and delay unit 100 in the circuit 10 of FIG1 and FIG2A according to various embodiments of the present disclosure.

[0132] Compared to delay unit 100a, delay unit 100b includes a p-type sensor circuit PS instead of an n-type sensor circuit NS. In some embodiments, the p-type sensor circuit PS is used to detect the carrier mobility of a p-type semiconductor device, such as a p-type metal-oxide-semiconductor field-effect transistor (PMOS).

[0133] Similar to the n-type sensor circuit NS, the p-type sensor circuit PS uses the supply voltages VDD and VSS as power sources and generates a signal to the output terminal O based on the signal from the input terminal I.

[0134] Referring now to FIG3A. FIG3A is a schematic diagram showing delay unit 100c configured relative to delay units 100 and 100a in FIG1 and FIG2A according to various embodiments of the present disclosure.

[0135] Compared to delay unit 100a, delay unit 100c further includes a switch SW1 coupled between the supply voltage VDD and the n-type sensor circuit NS. Switch SW1 controls the power supply to the n-type sensor circuit NS according to a control signal SL to conserve energy. For example, when the control signal SL has a first voltage level (e.g., logic high), the n-type sensor circuit NS is in a sleep mode.

[0136] In some embodiments, in response to a control signal EN having a second voltage level indicating enable, a control signal SL has a first voltage level indicating sleep mode. In some embodiments, the first voltage level of the control signal SL indicating sleep mode is reversed to the second voltage level of the control signal EN indicating enable.

[0137] In some embodiments, in response to a control signal SL having a first voltage level (e.g., logic low), switch SW1 is turned on to provide a supply voltage VDD to the n-type sensor circuit NS. Conversely, in response to a control signal SL having a second voltage level indicating a sleep mode (e.g., logic high), switch SW1 is turned off to stop providing the supply voltage VDD to the n-type sensor circuit NS.

[0138] In some embodiments, switch SW1 includes a p-type metal-oxide-semiconductor field-effect transistor (PMOS). The source / drain terminals of switch SW1 are coupled to the supply voltage VDD. The drain / source terminals of switch SW1 are coupled to an n-type sensor circuit NS. The gate terminal of switch SW1 is coupled to a control signal SL.

[0139] Referring now to FIG3B. FIG3B is a schematic diagram showing delay unit 100d configured relative to delay units 100, 100a, 100b and 100c in FIG1 and FIG2A to FIG2B and FIG3A according to various embodiments of the present disclosure.

[0140] Compared to delay unit 100b, delay unit 100d further includes a switch SW2 coupled between the supply voltage VSS and the p-type sensor circuit PS. Switch SW2 controls the power supply to the p-type sensor circuit PS according to a control signal NSL to conserve energy. For example, when the control signal NSL has a first voltage level (e.g., logic low), the p-type sensor circuit PS is in a sleep mode.

[0141] In some embodiments, the control signal EN has a second voltage level indicating enable, and the control signal NSL has a first voltage level indicating sleep mode. In some embodiments, the second voltage level indicating enable in response to the control signal EN is logic high, and the first voltage level indicating sleep mode in response to the control signal NSL is logic high.

[0142] In some embodiments, in response to the control signal NSL having a first voltage level (e.g., logic high), switch SW2 is turned on to provide supply voltage VSS to p-type sensor circuit PS. Conversely, in response to the control signal NSL having a second voltage level indicating sleep mode (e.g., logic low), switch SW2 is turned off to stop providing supply voltage VSS to p-type sensor circuit PS.

[0143] In some embodiments, switch SW2 includes an n-type metal-oxide-semiconductor field-effect transistor (NMOS). The source / drain terminals of switch SW2 are coupled to the supply voltage VSS. The drain / source terminals of switch SW2 are coupled to a p-type sensor circuit PS. The gate terminal of switch SW2 is coupled to a control signal NSL.

[0144] Referring now to FIG4A. FIG4A is a schematic diagram showing an example of an n-type sensor circuit NS of delay units 100a and 100c in FIG2A and 3A according to various embodiments of the present disclosure.

[0145] In some embodiments, the n-type sensor circuit NS includes transistors t11, t12, and t13. In some embodiments, transistors t11 and t12 are NMOS transistors, and transistor t13 is a PMOS transistor.

[0146] For illustration, the source / drain terminals of transistor t11 are coupled to input terminal I. The drain / source terminals of transistor t11 are coupled to the gate terminal of transistor t12. The gate terminal of transistor t11 is coupled to the source / drain terminals of transistor t13.

[0147] The source / drain terminals of transistor t12 are coupled to the supply voltage VSS. The drain / source terminals of transistor t12 are coupled to the output terminal O.

[0148] The source / drain terminals of transistor t13 are coupled to switch SW1. The drain / source terminals of transistor t13 are coupled to output terminal O. The gate terminal of transistor t13 is coupled to input terminal I.

[0149] Referring now to FIG4B. FIG4B is a schematic diagram showing an n-type sensor circuit NS configured relative to the n-type sensor circuit NS in FIG4A according to various embodiments of the present disclosure.

[0150] Compared to the n-type sensor circuit NS in Figure 4A, the n-type sensor circuit NS in Figure 4B further includes multiple transistors t12 connected in series between the supply voltage VSS and the output terminal O. The gate terminals of transistors t12 are coupled to the drain / source terminals of transistor t11.

[0151] Furthermore, compared to the n-type sensor circuit NS in Figure 4A, the n-type sensor circuit NS in Figure 4B further includes multiple transistors t13 connected in series between the switch SW1 and the output terminal O. The gate terminals of the transistors t13 are coupled to the input terminal I.

[0152] Referring now to FIG4C. FIG4C is a schematic diagram showing an n-type sensor circuit NS configured relative to the n-type sensor circuit NS in FIG4A according to various embodiments of the present disclosure.

[0153] Compared to the n-type sensor circuit NS in Figure 4A, the n-type sensor circuit NS in Figure 4C further includes multiple transistors t12 connected in parallel between the supply voltage VSS and the output terminal O. The gate terminals of transistors t12 are coupled to the drain / source terminals of transistor t11.

[0154] Furthermore, compared to the n-type sensor circuit NS in Figure 4A, the n-type sensor circuit NS in Figure 4C further includes multiple transistors t13 connected in parallel between the switch SW1 and the output terminal O. The gate terminals of the transistors t13 are coupled to the input terminal I.

[0155] In some embodiments, in the n-type sensor circuit NS of Figures 4B and 4C, the number of transistors t12 is equal to the number of transistors t13.

[0156] Referring now to FIG5. FIG5 is a schematic diagram showing an example of an n-type sensor circuit NS in FIG3A according to various embodiments of the present disclosure.

[0157] As shown in Figure 5, in some embodiments, the n-type sensor circuit NS includes transistors t21, t22, and t23. In some embodiments, transistor t21 is a PMOS, and transistors t22 and t23 are NMOS.

[0158] For illustration, the source / drain terminals of transistor t21 are coupled to switch SW1. The drain / source terminals of transistor t21 are coupled to the source / drain terminals of transistor t23. The gate terminal of transistor t21 is coupled to input terminal I.

[0159] The source / drain terminals of transistor t22 are coupled to the supply voltage VSS. The drain / source terminals of transistor t22 are coupled to the source / drain terminals of transistor t23. The gate terminal of transistor t22 is coupled to the input terminal I. In some embodiments, transistors t21 and t22 are configured as inverters.

[0160] The drain / source terminals of transistor t23 are coupled to output terminal O. The gate terminal of transistor t23 is coupled to switch SW1.

[0161] In some embodiments, the n-type sensor circuit NS in FIG5 further includes a plurality of transistors t21 and t22 connected in series, which are similar to transistors t12 and t13 in FIG4B.

[0162] Specifically, transistor t21 is connected in series between switch SW1 and the source / drain terminals of transistor t23. The gate terminal of transistor t21 is coupled to input terminal I. Transistor t22 is connected in series between the supply voltage VSS and the source / drain terminals of transistor t23. The gate terminal of transistor t22 is coupled to input terminal I.

[0163] In other embodiments, the n-type sensor circuit NS in FIG5 further includes a plurality of transistors t21 and t22 coupled in parallel, which are similar to transistors t12 and t13 in FIG4C.

[0164] Referring now to FIG6. FIG6 is a schematic diagram showing an example of a p-type sensor circuit PS of delay units 100b and 100d in FIG2B and 3B according to various embodiments of the present disclosure.

[0165] In some embodiments, the p-type sensor circuit PS includes transistors t31, t32, and t33. In some embodiments, transistors t31 and t32 are PMOS transistors, and transistor t33 is an NMOS transistor.

[0166] For illustration, the source / drain terminals of transistor t31 are coupled to input terminal I. The drain / source terminals of transistor t31 are coupled to the gate terminal of transistor t32. The gate terminal of transistor t31 is coupled to the source / drain terminals of transistor t33.

[0167] The source / drain terminals of transistor t32 are coupled to the supply voltage VDD. The drain / source terminals of transistor t32 are coupled to the output terminal O.

[0168] The source / drain terminals of transistor t33 are coupled to switch SW2. The drain / source terminals of transistor t33 are coupled to output terminal O. The gate terminal of transistor t33 is coupled to input terminal I.

[0169] In some embodiments, the p-type sensor circuit PS in FIG6 further includes a plurality of transistors t32 and t33 connected in series, which are similar to transistors t12 and t13 in FIG4B.

[0170] In other embodiments, the p-type sensor circuit PS in FIG6 further includes a plurality of transistors t32 and t33 coupled in parallel, which are similar to transistors t12 and t13 in FIG4C.

[0171] Referring now to FIG7. FIG7 is a schematic diagram showing an example of a p-type sensor circuit PS in FIG3B according to various embodiments of the present disclosure.

[0172] As shown in Figure 7, in some embodiments, the p-type sensor circuit PS includes transistors t41, t42, and t43. In some embodiments, transistor t41 is an NMOS, and transistors t42 and t43 are PMOS.

[0173] For illustration, the source / drain terminals of transistor t41 are coupled to switch SW2. The drain / source terminals of transistor t41 are coupled to the source / drain terminals of transistor t43. The gate terminal of transistor t41 is coupled to input terminal I.

[0174] The source / drain terminals of transistor t42 are coupled to the supply voltage VDD. The drain / source terminals of transistor t42 are coupled to the source / drain terminals of transistor t43. The gate terminal of transistor t42 is coupled to the input terminal I. In some embodiments, transistors t41 and t42 are configured as inverters.

[0175] The drain / source terminals of transistor t43 are coupled to output terminal O. The gate terminal of transistor t43 is coupled to switch SW2.

[0176] In some embodiments, the p-type sensor circuit PS in FIG7 further includes a plurality of transistors t41 and t42 connected in series, which are similar to transistors t12 and t13 in FIG4B.

[0177] In other embodiments, the p-type sensor circuit PS in FIG7 further includes a plurality of transistors t41 and t42 coupled in parallel, which are similar to transistors t12 and t13 in FIG4C.

[0178] Referring now to FIG8. FIG8 is a layout diagram of a delay unit 800 configured with respect to delay units 100c and 100d of FIG3A to 3B, FIG4A to 4C and FIG6, according to various embodiments of the present disclosure.

[0179] For illustration, the delay unit 800 includes active regions OD1 to OD2, gate structures 801 to 811, conductive structures 821 to 832, grid P1 to P2, metal lines M01 to M06, and metal lines M11 to M12.

[0180] Active regions OD1-OD2 are located in the oxide diffusion (OD) layer. Gate structures 801-811 are located in the gate layer above the OD layer. Conductive structures 821-832 are located in the metal-to-device (MD) layer above the OD layer. Metal lines M01-M06 are located in the metal zero (M0) layer above the gate and MD layers. Metal lines M11-M12 are located in the metal layer above the M0 layer.

[0181] As shown in Figure 8, the conductive structure in the MD layer is coupled to the metal line in the M0 layer via the via VD between the MD and M0 layers. The gate structure in the gate layer is coupled to the metal line in the M0 layer via the via VG between the gate and the M0 layer. The metal line in the M0 layer is coupled to the metal line in the M1 layer via the via V0 between the M0 and M1 layers.

[0182] In some embodiments, the delay unit 800 includes a switch SW1 and an n-type sensor NS. In the embodiment of FIG8, the n-type sensor NS includes four transistors t13 and four transistors t12 connected in parallel as described above with reference to FIG4C.

[0183] In this embodiment, gate structures 801, 803, 805, and 807 correspond to the gate terminals of transistor t13. Conductive structures 821, 824, and 827 correspond to the source / drain terminals of transistor t13. Conductive structures 823 and 826 correspond to the drain / source terminals of transistor t13.

[0184] Gate structures 802, 804, 806, and 808 correspond to the gate terminals of transistor t12. Conductive structures 822, 825, and 828 correspond to the source / drain terminals of transistor t12. Conductive structures 823 and 826 correspond to the drain / source terminals of transistor t12.

[0185] Gate structure 809 corresponds to the gate terminal of switch SW1. Conductive structure 827 corresponds to the drain / source terminals of switch SW1. Conductive structure 829 corresponds to the source / drain terminals of switch SW1.

[0186] Gate structure 811 corresponds to the gate terminal of transistor t11. Conductive structure 830 corresponds to the drain / source terminal of transistor t11. Conductive structure 832 corresponds to the source / drain terminal of transistor t11.

[0187] Power grids P1 and P2 transmit supply voltages VDD and VSS, respectively. Metal wire M11 corresponds to output terminal O. Metal wire M12 corresponds to input terminal I.

[0188] In some embodiments, the delay unit 800 includes a switch SW2 and a p-type sensor PS. In the embodiment of FIG8, the p-type sensor PS includes four transistors t32 and four transistors t33 connected in parallel as described above with reference to FIG4C and FIG6.

[0189] In this embodiment, gate structures 801, 803, 805, and 807 correspond to the gate terminals of transistor t33. Conductive structures 821, 824, and 827 correspond to the source / drain terminals of transistor t33. Conductive structures 823 and 826 correspond to the drain / source terminals of transistor t33.

[0190] Gate structures 802, 804, 806, and 808 correspond to the gate terminals of transistor t32. Conductive structures 822, 825, and 828 correspond to the source / drain terminals of transistor t32. Conductive structures 823 and 826 correspond to the drain / source terminals of transistor t32.

[0191] Gate structure 809 corresponds to the gate terminal of switch SW2. Conductive structure 827 corresponds to the drain / source terminals of switch SW2. Conductive structure 829 corresponds to the source / drain terminals of switch SW2.

[0192] Gate structure 811 corresponds to the gate terminal of transistor t31. Conductive structure 830 corresponds to the drain / source terminals of transistor t31. Conductive structure 832 corresponds to the source / drain terminals of transistor t31.

[0193] Power grids P1 and P2 transmit supply voltages VSS and VDD, respectively. Metal wire M11 corresponds to output terminal O. Metal wire M12 corresponds to input terminal I.

[0194] Referring now to FIG9. FIG9 is a layout diagram of delay unit 900 configured with delay units 100c and 100d corresponding to various embodiments of the present disclosure.

[0195] In some embodiments, the delay unit 900 includes a switch SW1 and an n-type sensor NS. In the embodiment of FIG9, the n-type sensor NS includes four transistors t21 and four transistors t22 connected in parallel as described above with reference to FIG4C and FIG5.

[0196] In this embodiment, gate structures 801, 803, 805, and 807 correspond to the gate terminals of transistors t21 and t22. Conductive structures 821, 824, and 827 correspond to the source / drain terminals of transistor t21. Conductive structures 823 and 826 correspond to the drain / source terminals of transistor t21.

[0197] Conductive structures 822, 825, and 828 correspond to the source / drain terminals of transistor t22. Conductive structures 823 and 826 correspond to the drain / source terminals of transistor t22.

[0198] Gate structure 809 corresponds to the gate terminal of switch SW1. Conductive structure 827 corresponds to the drain / source terminals of switch SW1. Conductive structure 829 corresponds to the source / drain terminals of switch SW1.

[0199] Gate structure 811 corresponds to the gate terminal of transistor t23. Conductive structure 830 corresponds to the drain / source terminals of transistor t23. Conductive structure 832 corresponds to the source / drain terminals of transistor t23.

[0200] Power grids P1 and P2 transmit supply voltages VDD and VSS, respectively. Metal wire M13 corresponds to output terminal O. Metal wire M03 corresponds to input terminal I.

[0201] In some embodiments, the delay unit 900 includes a switch SW2 and a p-type sensor PS. In the embodiment of FIG9, the p-type sensor PS includes four transistors t41 and four transistors t42 connected in parallel as described above with reference to FIG4C and FIG7.

[0202] In the layout of Figure 9, transistors t41, t42, t43 and switch SW2 in the embodiment of the p-type sensor PS correspond to transistors t21, t22, t23 and switch SW1 in the embodiment of the n-type sensor NS. For example, in the embodiment of the n-type sensor NS, gate structure 801 corresponds to the gate terminal of transistor t21, and in the embodiment of the p-type sensor PS, gate structure 801 corresponds to the gate terminal of transistor t41. Therefore, for simplicity, the correspondence of elements in the embodiment of the p-type sensor PS is omitted here.

[0203] In the embodiment of the p-type sensor PS, the power grids P1 and P2 transmit supply voltages VSS and VDD, respectively.

[0204] Referring now to FIG10. FIG10 is a layout diagram of a delay unit 1000 configured relative to the delay unit 900 in FIG9 according to various embodiments of the present disclosure.

[0205] Compared to delay unit 900, in delay unit 1000, metal wire M01 is cut into metal wires M01 and M06. Conductive structure 823 is cut into conductive structures 823 and 833. Conductive structure 826 is cut into conductive structures 826 and 834.

[0206] The correspondence of the elements in delay unit 1000 is similar to that in delay unit 900. Therefore, for simplicity, the description of the correspondence is omitted here.

[0207] The configurations shown in Figures 8 to 10 are for illustrative purposes only. Various implementations are within the scope of the embodiments disclosed herein. For example, a portion of the delay unit 800 may be repeated to have more transistors connected in parallel. The positions of the components can be adjusted without changing the connection relationships. For example, metal lines M11 to M12 may be moved along the x-direction. The positions of metal line M01 and the via VD coupled thereto may be moved along the y-direction.

[0208] Referring now to FIG11. FIG11 is a schematic diagram showing an example of an n-type sensor circuit NS of delay units 100a and 100c in FIG2A and 3A according to various embodiments of the present disclosure.

[0209] As shown in Figure 11, in some embodiments, the n-type sensor circuit NS includes a ratio inverter 110 and an inverter 120. The ratio inverter 110 includes transistors t51 and t52. In some embodiments, transistors t51 and t52 are NMOS.

[0210] In some embodiments, ratio inverter 110 is used to indicate the carrier mobility or velocity of the NMOS. Specifically, the propagation delay of ratio inverter 110 indicates the carrier mobility or velocity of the NMOS. Since the output of ratio inverter 110 may not be full swing, inverter 120 is used to provide a full swing output to output terminal O.

[0211] In some embodiments, when a falling edge is applied to input terminal I, transistor t52 is turned off, and then transistor t54 is turned on. On the other hand, when a rising edge is applied to output terminal I, transistor t52 is turned on, and then transistor t53 is turned on. Because the falling edge propagates through the n-type sensor circuit NS, and transistor t53 is not turned on, the falling edge propagation delay of the n-type sensor circuit NS is used to sense the NMOS carrier mobility or velocity.

[0212] For illustration, the drain / source terminals and gate terminal of transistor t51 are coupled to switch SW1. In an embodiment without switch SW1, the drain / source terminals and gate terminal of transistor t51 are coupled to the supply voltage VDD. The source / drain terminals of transistor t51 are coupled together with the drain / source terminals of transistor t52 as the output terminals of ratio inverter 110.

[0213] The source / drain terminals of transistor t52 are coupled to the supply voltage VSS. The gate terminal of transistor t52 is coupled to the input terminal I.

[0214] The inverter 120 includes a pull-up circuit 121 and a pull-down circuit 122. In some embodiments, the pull-up circuit 121 includes a transistor t53. In some embodiments, the transistor t53 is a PMOS.

[0215] The source / drain terminals of transistor t53 are coupled to switch SW1. In an embodiment without switch SW1, the source / drain terminals of transistor t53 are coupled to the supply voltage VDD. The drain / source terminals of transistor t53 are coupled to output terminal O. The gate terminal of transistor t53 is coupled together with the gate terminal of transistor t54 as the input terminal of inverter 120. The input terminal of inverter 120 is coupled to the output terminal of ratio inverter 110.

[0216] The drain / source terminals of transistor t54 are coupled to the output terminal O. The source / drain terminals of transistor t54 are coupled to the supply voltage VSS.

[0217] Referring now to FIG12. FIG12 is a schematic diagram showing examples of n-type sensor circuit NS configured relative to the n-type sensor circuit NS in FIG11 according to various embodiments of the present disclosure.

[0218] As shown in Figure 12, in some embodiments, the pull-up circuit 121 includes a plurality of transistors t53 connected in series between the output terminal O and the switch SW1 or the supply voltage VDD. The pull-down circuit 122 includes a plurality of transistors t54 connected in series between the output terminal O and the supply voltage VSS. The gate terminals of transistors t53 and t54 are coupled together as the input terminal of the inverter 120.

[0219] Referring now to FIG13. FIG13 is a schematic diagram showing examples of an n-type sensor circuit NS configured relative to the n-type sensor circuit NS in FIG11 and FIG12 according to various embodiments of the present disclosure.

[0220] As shown in Figure 13, in some embodiments, the inverter 120 includes a plurality of pull-up circuits 121 connected in parallel between the output terminal O and the switch SW1 or the supply voltage VDD. In some embodiments, the inverter 120 includes a plurality of pull-down circuits 122 connected in parallel between the output terminal O and the supply voltage VSS. The gate terminals of transistors t53 and t54 are coupled together as the input terminals of the inverter 120.

[0221] Referring now to FIG14. FIG14 is a schematic diagram showing examples of an n-type sensor circuit NS configured relative to the n-type sensor circuit NS in FIG11 to FIG13 according to various embodiments of the present disclosure.

[0222] According to various embodiments disclosed herein, inverter 120 may include one or more pull-up circuits 121 and one or more pull-down circuits 122 connected in parallel in the manner described above corresponding to FIG. 13. In inverter 120, the number of pull-up circuits 121 may differ from the number of pull-down circuits 122.

[0223] Each pull-up circuit 121 may include one or more transistors t53 connected in series in the manner described above, corresponding to FIG. 12. Each pull-down circuit 122 may include one or more transistors t54 connected in series in the manner described above, corresponding to FIG. 12. The number of transistors t53 connected in series in different pull-up circuits 121 may be different. Similarly, the number of transistors t54 connected in series in different pull-down circuits 122 may be different.

[0224] For example, as shown in Figure 14, in some embodiments, the inverter 120 includes four pull-up circuits 121 coupled in parallel and one pull-down circuit 122. Each pull-up circuit 121 includes a transistor t53. The pull-down circuit 122 includes three transistors t54 coupled in series.

[0225] According to various embodiments, the sensitivity of the n-type sensor circuit increases as the rate at which the voltage at the output terminal O is pulled up by the pull-up circuit 121 increases. According to various embodiments, increasing the parallel-coupled transistor t53 can improve the rate of increase, thereby improving the sensitivity.

[0226] Conversely, as the rate at which the pull-down circuit 122 pulls down the voltage at the output terminal O decreases, the sensitivity of the n-type sensor circuit increases. According to various embodiments, adding a series-coupled transistor t54 reduces the rate of decrease, thereby increasing sensitivity.

[0227] In summary, the sensitivity of an n-type sensor circuit is directly proportional to the number of transistors t53 connected in parallel and the number of transistors t54 connected in series. The sensitivity of an n-type sensor circuit is inversely proportional to the number of transistors t54 connected in parallel and the number of transistors t53 connected in series.

[0228] Referring now to FIG15. FIG15 is a schematic diagram showing an example of a p-type sensor circuit PS of delay units 100b and 100d in FIG2B and 3B according to various embodiments of the present disclosure.

[0229] As shown in Figure 15, in some embodiments, the p-type sensor circuit PS includes a ratio inverter 130 and an inverter 120. The ratio inverter 130 includes transistors t61 and t62. In some embodiments, transistors t61 and t62 are PMOS.

[0230] In some embodiments, when a rising edge is applied to input terminal I, transistor t61 is turned off, and then transistor t53 is turned on. On the other hand, when a falling edge is applied to input terminal I, transistor t61 is turned on, and then transistor t54 is turned on. Because the rising edge propagates through the p-type sensor circuit PS while transistor t54 is not turned on, the rise propagation delay of the p-type sensor circuit PS is used to sense the PMOS carrier mobility or velocity.

[0231] For illustration, the drain / source terminals and gate terminal of transistor t62 are coupled to switch SW2. In an embodiment without switch SW2, the drain / source terminals and gate terminal of transistor t62 are coupled to the supply voltage VSS. The source / drain terminals of transistor t62 are coupled together with the drain / source terminals of transistor t61 as the output terminals of ratio inverter 130.

[0232] The source / drain terminals of transistor t61 are coupled to the supply voltage VDD. The gate terminal of transistor t61 is coupled to the input terminal I.

[0233] The inverter 120 of the p-type sensor circuit PS in Figure 15 is similar to the inverter 120 of the n-type sensor circuit NS in Figures 11 to 14. Specifically, the inverter 120 may include one or more pull-up circuits 121 connected in parallel between the supply voltage VDD and the output terminal O. The inverter 120 may also include one or more pull-down circuits 122 connected in parallel between the output terminal O and the switch SW2 or the supply voltage VSS.

[0234] Each pull-up circuit 121 may include one or more transistors t53 connected in series, and each pull-down circuit 122 may include at least one transistor t54 connected in series in the manner described above corresponding to FIG12.

[0235] Referring now to FIG16. FIG16 is a schematic diagram showing examples of p-type sensor circuit PS configured relative to the p-type sensor circuit PS in FIG15 according to various embodiments of the present disclosure.

[0236] According to various embodiments disclosed herein, the number of pull-up circuits 121 in inverter 120 may differ from the number of pull-down circuits 122. The number of transistors t53 series-coupled in different pull-up circuits 121 may differ. The number of transistors t54 series-coupled in different pull-down circuits 122 may differ.

[0237] For example, as shown in Figure 16, in some embodiments, the inverter 120 includes four pull-down circuits 122 coupled in parallel and one pull-up circuit 121. Each pull-down circuit 122 includes a transistor t54. The pull-up circuit 121 includes two transistors t53 coupled in series.

[0238] According to various embodiments, the sensitivity of the p-type sensor circuit increases when the rate at which the voltage at the output terminal O of the pull-up circuit 121 decreases. According to various embodiments, adding a series-coupled transistor t53 reduces the rate of increase, thereby improving sensitivity.

[0239] Conversely, as the rate at which the voltage at the output terminal O is pulled down by the pull-down circuit 122 increases, the sensitivity of the p-type sensor circuit increases. According to various embodiments, adding a parallel-coupled transistor t54 can increase the rate of increase, thereby improving the sensitivity.

[0240] In summary, the sensitivity of a p-type sensor circuit is directly proportional to the number of transistors t54 connected in parallel and the number of transistors t53 connected in series. The sensitivity of a p-type sensor circuit is inversely proportional to the number of transistors t53 connected in parallel and the number of transistors t54 connected in series.

[0241] Referring now to FIG17. FIG17 is a layout diagram of delay unit 1700 configured with delay units 100c to 100d according to various embodiments of the present disclosure, relative to the delay units 100c to 100d of FIG3A to FIG3B and FIG11 to FIG16.

[0242] In some embodiments, the delay unit 1700 includes a switch SW1 and an n-type sensor NS, as shown in FIG13. In the embodiment of FIG17, the n-type sensor NS includes four transistors t53 and four transistors t54 connected in parallel.

[0243] In this embodiment, gate structures 805, 807, 809, and 811 correspond to the gate terminals of transistors t53 and t54. Conductive structures 824, 827, and 831 correspond to the source / drain terminals of transistor t53. Conductive structures 826 and 829 correspond to the drain / source terminals of transistor t53.

[0244] Conductive structures 825, 828, and 832 correspond to the source / drain terminals of transistor t54. Conductive structures 826 and 829 correspond to the drain / source terminals of transistor t54.

[0245] Gate structures 801 and 803 correspond to the gate terminals of switch SW1. Conductive structures 821 and 824 correspond to the drain / source terminals of switch SW1. Conductive structure 823 corresponds to the source / drain terminals of switch SW1.

[0246] Gate structure 802 corresponds to the gate terminal of transistor t51. Conductive structure 821 corresponds to the drain / source terminals of transistor t51. Conductive structure 833 corresponds to the source / drain terminals of transistor t51.

[0247] Gate structure 804 corresponds to the gate terminal of transistor t52. Conductive structure 833 corresponds to the drain / source terminals of transistor t52. Conductive structure 825 corresponds to the source / drain terminals of transistor t52.

[0248] Power grids P1 and P2 transmit supply voltages VDD and VSS, respectively. Metal wire M15 corresponds to output terminal O. Metal wire M13 corresponds to input terminal I.

[0249] In some embodiments, the delay unit 1700 includes a switch SW2 and a p-type sensor PS, as shown in FIG15. In the embodiment of FIG17, the p-type sensor PS includes four transistors t53 and four transistors t54 connected in parallel.

[0250] In the layout of Figure 17, transistors t61, t62, t54, t53 and switch SW2 in the embodiment of the p-type sensor PS correspond to transistors t51, t52, t53, t54 and switch SW1 in the embodiment of the n-type sensor NS. For example, in the embodiment of the n-type sensor NS, gate structure 801 corresponds to the gate terminal of switch SW1, and in the embodiment of the p-type sensor PS, gate structure 801 corresponds to the gate terminal of switch SW2. Therefore, for simplicity, the correspondence of elements in the embodiment of the p-type sensor PS is omitted here.

[0251] In the embodiment of the p-type sensor PS, the power grids P1 and P2 transmit supply voltages VSS and VDD, respectively.

[0252] Referring now to FIG18. FIG18 is a layout diagram of delay unit 1800 configured relative to delay unit 1700 in FIG17 according to various embodiments of the present disclosure.

[0253] Compared to delay unit 1700, in delay unit 1800, metal wire M01 is cut into metal wires M01 and M06. Metal wire M07 is cut into metal wires M07 and M08. Conductive structure 826 is cut into conductive structures 826 and 834.

[0254] The correspondence of the elements in delay unit 1800 is similar to that in delay unit 1700. Therefore, for simplicity, the description of the correspondence is omitted here.

[0255] Now refer to Figure 19. Figure 19 is a layout diagram of the standard unit of the inverter 120 configured relative to the inverter 120 configuration corresponding to Figures 11 to 18.

[0256] In the embodiment of Figure 19, inverter 120 is a mismatched inverter, wherein the term mismatched inverter indicates that the number of transistors t53 and t54 are different, in order to adjust the sensitivity of the n-type sensor circuit NS or the p-type sensor circuit PS.

[0257] For example, inverter 120 includes four transistors t53 corresponding to gate structures 805, 807, 809, 811 and conductive structures 824, 826, 827, 829, 831. Inverter 120 further includes one transistor t54 corresponding to gate structure 805 and conductive structures 825 and 834.

[0258] As shown in Figure 19, in the standard unit of the mismatched inverter, the number of conductive structures (e.g., 824, 827, 831) coupled to the power grid P1 is different from the number of conductive structures (e.g., 825, 828, 830, 832) coupled to the power grid P2.

[0259] The configurations shown in Figures 17 to 19 are for illustrative purposes only. Various implementations are within the scope of the embodiments disclosed herein. For example, a portion of the delay unit 1700 may be repeated to have more transistors connected in parallel. The positions of the components can be adjusted without changing the connection relationships. For example, the positions of the metal line M01 and the via VG coupled thereto may be moved along the y-direction.

[0260] Referring now to FIG20. FIG20 is a schematic diagram showing a standard cell 2000 including circuit 10, delay cell 100, and delay cell circuit 2010 configured with 100a to 100d relative to FIG1, 2A to 2B, 3A to 3B, 4A to 4C, and 5 to 19, according to various embodiments of the present disclosure.

[0261] As shown in Figure 20, the standard unit 2000 includes a delay unit circuit 2010 and tap units 2001 and 2002. The delay unit circuit 2010 and tap unit 2001 are located in a first voltage domain. For example, the delay unit circuit 2010 is coupled to a supply voltage VDD, which serves as a supply voltage source. The tap unit 2001 couples the supply voltage VDD to the substrate 2020.

[0262] Tap unit 2002 operates in a second voltage domain of the supply voltage VDD2, which is different from (e.g., higher than) the supply voltage VDD in the first voltage domain. Tap unit 2002 couples the supply voltage VDD2 to substrate 2020.

[0263] In some embodiments, tap unit 2002 is located in well W2 at the edge of standard unit 2000. In some embodiments, delay unit circuit 2010 and tap unit 2001 are located in well W1 between wells W2. According to some embodiments, a lower supply voltage to delay unit circuit 2010 helps to improve detection sensitivity and reduce power consumption.

[0264] In some embodiments, the delay unit circuit 2010 is circuit 10. In some embodiments, the delay unit circuit 2010 includes one or more delay units 100 and 100a to 100d of FIG1, FIG2A to FIG2B, FIG3A to FIG3B, FIG4A to FIG4C, and FIG5 to FIG19.

[0265] Referring now to Figures 21A to 21C. Figures 21A to 21C are schematic diagrams showing examples of delay units 2100 configured with delay units 100 and 100a to 100d relative to various embodiments of the present disclosure, according to Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, and 5 to 20.

[0266] As shown in Figures 21A to 21C, the delay unit 2100 includes a p-type semiconductor column and an n-type semiconductor column. The delay unit 2100 abuts against semiconductor columns R1 and R2 (which are p-type or n-type).

[0267] According to various embodiments, a metal boundary effect (MBE) exists between the delay cell 2100 and adjacent semiconductor rows. Specifically, with MBE, the threshold voltages of semiconductor rows R1 and R2 adjacent to the delay cell 2100 affect the performance of the delay cell 2100. According to various embodiments, the threshold voltage here refers to the threshold voltage of the MOS in the corresponding semiconductor row.

[0268] In some embodiments, the semiconductor columns R1 and R2 of the delay unit 2100 are configured to have a specific threshold voltage to reduce the impact of MBE.

[0269] In some embodiments, the delay cell 2100 and columns R1 and R2 are configured to have the same threshold voltage. For example, when the delay cell 2100 has a standard threshold voltage (SVT), the semiconductor columns R1 and R2 are configured to have SVT.

[0270] In some embodiments, the delay unit 2100 and columns R1 and R2 are configured to have threshold voltages from the set of threshold voltages. For example, when the delay unit 2100 has one of the threshold voltages lvt11 and lvt, the semiconductor columns R1 and R2 are configured to have one of the threshold voltages lvt11 and lvt.

[0271] Referring now to Figures 22A to 22C. Figures 22A to 22C are schematic diagrams showing examples of delay unit 2100 in Figures 21A to 21C according to various embodiments of the present disclosure.

[0272] In some embodiments, the delay unit 2100 abuts against a decoupling capacitor DCAP having a specific threshold voltage, as described with reference to Figures 22A to 22C. For example, when the delay unit 2100 has an SVT, the decoupling capacitor DCAP abuts against the delay unit 2100, which includes semiconductor arrays R1 and R2 having an SVT.

[0273] In some embodiments, the cut-off CPO of the gate structure is configured between the delay unit 2100 and the decoupling capacitor DCAP.

[0274] Referring now to Figures 23A to 23C. Figures 23A to 23C are schematic diagrams of standard units 2300a, 2300b, and 2300c configured with delay units 100, 100a to 100d, and 2100 relative to various embodiments of the present disclosure, as shown in Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, 5 to 20, 21A to 21C, and 22A to 22C.

[0275] As shown in Figure 23A, the standard unit 2300a includes a delay unit 2100. The delay unit includes an n-type sensor circuit NS, which includes a ratio inverter 110 and an inverter 120.

[0276] The standard unit 2300a includes a p-type semiconductor column R11 connected to the ratio inverter 110, a p-type semiconductor column R12 connected to the inverter 120, an n-type semiconductor column R21 connected to the ratio inverter 110, and an n-type semiconductor column R22 connected to the inverter 120.

[0277] Ratio inverter 110 and inverter 120 have the same threshold voltage. In some embodiments, ratio inverter 110 and semiconductor columns R11 and R21 are configured to have the same threshold voltage or threshold voltages from the set of threshold voltages.

[0278] According to various embodiments, when the threshold voltage of the semiconductor column of the delay unit 2100 increases, the speed of the MOS in the semiconductor column of the delay unit 2100 decreases. When the threshold voltage of the semiconductor column of the delay unit 2100 decreases, the speed of the MOS in the semiconductor column of the delay unit 2100 increases.

[0279] When the speed of the PMOS in inverter 120 increases while the speed of the NMOS in inverter 120 decreases, the sensitivity of the n-type sensor circuit NS increases.

[0280] Therefore, the threshold voltage configuration of semiconductor array R12 is lower than the threshold voltage of inverter 120, thereby improving the sensitivity of n-type sensor circuit NS.

[0281] The threshold voltage configuration of semiconductor array R22 is higher than the threshold voltage of inverter 120, thereby improving the sensitivity of n-type sensor circuit NS.

[0282] In summary, the sensitivity of the n-type sensor circuit NS is directly proportional to the threshold voltage of semiconductor column R22 and inversely proportional to the threshold voltage of semiconductor column R12.

[0283] As shown in Figure 23B, the standard unit 2300b includes a delay unit 2100. The delay unit includes a p-type sensor circuit PS, which includes a ratio inverter 130 and an inverter 120.

[0284] The standard unit 2300a includes a p-type semiconductor column R11 connected to the ratio inverter 130, a p-type semiconductor column R12 connected to the inverter 120, an n-type semiconductor column R21 connected to the ratio inverter 130, and an n-type semiconductor column R22 connected to the inverter 120.

[0285] Ratio inverter 130 has the same threshold voltage as inverter 120. In some embodiments, ratio inverter 130 and semiconductor columns R11 and R21 are configured to have the same threshold voltage or threshold voltages from the set of threshold voltages.

[0286] When the speed of the NMOS in inverter 120 increases and the speed of the PMOS in inverter 120 decreases, the sensitivity of the p-type sensor circuit PS increases.

[0287] Therefore, the threshold voltage configuration of semiconductor array R12 is higher than the threshold voltage of inverter 120, thereby improving the sensitivity of p-type sensor circuit PS.

[0288] The threshold voltage configuration of semiconductor array R22 is lower than the threshold voltage of inverter 120, thereby improving the sensitivity of the p-type sensor circuit PS.

[0289] In summary, the sensitivity of the p-type sensor circuit PS is directly proportional to the threshold voltage of semiconductor column R12 and inversely proportional to the threshold voltage of semiconductor column R22.

[0290] As shown in Figure 23C, the standard unit 2300c includes two delay units 2100. One delay unit includes an n-type sensor circuit NS, which includes a ratio inverter 110 and an inverter 120. The other delay unit includes a p-type sensor circuit PS, which includes a ratio inverter 130 and an inverter 120.

[0291] The standard unit 2300c includes a p-type semiconductor column R11 connected to the ratio inverter 130, a p-type semiconductor column R12 connected to the inverter 120, an n-type semiconductor column R21 connected to the ratio inverter 130, and an n-type semiconductor column R22 connected to the inverter 120.

[0292] The standard unit 2300c includes a p-type semiconductor column R31 connected to the ratio inverter 110, a p-type semiconductor column R32 connected to the inverter 120, an n-type semiconductor column R41 connected to the ratio inverter 110, and an n-type semiconductor column R42 connected to the inverter 120.

[0293] In some embodiments, semiconductor columns R22 and R32 have the same threshold voltage. To obtain better sensitivity, the threshold voltages of semiconductor columns R22 and R32 are lower than the threshold voltage of inverter 120.

[0294] Semiconductor arrays R12 and R42 have the same threshold voltage. The threshold voltages of semiconductor arrays R12 and R42 are higher than the threshold voltage of inverter 120 for better sensitivity.

[0295] Referring now to FIG24. FIG24 is a schematic diagram of a standard unit 2400 configured with delay units 100, 100a to 100d and 2100 relative to FIG1, 2A to 2B, 3A to 3B, 4A to 4C, 5 to 20, 21A to 21C, 22A to 22C and 23A to 23C, according to various embodiments of the present disclosure.

[0296] Standard cell 2400 includes delay cell 2100, which includes p-type semiconductor columns and n-type semiconductor columns. According to various embodiments, the length of the gate structure adjacent to delay cell 2100 affects the speed of the MOS in delay cell 2100.

[0297] In some embodiments, the standard cell 2400 includes a filler 2401 that abuts against the delay cell 2100. The length of the gate structure of the filler 2401 is configured to be equal to the height of the delay cell 2100 along the direction y (i.e., the height of the p-type semiconductor column and the n-type semiconductor column) to reduce the impact on the speed of the MOS in the delay cell 2100.

[0298] Referring now to Figures 25A to 25B. Figures 25A to 25B are schematic diagrams of standard units 2500a and 2500b configured with delay units 100, 100a to 100d and 2100 according to various embodiments of the present disclosure, relative to Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, 5 to 20, 21A to 21C, 22A to 22C, 23A to 23C, and 24.

[0299] As shown in FIG25A, the standard unit 2500a includes a delay unit 2100, which includes a ratio inverter 130 and a p-type sensor circuit PS of an inverter 120. In some embodiments, the standard unit 2500a further includes fillers 2501 and 2502.

[0300] In some embodiments, as shown in FIG25A, the gate structure along the direction y is cut by a gate-cut CPO.

[0301] In some embodiments, the filler 2501 abutting the inverter 120 has a gate structure having a length twice the height of the delay cell 2100 along the y-direction. For example, the height of the delay cell 2100 is equal to the height of two semiconductor columns, and the length of the gate structure of the filler 2501 is equal to the height of four semiconductor columns.

[0302] Filler 2501 is used to reduce the speed of PMO in the p-type semiconductor column of inverter 120 in order to further improve the sensitivity of delay cell 2100.

[0303] As shown in FIG25B, the standard unit 2500b includes a delay unit 2100, which includes a ratio inverter 130 and a p-type sensor circuit PS of an inverter 120. In some embodiments, the standard unit 2500b further includes fillers 2501 and 2502.

[0304] In some embodiments, as shown in FIG25B, the gate structure along the direction y is cut by a gate-cut CPO.

[0305] In some embodiments, the filler 2501 abutting the inverter 120 has a gate structure having a length that is twice the height of the delay unit 2100 along the y direction.

[0306] Filler 2501 is used to increase the speed of the NMOS in the N-type semiconductor column of inverter 120, so as to further improve the sensitivity of delay cell 2100.

[0307] For the embodiments of standard cells 2500a and 2500b that include a delay cell 2100 with a p-type sensor circuit PS, in Figures 25A and 25B, the ratio inverter 110 is replaced by the ratio inverter 130, and the conductivity type of each semiconductor is switched from P to N or from N to P.

[0308] Referring now to FIG. 26. FIG. 26 is a flowchart of a method 2600 for detecting carrier mobility or internal stress according to some embodiments of the present disclosure. It should be understood that, for additional embodiments of the method, additional operations may be provided before, during, and after the operations shown in FIG. 10, and some of the operations described below may be replaced or eliminated. The order of operations may be interchanged. Some of the operations are performed simultaneously. Method 2600 includes operations 2601 to 2605 described below with reference to FIG. 1, FIG. 2A to 2B, FIG. 3A to 3B, FIG. 4A to 4C, FIG. 5 to 20, FIG. 21A to 21C, FIG. 22A to 22C, FIG. 23A to 23C, FIG. 24, and FIG. 25A to 25B.

[0309] In operation 2601, delay unit 100 receives an input signal. For example, transistor t52 receives the input signal via its gate terminal.

[0310] In operation 2602, delay unit 100 generates a first signal based on the input signal. For example, diode-connected transistors t51 and t52 generate the first signal at a first node, wherein the source / drain terminals of transistor t51 are coupled to the drain / source terminals of transistor t52.

[0311] In operation 2603, delay unit 100 pulls up the voltage signal according to the first signal. For example, transistor t53, coupled between the supply voltage VDD and the output terminal O, turns on transistor t52 according to the first signal to pull up the voltage signal at the output terminal O.

[0312] In operation 2604, delay unit 100 pulls down the voltage signal according to the first signal. For example, transistor t54, coupled between the supply voltage VSS and the output terminal O, turns off transistor t52 according to the first signal, thereby pulling down the voltage signal at the output terminal O.

[0313] In operation 2604, the carrier mobility of the wafer including the delay unit 100 is determined. For example, the delay unit 100 generates a voltage signal at output terminal O, wherein the frequency of the voltage signal indicates the carrier mobility. In some embodiments, logic circuitry (not shown) coupled to the delay unit 100 may determine the carrier mobility based on the frequency.

[0314] In some embodiments, the frequency of the voltage signal indicates the internal stress in the wafer. In some embodiments, logic circuitry (not shown) coupled to the delay unit 100 can determine the internal stress based on the frequency.

[0315] Referring now to FIG. 27. FIG. 27 is a block diagram of an electronic design automation (EDA) system 2700 for designing integrated circuit layout designs according to some embodiments of the present disclosure. The EDA system 2700 is used to implement the layout designs disclosed in FIG. 8 to FIG. 10, FIG. 17 to FIG. 20, FIG. 21A to FIG. 21C, FIG. 23A to FIG. 23C, FIG. 24, and FIG. 25A to FIG. 25B.

[0316] In some embodiments, the EDA system 2700 is a general-purpose computing device including a hardware processor 2720 and a non-transitory computer-readable storage medium 2760. Among other things, the storage medium 2760 is also encoded, i.e., stores instructions (computer program code) 2761, i.e., a set of executable instructions. Execution of the instructions 2761 by the hardware processor 2720 represents (at least partially) an EDA tool that implements some or all of the methods for implementing layout design disclosed, for example, in Figures 8-10, 17-20, 21A-21C, 23A-23C, 24, and 25A-25B.

[0317] Processor 2720 is electrically coupled to storage medium 2760 via bus 2750. Processor 2720 is also electrically coupled to input / output (I / O) interface 2710 and manufacturing tool 2770 via bus 2750. Network interface 2730 is also electrically connected to processor 2720 via bus 2750. Network interface 2730 is connected to network 2740, enabling processor 2720 and storage medium 2760 to be connected to external components via network 2740. Processor 2720 is used to execute instructions 2761 encoded in storage medium 2760 to enable EDA system 2700 to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 2720 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0318] In one or more embodiments, the storage medium 2760 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the storage medium 2760 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the storage medium 2760 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0319] In one or more embodiments, storage medium 2760 stores instructions 2761 that enable EDA system 2700 (wherein this execution representation (at least partially) EDA tools) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 2760 also stores information that facilitates the performance of part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 2760 stores a standard cell library 2762, including the standard cells disclosed herein, for example, the standard cells in Figures 20, 21A-21C, 23A-23C, 24, and 25A-25B.

[0320] EDA system 2700 includes I / O interface 2710. I / O interface 2710 is coupled to an external circuit system. In one or more embodiments, I / O interface 2710 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or directional keys for conveying information and commands to processor 2720.

[0321] EDA system 2700 also includes a network interface 2730 coupled to processor 2720. Network interface 2730 allows EDA system 2700 to communicate with a network 2740 to which one or more other computer systems are connected. Network interface 2730 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more EDA systems 2700.

[0322] The EDA system 2700 also includes a manufacturing tool 2770 coupled to the processor 2720. The manufacturing tool 2770 is used to manufacture integrated circuits, such as those shown in Figures 1, 2A to 2B, 3A to 3B, 4A to 4C, 5 to 7, and 11 to 15, based on design documents processed by the processor 2720.

[0323] EDA system 2700 receives information via I / O interface 2710. The information received via I / O interface 2710 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 2720. The information is transferred to processor 2720 via bus 2750. EDA system 2700 also receives information related to the user interface (UI) via I / O interface 2710. This information is stored as user interface (UI) 2763 in computer-readable storage medium 2760.

[0324] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by EDA system 2700. In some embodiments, the layout diagram including standard cells uses, for example, a layout diagram available from CADENCE DESIGN SYSTEMS, Inc. Use a tool or another suitable layout generator to generate it.

[0325] In some embodiments, these processes are implemented as the functionality of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or storage units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs, RAMs, memory cards), and one or more of the like.

[0326] Figure 28 is a block diagram of an IC manufacturing system 2800 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the IC manufacturing system 2800 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0327] In Figure 28, the IC manufacturing system 2800 includes entities such as design room 2810, mask room 2820, and IC manufacturer / wafer fab (“fab”) 2830, which interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 2840. The entities in the IC manufacturing system 2800 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities, providing services to and / or receiving services from one or more other entities. In some embodiments, two or more of the design room 2810, mask room 2820, and IC wafer fab 2830 are owned by a single larger company. In some embodiments, two or more of the design room 2810, mask room 2820, and IC wafer fab 2830 coexist in a shared facility and use shared resources.

[0328] Design studio (or design team) 2810 generates IC design layout 2811. IC design layout 2811 includes various geometric patterns, for example, the IC layout designs depicted in Figures 8-10, Figures 17-20, Figures 21A-21C, Figures 23A-23C, Figure 24, and Figures 25A-25B. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 2840 to be manufactured. Various layers are combined to form various IC features. For example, a portion of IC design layout 2811 includes various IC features such as active regions, gate electrodes, source and drain electrodes, conductive segments or vias for interlayer interconnects to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers disposed on the semiconductor substrate. Design studio 2810 implements appropriate design procedures to form IC design layout 2811. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout diagram 2811 is presented in the form of one or more data files containing information about geometric patterns. For example, IC design layout diagram 2811 can be expressed in GDSII file format or DFII file format.

[0329] Masking chamber 2820 includes data preparation 2821 and mask fabrication 2822. Masking chamber 2820 uses an IC design layout 2811 to fabricate one or more masks 2823 for use in fabricating various layers in an IC device 2840 according to the IC design layout 2811. Masking chamber 2820 performs mask data preparation 2821, in which the IC design layout 2811 is translated into a representative data file (RDF). Mask data preparation 2821 provides the RDF to mask fabrication 2822. Mask fabrication 2822 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 2823 or a semiconductor wafer 2832. The IC design layout 2811 is controlled by mask data preparation 2821 to conform to the specific characteristics of the mask writer and / or the requirements of the IC wafer fab 2830. In Figure 28, data preparation 2821 and mask manufacturing 2822 are illustrated as separate elements. In some embodiments, data preparation 2821 and mask manufacturing 2822 may be collectively referred to as mask data preparation.

[0330] In some embodiments, data preparation 2821 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as those that can cause self-diffraction, interference, other process effects, and the like. OPC adjustment IC design layout diagram 2811 is shown. In some embodiments, data preparation 2821 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0331] In some embodiments, data preparation 2821 includes checking an IC design layout 2811 using a mask rule checker (MRC) that has undergone processing in an OPC using a set of mask generation rules, which contain certain geometric and / or connectivity constraints to ensure sufficient margin, take into account variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 2811 to compensate for constraints during mask manufacturing 2822, which may undo modifications performed via the OPC to satisfy the mask generation rules.

[0332] In some embodiments, data preparation 2821 includes lithography process checking (LPC), which simulates the process to be performed by IC wafer fab 2830 to manufacture IC device 2840. LPC simulates this process based on IC design layout 2811 to produce a simulated manufactured device, such as IC device 2840. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after the simulated manufactured device has been produced by LPC, if the simulated device does not sufficiently approximate the design rules in shape, OPC and / or MRC are repeated to further refine the IC design layout 2811.

[0333] It should be understood that the above description of data preparation 2821 has been simplified for clarity. In some embodiments, data preparation 2821 includes additional features, such as modifying the logic operation (LOP) of IC design layout 2811 according to manufacturing rules. Additionally, the processes applied to IC design layout 2811 during data preparation 2821 can be performed in a variety of different sequences.

[0334] Following data preparation 2821 and during mask manufacturing 2822, mask 2823 or a group of masks 2823 is manufactured based on a modified IC design layout 2811. In some embodiments, mask manufacturing 2822 includes performing one or more lithography exposures based on IC design layout 2811. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to pattern the mask (photomask or master photomask) 2823 based on the modified IC design layout 2811. Mask 2823 can be formed using various techniques. In some embodiments, mask 2823 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., a photoresist layer) coated on the wafer, is blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of mask 2823 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 2823 is formed using a phase shift mask (PSM) technique. In the phase shift mask (PSM) version of mask 2823, various features in the pattern formed on the phase shift mask are used to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuating PSM or an alternating PSM. The mask produced by mask fabrication 2822 is used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 2832, in etching processes to form various etched regions in semiconductor wafer 2832, and / or in other suitable processes.

[0335] IC wafer fab 2830 includes wafer fabrication 2831. IC wafer fab 2830 is an IC manufacturing business, including one or more manufacturing facilities that manufacture a variety of different IC products. In some embodiments, IC wafer fab 2830 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end-of-line (FEOL) manufacturing of multiple IC products, a second manufacturing facility that provides back-end-of-line (BEOL) manufacturing for interconnection and packaging of IC products, and a third manufacturing facility that provides other services for the foundry business.

[0336] IC wafer fab 2830 manufactures IC device 2840 using multiple masks 2823 fabricated via mask chamber 2820. Therefore, IC wafer fab 2830 at least indirectly uses IC design layout 2811 to manufacture IC device 2840. In some embodiments, semiconductor wafer 2833 is fabricated by IC wafer fab 2830 using multiple masks 2823 to form IC device 2840. In some embodiments, IC fabrication includes performing one or more lithography exposures at least indirectly based on IC design layout 2811. Semiconductor wafer 2833 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 2833 further includes various doped regions, dielectric features, multilevel interconnects, and one or more of the like (formed in subsequent fabrication steps).

[0337] As described above, a circuit, semiconductor device, and method for detecting carrier mobility or internal stress are provided. In the provided circuit, semiconductor device, and method, a switching circuit indicating a sleep mode is used to reduce power consumption. Furthermore, a mismatch design for delay cells is provided to improve detection sensitivity. By improving sensitivity, the number of stages of delay cells used for detection can be reduced while maintaining detection accuracy. As a result, area usage and current leakage can be reduced.

[0338] In some embodiments, a circuit is provided. The circuit includes a series of delay units coupled in series and logic gates. Each delay unit includes an inverter and a switch. The inverter generates an output signal based on an input signal. The switch is coupled between a first supply voltage and the inverter. The switch provides the first supply voltage to the inverter based on a first control signal. The logic gates transmit the output signal of the last delay unit in the series to the first delay unit in the series as an input signal. A frequency of the output signal of the last delay unit indicates a carrier mobility of the circuit.

[0339] In some embodiments, the inverter includes a first transistor and a second transistor connected in series between the switch and a second supply voltage, wherein a gate terminal of the first transistor is coupled to the input signal. The delay unit further includes a third transistor coupled between the input signal and a gate terminal of the second transistor.

[0340] In some embodiments, the inverter includes a plurality of first transistors and a plurality of second transistors. The plurality of first transistors are coupled between a switch and an output signal, wherein a plurality of gate terminals of the plurality of first transistors are coupled to an input signal. The plurality of second transistors are coupled between a second supply voltage and the output signal. The delay unit further includes a third transistor coupled between the input signal and a plurality of gate terminals of the plurality of second transistors.

[0341] In some embodiments, the inverter includes a first transistor and a second transistor connected in series between the switch and a second supply voltage. A gate terminal of the first transistor and a gate terminal of the second transistor are coupled to the input signal. The delay unit further includes a third transistor having a gate terminal coupled to the switch. The third transistor is used to turn on to forward the output signal.

[0342] In some embodiments, the inverter includes a plurality of first transistors and a plurality of second transistors. The plurality of first transistors are coupled between a switch and an output signal. The plurality of second transistors are coupled between a second supply voltage and the output signal. A plurality of gate terminals of each of the plurality of first transistors and each of the plurality of second transistors are coupled to an input signal. The delay unit further includes a third transistor. The third transistor has a gate terminal coupled to a switch, wherein the third transistor is turned on to forward the output signal.

[0343] In some embodiments, the delay unit further includes a ratio inverter and a gate terminal. The ratio inverter includes a first transistor having a gate terminal coupled to an input signal. A second transistor has a gate terminal coupled to a switch, and the first and second transistors are together coupled to an input terminal of the inverter.

[0344] In some embodiments, the inverter includes a third transistor and a fourth transistor. The third transistor is coupled between the switch and the output signal. The fourth transistor is coupled between the output signal and a second supply voltage. Multiple gate terminals of the third and fourth transistors are coupled together as input terminals.

[0345] In some embodiments, the first transistor, the second transistor, and the fourth transistor have a first conductivity type, and the third transistor has a second conductivity type different from the first conductivity type.

[0346] In some embodiments, the frequency indication of the output signal of the final delay unit corresponds to a carrier mobility of the first conductivity type.

[0347] In some embodiments, the inverter includes a plurality of third transistors and a plurality of fourth transistors. The plurality of third transistors are coupled between the switch and the output signal. The plurality of fourth transistors are coupled between the output signal and a second supply voltage. The gate terminals of the plurality of third and fourth transistors are coupled together as input terminals. The number of the plurality of third transistors differs from the number of the plurality of fourth transistors.

[0348] In some embodiments, the inverter includes a plurality of third transistors and a plurality of fourth transistors. The plurality of third transistors are connected in parallel between the switch and the output signal. The plurality of fourth transistors are connected in series between the output signal and the second supply voltage. The plurality of gate terminals of the plurality of third and fourth transistors are coupled together as input terminals.

[0349] In some embodiments, a semiconductor device is provided. The semiconductor device includes a delay unit. The delay unit includes an inverter and a ratio inverter. The inverter includes a first pull-up circuit and a first pull-down circuit. The first pull-up circuit is coupled between a first supply voltage and an output terminal. The first pull-down circuit is coupled between a second supply voltage and an output terminal. The ratio inverter includes a first transistor coupled to an input terminal of the inverter and has a gate terminal coupled to a first signal. The delay unit generates a second signal at the output terminal based on the first signal. The frequency of the second signal indicates the carrier mobility of the semiconductor device.

[0350] In some embodiments, the first pull-up circuit includes a plurality of second transistors connected in series between the first supply voltage and the output terminal. Multiple gate terminals of the plurality of second transistors are coupled to the input terminal.

[0351] In some embodiments, the inverter further includes a second pull-up circuit. The first and second pull-up circuits are coupled in parallel between the first supply voltage and the output terminal.

[0352] In some embodiments, the first pull-down circuit includes a plurality of second transistors. The plurality of second transistors are connected in series between a second supply voltage and an output terminal. A plurality of gate terminals of the plurality of second transistors are coupled to an input terminal. The first transistor has a first conductivity type, and the frequency of the second signal indicates the carrier mobility corresponding to the first conductivity type.

[0353] In some embodiments, the semiconductor device further includes a first well and a second well. The first well includes a delay unit and a first tap unit coupled to a first supply voltage. The second well is adjacent to the first well and includes a second tap unit coupled to a third supply voltage higher than the first supply voltage.

[0354] In some embodiments, the semiconductor device further includes a first semiconductor column and a second semiconductor column abutting against an inverter. A first threshold voltage of the first semiconductor column is higher than a second threshold voltage of the inverter. A third threshold voltage of the second semiconductor column is lower than the second threshold voltage.

[0355] In some embodiments, the semiconductor device further includes a filler. The filler abuts against the inverter along a first direction, wherein the filler includes a plurality of gate structures that are longer than a width of the inverter along a second direction perpendicular to the first direction.

[0356] In some embodiments, an operating method is provided. The operating method includes: receiving an input signal via a gate terminal of a first transistor; generating a first signal at a first node between the first transistor and a diode-connected second transistor based on the input signal; pulling up a voltage signal at an output terminal via a plurality of third transistors of an inverter based on the first signal, wherein the third transistors are coupled between a first supply voltage and the output terminal; pulling down the voltage signal via a plurality of fourth transistors of an inverter based on the first signal, wherein the fourth transistors are coupled between a second supply voltage and the output terminal, wherein the number of third transistors is different from the number of fourth transistors; and determining the carrier mobility of a wafer based on the frequency of the voltage signal.

[0357] In some embodiments, the operating method further includes the step of determining an internal stress of the wafer based on the frequency of a voltage signal.

[0358] In some embodiments, an integrated circuit is provided. The integrated circuit includes a series of multiple delay units coupled in series and logic gates. Each delay unit includes an inverter and a switch. The inverter generates an output signal based on an input signal. The switch is coupled between a first supply voltage and the inverter. The switch provides the first supply voltage to the inverter based on a first control signal. The logic gates transmit the output signal of the last delay unit in the series to the first delay unit in the series as an input signal. A frequency of the output signal of the last delay unit indicates a carrier mobility of the circuit. The inverter includes a first transistor and a second transistor coupled in series between the switch and a second supply voltage, the gate terminals of the first transistor and the second transistor being coupled to the input signal, wherein the delay unit further includes a third transistor having a gate terminal coupled to the switch, wherein the third transistor is turned on to forward the output signal.

[0359] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of the embodiments disclosed herein. Those skilled in the art will understand that the embodiments disclosed herein can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same benefits. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments disclosed herein, and that such equivalent constructions can be modified, substituted, and replaced in various ways without departing from the spirit and scope of the embodiments disclosed herein.

Claims

1. An integrated circuit, characterized in that, The circuit comprises: a series of multiple delay units coupled in series, each of the multiple delay units comprising: an inverter for generating an output signal based on an input signal; a switch coupled between a first supply voltage and the inverter, wherein the switch provides the first supply voltage to the inverter based on a first control signal; and a logic gate for transmitting the output signal of a last delay unit in the series to a first delay unit in the series as the input signal, wherein a frequency of the output signal of the last delay unit indicates a carrier mobility of the circuit.

2. The integrated circuit as described in claim 1, characterized in that, The inverter includes a first transistor and a second transistor connected in series between the switch and a second supply voltage, wherein a gate terminal of the first transistor is coupled to the input signal, and the delay unit further includes a third transistor coupled between the input signal and a gate terminal of the second transistor.

3. The integrated circuit as described in claim 1, characterized in that, The inverter includes: a plurality of first transistors coupled between the switch and the output signal, wherein a plurality of gate terminals of the plurality of first transistors are coupled to the input signal; and a plurality of second transistors coupled between a second supply voltage and the output signal, wherein the delay unit further includes: a third transistor coupled between the input signal and a plurality of gate terminals of the plurality of second transistors.

4. The integrated circuit as described in claim 1, characterized in that, The delay unit further includes: a ratio inverter, which includes: a first transistor having a gate terminal coupled to the input signal; and a second transistor having a gate terminal coupled to the switch, wherein the first and second transistors are together coupled to an input terminal of the inverter.

5. A semiconductor device, characterized in that, The device comprises: a delay unit, which includes: an inverter, which includes: a first pull-up circuit coupled between a first supply voltage and an output terminal; and a first pull-down circuit coupled between a second supply voltage and the output terminal; and a ratio inverter, which includes: a first transistor coupled to an input terminal of the inverter and having a gate terminal coupled to a first signal, wherein the delay unit is configured to generate a second signal at the output terminal according to the first signal, wherein a frequency of the second signal indicates a carrier mobility of the semiconductor device.

6. The semiconductor device as claimed in claim 5, characterized in that, The inverter further includes: a second pull-up circuit, wherein the first pull-up circuit and the second pull-up circuit are coupled in parallel between the first supply voltage and the output terminal, wherein the first pull-down circuit includes: a plurality of second transistors, which are coupled in series between the second supply voltage and the output terminal, wherein a plurality of gate terminals of the plurality of second transistors are coupled to the input terminal, wherein the first transistor has a first conductivity type, and the frequency indication of the second signal corresponds to the carrier mobility of the first conductivity type.

7. The semiconductor device as claimed in claim 5, characterized in that, It further includes: a first well, which includes the delay unit and a first tap unit coupled to the first supply voltage; and a second well adjacent to the first well, wherein the second well includes a second tap unit coupled to a third supply voltage higher than the first supply voltage.

8. The semiconductor device as claimed in claim 5, characterized in that, It further includes: a first semiconductor column and a second semiconductor column abutting the inverter, wherein a first threshold voltage of the first semiconductor column is higher than a second threshold voltage of the inverter, and a third threshold voltage of the second semiconductor column is lower than the second threshold voltage.

9. The semiconductor device as claimed in claim 5, characterized in that, It further includes: a filler abutting the inverter along a first direction, wherein the filler includes a plurality of gate structures, the plurality of gate structures being longer than a width of the inverter along a second direction perpendicular to the first direction.

10. An integrated circuit, characterized in that, The circuit comprises: a series of multiple delay units coupled in series, each of the multiple delay units comprising: an inverter for generating an output signal based on an input signal; a switch coupled between a first supply voltage and the inverter, wherein the switch provides the first supply voltage to the inverter based on a first control signal; and a logic gate for transmitting the output signal of a last delay unit in the series to a first delay unit in the series as the input signal, wherein a frequency of the output signal of the last delay unit indicates a carrier mobility of the circuit, wherein the inverter comprises: a first transistor and a second transistor coupled in series between the switch and a second supply voltage, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to the input signal, wherein the delay unit further comprises: a third transistor having a gate terminal coupled to the switch, wherein the third transistor is turned on to forward the output signal.

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