SRAM (Static Random Access Memory) test structure and layout structure
By setting the active regions of the second selection transistor and the external selection transistor to an electrically isolated state in the SRAM test structure, the problem of inaccurate gate tunneling leakage current testing is solved, achieving higher test accuracy and reliability of subsequent analysis.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- QINGDAO YUNLIAN ZHIXIANG INFORMATION TECHNOLOGY CO LTD
- Filing Date
- 2025-04-24
- Publication Date
- 2026-05-01
AI Technical Summary
In the prior art, the gate tunneling leakage current test of SRAM devices is inaccurate and can easily interfere with subsequent leakage current analysis.
An SRAM test structure was designed. By setting the active regions of the second selection transistor and the external selection transistor to an electrically isolated state, their influence on the gate tunneling leakage current under test is eliminated. This structure is used to perform accurate gate tunneling leakage current testing.
This improves the accuracy of gate tunneling leakage current testing, reduces noise interference, and facilitates subsequent leakage current analysis.
Smart Images
Figure CN224192416U_ABST
Abstract
Description
SRAM test structure and layout structure Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to an SRAM test structure and layout structure. Background Technology
[0002] Static Random-Access Memory (SRAM) is a type of memory that allows for static access without requiring a refresh circuit. It offers advantages such as large capacity and faster read speeds than Dynamic Random-Access Memory (DRAM). SRAM is widely used in PCs, personal communications, and consumer electronics (smart cards, digital cameras, multimedia players) due to its high speed, low power consumption, and compatibility with standard manufacturing processes.
[0003] The static power consumption of SRAM devices mainly includes gate-tunnel leakage current (Iginv), gate-induced drain leakage current (GIDL), and subthreshold leakage current. Gate-tunnel leakage current (Iginv) is formed when charge on the gate tunnels through the gate oxide layer into the substrate. As device dimensions continue to shrink, the gate oxide layer thickness also decreases, leading to a rapid increase in gate leakage current and thus affecting the device's static power consumption. Therefore, monitoring the gate-tunnel leakage current is necessary throughout the research, development, and mass production of SRAM devices.
[0004] However, the current method of directly electrically drawing the gate tunneling leakage current from the SRAM cell not only often results in inaccurate testing, but also causes significant interference to subsequent leakage current analysis. Summary of the Invention
[0005] The purpose of this invention is to provide an SRAM test structure and layout structure for accurately measuring the gate tunneling leakage current of transistors in SRAM.
[0006] To solve the above-mentioned technical problems, the SRAM test structure provided in this application includes a second selection transistor, an external selection transistor, and a first pull-down transistor for the gate tunneling leakage current to be tested. The second selection transistor and the first pull-down transistor are located in a first memory cell, and the external selection transistor is located in a second memory cell adjacent to the first memory cell. The gate of the second selection transistor, the gate of the external selection transistor, and the gate of the second selection transistor are all connected.
[0007] The active regions of the second selection transistor and the external selection transistor are electrically isolated.
[0008] Optionally, both the first and second memory cells are 6T structures, and the drain of the second selection transistor is connected to the gate of the first pull-down transistor.
[0009] Optionally, the SRAM test structure is disposed on a P-type substrate, and the first pull-down transistor includes a P-type active region and a plug, wherein the P-type active region is located in the P-type substrate, and the plug is electrically led out of the P-type active region.
[0010] Optionally, the second selection transistor includes a first P-type active region and a first N-type deep well region, wherein the first N-type deep well region is located in the P-type substrate, and the first P-type active region is located in the first N-type deep well region.
[0011] The external selection transistor includes a second P-type active region and a second N-type deep well region, wherein the second N-type deep well region is located in the P-type substrate and the second P-type active region is located in the second N-type deep well region.
[0012] Optionally, the first N-type deep well region and the second N-type deep well region have the same doping concentration and doping depth.
[0013] Optionally, the second selection transistor includes a first P-type active region located in the P-type substrate, and the first P-type active region is not electrically exposed.
[0014] The external selection transistor includes a second P-type active region located in the P-type substrate, and the second P-type active region is not electrically exposed.
[0015] Optionally, neither the first P-type active region nor the second P-type active region is provided with a plug for electrical lead-out.
[0016] Optionally, both the first P-type active region and the second P-type active region are provided with a second plug, which is not connected to the VSS.
[0017] Optionally, both the first and second memory cells are 8T structures and are arranged adjacent to each other. The first memory cell includes a first selection transistor, a second selection transistor, and a first pull-down transistor for measuring gate tunneling leakage current. The second memory cell includes two external selection transistors. The gates of the two external selection transistors, the gate of the second selection transistor, and the gate of the first selection transistor are connected to the gate of the first pull-down transistor. The active regions of the second selection transistor, the first selection transistor, and the two external selection transistors are electrically isolated.
[0018] Based on another aspect of this application, a layout structure is also provided, including the SRAM test structure described above. Attached Figure Description
[0019] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the present invention. Wherein:
[0020] Figure 1A is a circuit diagram of an SRAM storage cell provided in an embodiment of this application;
[0021] Figure 1B is a schematic layout diagram of the SRAM test structure provided in an embodiment of this application;
[0022] Figure 2A is a schematic diagram of the first pull-down transistor, the second selection transistor, and the external selection transistor provided in an embodiment of this application;
[0023] Figure 2B is a schematic diagram of the first pull-down transistor, the second selection transistor, and the external selection transistor provided in the embodiments of this application;
[0024] Figure 3A is a circuit diagram of an SRAM memory cell provided in an embodiment of this application;
[0025] Figure 3B is a schematic diagram of the SRAM test structure provided in an embodiment of this application.
[0026] In the attached image:
[0027] 11-First memory cell; 12-Second memory cell; 13-First gate pattern; 14-Second gate pattern; 15-First plug; PD1-First pull-down transistor; PD2-Second pull-down transistor; PU1-First pull-up transistor; PU2-Second pull-up transistor; PG-External select transistor; PG1-First select transistor; PG2-Second select transistor; PG3-Third select transistor; PG4-Fourth select transistor; 20-Substrate; 21-Gate structure; 22-Source / drain structure; 23-P-type active region; 24-First P-type active region; 25-First N-type deep well region; 26-Second P-type active region; 27-Second N-type deep well region; 28-Isolation structure; WL1-First word line; WL2-Second word line; WL-Word line; X-First direction; Y-Second direction. Detailed Implementation
[0028] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales.
[0029] It should be understood that when an element or layer is referred to as "on" or "connected to" other elements or layers, it may be directly on or connected to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on" or "directly connected to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. Spatial relation terms such as "below," "under," "below," "above," "on top," "above," etc., may be used herein for convenience of description to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relational terms are intended to also include different orientations of the devices in use and operation. For example, if the devices in the figures are flipped, then elements or features described as “below,” “under,” or “below” will be oriented “on” other elements or features. Devices may be oriented additionally (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly. The terminology used herein is intended only to describe particular embodiments and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “comprising” is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the terms “and / or” include any and all combinations of the associated listed items.
[0030] This application provides an SRAM test structure.
[0031] Figure 1A is a circuit diagram of the SRAM storage cell provided in an embodiment of this application.
[0032] As shown in Figure 1A, the SRAM memory cell provided in this embodiment of the application can be a 6T structure, including a first selection transistor PG1, a second selection transistor PG2, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, and a second pull-down transistor PD2. The first selection transistor PG1, the second selection transistor PG2, the first pull-down transistor PD1, and the second pull-down transistor PD2 can be NMOS transistors, and the first pull-up transistor PU1 and the second pull-up transistor PU2 can be PMOS transistors. The first pull-up transistor PU1 and the first pull-down transistor PD1 form one of a cross-coupled inverter (the first inverter), and the second pull-up transistor PU2 and the second pull-down transistor PD2 form the other cross-coupled inverter (the second inverter). The gates of both the first selection transistor PG1 and the second selection transistor PG2 are connected to the word line WL. The drain of the first selection transistor PG1 is connected to the gate of the second inverter, and the drain of the second selection transistor PG2 is connected to the gate of the first inverter. The source of the first selection transistor PG1 is connected to the first bit line, and the source of the second selection transistor PG2 is connected to the second bit line.
[0033] Figure 1B is a schematic diagram of the SRAM test structure provided in an embodiment of this application.
[0034] As shown in Figure 1B, the SRAM test structure provided in this embodiment includes at least two adjacent SRAM memory cells, namely a first memory cell 11 and a second memory cell 12. Both the first memory cell 11 and the second memory cell 12 can be the aforementioned 6T structure, and they are arranged adjacent to each other along the gate extension direction. Taking the transistor to be tested for gate tunneling leakage current as the first pull-down transistor PD1 of the first memory cell 11 as an example, the test structure may include two gate patterns extending along the first direction X, namely a first gate pattern 13 and a second gate pattern 14. The first gate pattern 13 and the second gate pattern 14 are arranged at intervals along the second direction Y, and the first direction X and the second direction Y are orthogonal. Along the extension direction (first direction X) of the first gate pattern 13, the external selection transistor PG of the second memory cell 12, the second selection transistor PG2 of the first memory cell 11, the first pull-up transistor PU1, and the first pull-down transistor PD1 are sequentially arranged. Along the extension direction of the second gate pattern 14, the second pull-up transistor PU2 and the second pull-down transistor PD2 of the first memory cell 11 are sequentially arranged. The connection method of the above transistors can be referred to the memory cell in Figure 1A. It should be noted that, unlike the circuit diagram of the aforementioned SRAM memory cell, in the SRAM test structure of this application, the first gate pattern 13 is also connected to the gates of the second selection transistor PG2 and the first pull-up transistor PU1, and the second gate pattern 14 is also connected to the gates of the first selection transistor PG1 and the second pull-up transistor PU2. In other words, the first gate pattern 13 is sequentially connected to the gates of the external selection transistor PG, the second selection transistor PG2, the first pull-up transistor PU1, and the first pull-down transistor PD1 under test. Among them, the gate of the external selection transistor PG of the second memory cell 12 is connected to the gate of the second selection transistor PG2, that is, the gates of the external selection transistor PG and the second selection transistor PG2 share the first plug 15, which is used to connect to the word line WL and apply voltage (connected to VDD) when performing the gate tunneling leakage current test. The source and drain terminals of the first pull-down transistor PD1 under test are respectively led out and grounded (connected to VSS) when performing the gate tunneling leakage current test. It should be noted that the active regions of the second selection transistor PG2 and the external selection transistor PG are electrically isolated.
[0035] Figure 2A is a schematic diagram of the first pull-down transistor PD1, the second selection transistor PG2, and the external selection transistor PG provided in an embodiment of this application.
[0036] As shown in Figure 2A, the SRAM test structure (each transistor) of this embodiment is disposed on a P-type substrate 20, and an isolation structure 28 (e.g., a trench isolation structure) is provided between adjacent transistors for isolation. The first pull-down transistor PD1 under test includes a P-type active region 23, a gate structure 21, and a plug (not shown). The P-type active region 23 is located in the P-type substrate 20, and the gate structure 21 is located on the P-type active region 23. Source / drain structures are provided in the P-type active regions 23 on both sides of the gate structure 21. The plug and the P-type active region 23 are used for electrical lead-out of the P-type active region 23. The second selection transistor PG2 includes a first P-type active region 24, a first N-type deep well region 25, a gate structure 21, and a plug (not shown). The first N-type deep well region 25 is located in the P-type substrate 20, and the first P-type active region 24 is located in the first N-type deep well region 25 (i.e., the first N-type deep well region 25 covers the first P-type active region 24). The gate structure 21 is located on the first P-type active region 24, and source / drain structures are provided in the first P-type active regions 24 on both sides of the gate structure 21. The plug is connected to the first P-type active region. Connection 24 is used for electrically leading out the first P-type active region 24 (connected to VSS). The external selection transistor PG includes a second P-type active region 26, a second N-type deep well region 27, a gate structure 21, and a plug. The second N-type deep well region 27 is located in the P-type substrate 20, and the second P-type active region 26 is located in the second N-type deep well region 27 (i.e., the second N-type deep well region 27 covers the second P-type active region 26). The gate structure 21 is located on the second P-type active region 26, and the second P-type active regions 24 on both sides of the gate structure 21 are connected to the plug. The 6th transistor has a source / drain structure, and the plug is connected to the second P-type active region 26 for electrically leading out the second P-type active region 26 (connected to VSS). Therefore, during gate tunneling leakage current testing, the first N-type deep well region 25 located between the P-type substrate 20 and the first P-type active region 24 can electrically isolate the first P-type active region 24 from the P-type substrate 20 (completely inactive), and the second N-type deep well region 27 located between the P-type substrate 20 and the second P-type active region 26 can electrically isolate the second P-type active region 26 from the P-type substrate 20 (completely inactive). This avoids the influence of the tunneling leakage current present (or potentially present) at the gates of the second selection transistor PG2 and the external selection transistor PG on the gate tunneling leakage current test of the first pull-down transistor PD1, i.e., eliminates the noise influence of the second selection transistor PG2 and the external selection transistor PG on the gate tunneling leakage current test of the first pull-down transistor PD1. This not only improves the accuracy of the gate tunneling leakage current test but also facilitates subsequent leakage current analysis.
[0037] In some examples, the first N-type deep well region 25 and the second N-type deep well region 27 may have the same or similar doping concentration and doping depth, that is, the first N-type deep well region 25 and the second N-type deep well region 27 may be formed simultaneously.
[0038] Figure 2B is a schematic diagram of the first pull-down transistor PD1, the second selection transistor PG2, and the external selection transistor PG provided in an embodiment of this application.
[0039] As shown in Figure 2B, the SRAM test structure (each transistor) of this embodiment is disposed on a P-type substrate 20. An isolation structure 28 (e.g., a trench isolation structure 28) is provided between adjacent transistors for isolation. The first pull-down transistor PD1 to be tested can be configured the same as the first pull-down transistor PD1 in Figure 2A, including a P-type active region 23, a gate structure 21, and a plug (not shown). The second selection transistor PG2 includes a first P-type active region 24 and a gate structure 21. The first P-type active region 24 is located in the P-type substrate 20, and the gate structure 21 is located on the first P-type active region 24. Source / drain structures are provided in the first P-type active regions 24 on both sides of the gate structure 21. The external selection transistor PG includes a second P-type active region 26 and a gate structure 21. The second P-type active region 26 is located in the P-type substrate 20, and the gate structure 21 is located on the second P-type active region 26. Source / drain structures are provided in the second P-type active regions 26 on both sides of the gate structure 21. Neither the first P-type active region 24 nor the second P-type active region 26 is electrically led out (not connected to the VSS). In some examples, no plugs for electrical lead-out and connection to the VSS are provided on either the first P-type active region 24 or the second P-type active region 26. In other examples, plugs are provided on both the first P-type active region 24 and the second P-type active region 26, but the plugs are not connected to the VSS; that is, no metal interconnect is provided between the plugs and the VSS. Therefore, since the first P-type active region 24 and the second P-type active region 26 are not connected to VSS, the first P-type active region 24 (second selection transistor PG2) and the second P-type active region 26 (external selection transistor PG) are electrically isolated from the P-type substrate 20 (completely inactive). This avoids the influence of the tunneling leakage current of the gate of the second selection transistor PG2 and the external selection transistor PG on the gate tunneling leakage current test of the first pull-down transistor PD1. In other words, it eliminates the noise influence of the second selection transistor PG2 and the external selection transistor PG on the gate tunneling leakage current test of the first pull-down transistor PD1, which not only improves the accuracy of the gate tunneling leakage current test, but also facilitates subsequent leakage current analysis.
[0040] Figure 3A is a circuit diagram of the SRAM storage cell provided in an embodiment of this application.
[0041] As shown in Figure 3A, the SRAM storage cell provided in this embodiment of the application can be an 8T structure, including a first selection transistor PG1, a second selection transistor PG2, a third selection transistor PG3, a fourth selection transistor PG4, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, and a second pull-down transistor PD2. In this configuration, the first to fourth select transistors PG4, the first pull-down transistor PD1, and the second pull-down transistor PD2 can be NMOS transistors, and the first pull-up transistor PU1 and the second pull-up transistor PU2 can be PMOS transistors. The first pull-up transistor PU1 and the first pull-down transistor PD1 form one of the cross-coupled inverters (the first inverter), and the second pull-up transistor PU2 and the second pull-down transistor PD2 form the other cross-coupled inverter (the second inverter). The gates of the first select transistor PG1 and the second select transistor PG2 are both connected to the first word line WL1, and the gates of the third select transistor PG3 and the fourth select transistor PG4 are both connected to the second word line WL2. The drain of the first select transistor PG1 is connected to the gate of the second inverter, the drain of the fourth select transistor PG4 is connected to the gate of the first inverter, the drain of the second select transistor PG2 is connected to the source of the first pull-down transistor PD1, the drain of the third select transistor PG3 is connected to the source of the second pull-down transistor PD2, and the source of each of the first to fourth select transistors PG4 is connected to a bit line.
[0042] Figure 3B is a schematic diagram of the SRAM test structure provided in an embodiment of this application.
[0043] As shown in Figure 3B, the SRAM test structure provided in this embodiment includes at least two adjacent SRAM memory cells, namely a first memory cell 11 and a second memory cell 12. Both the first memory cell 11 and the second memory cell 12 can be the aforementioned 8T structure, and they are arranged adjacent to each other along the gate extension direction. Taking the first pull-down transistor PD1 of the first memory cell 11 as an example, the test structure may include two gate patterns extending along the first direction X, namely a first gate pattern 13 and a second gate pattern 14. The first gate pattern 13 and the second gate pattern 14 are arranged at intervals along the second direction Y, and the first direction X and the second direction Y are orthogonal. Along the extension direction (first direction X) of the first gate pattern 13, two external selection transistors PG of the second memory cell 12, a second selection transistor PG2 of the first memory cell 11, a first selection transistor PG1, a first pull-up transistor PU1, and the first pull-down transistor PD1 to be tested are sequentially arranged. The second gate pattern 14 extends along the direction of the first memory cell 11 and includes a second pull-up transistor PU2, a second pull-down transistor PD2, a third selection transistor PG3, and a fourth selection transistor PG4. The connection of these transistors can be referenced to the memory cell in Figure 3A. It should be noted that, unlike the circuit diagram of the aforementioned SRAM memory cell, in the above SRAM test structure, the first gate pattern 13 is also connected to the gates of the first selection transistor PG1 and the first pull-up transistor PU1, and the second gate pattern 14 is also connected to the gates of the third selection transistor PG3 and the second pull-up transistor PU2. In other words, the first gate pattern 13 sequentially connects the gates of two external selection transistors PG, the second selection transistor PG2, the first selection transistor PG1, the first pull-up transistor PU1, and the first pull-down transistor PD1 to be tested. In this configuration, the gates of the two external selection transistors PG in the second memory cell 12 are connected to the gates of the first selection transistor PG1 and the second selection transistor PG2 in the first memory cell 11. That is, the two external selection transistors PG and the gates of the first selection transistors PG1 and PG2 share a first plug 15, which is used to connect to the first word line WL1 and apply voltage (connected to VDD) during the gate tunneling leakage current test. The source and drain terminals of the first pull-down transistor PD1 under test are each led out and grounded (connected to VSS) during the gate tunneling leakage current test. The active regions of the first selection transistor PG1, the second selection transistor PG2, and the two external selection transistors PG connected to their gates are all electrically isolated. The above is an example of the first selection transistor PG1, the second selection transistor PG2, and the two external selection transistors PG, which can be referred to in Figures 2A and 2B, and will not be elaborated further here.
[0044] Additionally, it should be noted that, taking the first pull-down transistor to be tested located in the first memory cell as an example, although the SRAM test structure of this application embodiment includes the first memory cell and the second memory cell, it is not necessary to have all the transistors in the second memory cell. It is also feasible to only have the transistors corresponding to the transistor to be tested.
[0045] This application also provides a layout structure, including the SRAM test structure as described above.
[0046] In summary, this application provides an SRAM test structure and layout structure. The SRAM test structure includes a second selection transistor, an external selection transistor, and a first pull-down transistor for testing gate tunneling leakage current. The second selection transistor and the first pull-down transistor are located in a first memory cell, and the external selection transistor is located in a second memory cell adjacent to the first memory cell. The gates of the second selection transistor, the external selection transistor, and the second selection transistor are all connected. The active regions of the second selection transistor and the external selection transistor are electrically isolated. In this application, by electrically isolating (disabling) the active regions of the transistors (such as the second selection transistor and the external selection transistor) in the current path for testing the gate tunneling leakage current of the first pull-down transistor, the noise influence of the second selection transistor and the external selection transistor on the gate tunneling leakage current test of the first pull-down transistor is eliminated. This not only improves the accuracy of the gate tunneling leakage current test but also facilitates subsequent leakage current analysis.
[0047] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. An SRAM test structure, characterized in that, The device includes a second selection transistor, an external selection transistor, and a first pull-down transistor for measuring gate tunneling leakage current. The second selection transistor and the first pull-down transistor are located in a first memory cell, and the external selection transistor is located in a second memory cell adjacent to the first memory cell. The gates of the second selection transistor, the external selection transistor, and the second selection transistor are all connected. The active regions of the second selection transistor and the external selection transistor are electrically isolated.
2. The SRAM test structure according to claim 1, characterized in that, Both the first and second memory cells have a 6T structure, and the drain of the second selection transistor is connected to the gate of the first pull-down transistor.
3. The SRAM test structure according to claim 2, characterized in that, The SRAM test structure is disposed on a P-type substrate. The first pull-down transistor includes a P-type active region and a plug. The P-type active region is located in the P-type substrate, and the plug is electrically led out of the P-type active region.
4. The SRAM test structure according to claim 3, characterized in that, The second selection transistor includes a first P-type active region and a first N-type deep well region, wherein the first N-type deep well region is located in the P-type substrate and the first P-type active region is located in the first N-type deep well region; the external selection transistor includes a second P-type active region and a second N-type deep well region, wherein the second N-type deep well region is located in the P-type substrate and the second P-type active region is located in the second N-type deep well region.
5. The SRAM test structure according to claim 4, characterized in that, The first N-type deep well region and the second N-type deep well region have the same doping concentration and doping depth.
6. The SRAM test structure according to claim 3, characterized in that, The second selection transistor includes a first P-type active region located in the P-type substrate and not electrically exposed; the external selection transistor includes a second P-type active region located in the P-type substrate and not electrically exposed.
7. The SRAM test structure according to claim 6, characterized in that, Neither the first P-type active region nor the second P-type active region is provided with a plug for electrical lead-out.
8. The SRAM test structure according to claim 6, characterized in that, Both the first P-type active region and the second P-type active region are provided with a second plug, which is not connected to the VSS.
9. The SRAM test structure according to claim 1, characterized in that, Both the first and second memory cells are 8T structures and are arranged adjacent to each other. The first memory cell includes a first selection transistor, a second selection transistor, and a first pull-down transistor for measuring gate tunneling leakage current. The second memory cell includes two external selection transistors. The gates of the two external selection transistors, the gate of the second selection transistor, and the gate of the first selection transistor are connected to the gate of the first pull-down transistor. The active regions of the second selection transistor, the first selection transistor, and the two external selection transistors are electrically isolated.
10. A layout structure, characterized in that, Includes the SRAM test structure as described in any one of claims 1 to 9.