Clock system and computer equipment

Abstract

The embodiment of the utility model provides a clock system and computer equipment, and the clock system comprises a clock source circuit which generates multiple paths of clock signals, and the multiple paths of clock signals comprise at least one path of first clock signal and at least one path of second clock signal; the plurality of clock buffers comprise at least one first clock buffer, one first clock buffer is in butt joint with one path of first clock signal, the path of first clock signal is expanded into a plurality of paths of calculation unit clock signals, and the calculation unit clock signals are provided for the butt joint of the plurality of calculation units; and at least one second clock buffer, one of the second clock buffers being in butt joint with a path of second clock signal, expanding the path of second clock signal into a plurality of paths of interface switching chip clock signals, and providing the interface switching chip clock signals to the plurality of butted interface switching chips. According to the clock system provided by the embodiment of the invention, the deployment cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of processor technology, specifically to a clock system and computer device. Background Technology

[0002] The processor motherboard is the core circuit board of a computer system, used to connect and coordinate the hardware components on the motherboard to ensure the operation and communication of the computer system. The clock signal is a periodically changing pulse signal on the processor motherboard used to synchronize and coordinate the hardware components on the motherboard, ensuring that the hardware components operate according to a predetermined time sequence and rate, enabling the computer system to perform tasks and process data efficiently and stably.

[0003] With the development of artificial intelligence technology, the demand for computing power is increasing. Processor motherboards need to be equipped with multiple computing units and interconnected between them to meet the higher density computing power requirements. Against this backdrop, how to deploy the clock system of the processor motherboard and reduce deployment costs has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] In view of this, embodiments of this application provide a clock system and computer device that can reduce the deployment cost of the clock system on the processor motherboard.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a clock system applied to a processor motherboard, the processor motherboard having multiple computing units and multiple interface switching chips, the multiple computing units being interconnected through the multiple interface switching chips; the clock system includes:

[0007] A clock source circuit that generates multiple clock signals, wherein the multiple clock signals include at least one first clock signal and at least one second clock signal;

[0008] Multiple clock buffers, including:

[0009] At least one first clock buffer, wherein one first clock buffer is connected to a first clock signal, expands the first clock signal into multiple computing unit clock signals, and provides them to the connected multiple computing units;

[0010] And at least one second clock buffer, wherein one second clock buffer is connected to a second clock signal, expands the second clock signal into multiple interface switching chip clock signals, and provides them to the connected multiple interface switching chips.

[0011] Optionally, the interconnection interface of the plurality of computing units supports the interconnection of the plurality of computing units through the plurality of interfaces; the computing unit clock signal includes: the top-level interconnection clock signal and the bottom-level interconnection clock signal of the interconnection interface;

[0012] The at least one first clock buffer includes:

[0013] The clock buffer of the top-level interconnect clock signal is connected to a first clock signal, which is then expanded into multiple top-level interconnect clock signals corresponding to the multiple computing units and provided to the connected multiple computing units.

[0014] The clock buffer for the underlying interconnect clock signal interfaces with a first clock signal, expands the interfaced first clock signal into multiple underlying interconnect clock signals corresponding to the multiple computing units, and provides them to the interfaced multiple computing units.

[0015] Optionally, the computing unit clock signal further includes: a wide area function link clock signal corresponding to the wide area function link between the computing units;

[0016] The at least one first clock buffer further includes:

[0017] A clock buffer for a wide area function link clock signal is connected to a first clock signal, which is then expanded into multiple wide area function link clock signals corresponding to the multiple computing units and provided to the connected multiple computing units.

[0018] Optionally, the interface switching chip clock signal includes: the system clock signal of the interface switching chip;

[0019] The at least one second clock buffer includes:

[0020] The system clock signal clock buffer is connected to a second clock signal, which expands the connected second clock signal into multiple system clock signals corresponding to the multiple interface switching chips, and provides them to the connected multiple interface switching chips.

[0021] Optionally, the clock source circuit includes:

[0022] Crystal oscillator;

[0023] A clock generator that connects to a crystal oscillator and outputs the multiple clock signals based on the crystal oscillator's clock signal.

[0024] Optionally, the computing unit clock signal includes a PCIe clock signal for supporting the PCIe connection of the computing unit;

[0025] The at least one first clock buffer includes: a plurality of PCIe clock buffers;

[0026] The PCIe clock buffer is connected to one first clock signal and extended into a PCIe clock signal; wherein, the number of PCIe clock signals extended by the multiple PCIe clock buffers corresponds to the multiple computing units, and the multiple PCIe clock signals extended by the multiple PCIe clock buffers are provided to the multiple computing units.

[0027] Optionally, it also includes: a clock multiplexer;

[0028] The clock multiplexer interfaces with one second clock signal and one PCIe clock buffer among the plurality of PCIe clock buffers, and outputs two clock signals based on the interfaced second clock signal and the first clock signal received by the PCIe clock buffer.

[0029] The interface switching chip clock signal includes the interface switching chip's reference clock signal;

[0030] The at least one second clock buffer includes:

[0031] A clock buffer for the reference clock signal is connected to the clock multiplexer, which expands one clock signal output by the clock multiplexer into multiple reference clock signals corresponding to the multiple interface switching chips, and provides them to the connected multiple interface switching chips.

[0032] Optionally, it also includes:

[0033] Multiple re-timers connected to the clock multiplexer receive another clock signal output by the clock multiplexer as a PCIe clock signal provided to the multiple re-timers;

[0034] The multiple retimers are also connected to the multiple PCIe clock buffers and receive the remaining PCIe clock signals from the multiple PCIe clock buffers. The total number of the remaining PCIe clock signals corresponds to the number of the multiple retimers.

[0035] Optionally, it also includes:

[0036] A baseboard management controller connected to the clock generator, wherein the multiple clock signals also include one clock signal provided by the clock generator to the baseboard management controller;

[0037] The field-programmable gate array connected to the clock generator includes a system clock signal provided by the clock generator to the field-programmable gate array, and an interface clock signal.

[0038] Secondly, embodiments of this application provide a computer device, the computer device including the clock system as described above.

[0039] In this embodiment of the application, when multiple computing units on a processor motherboard are interconnected through multiple interface switching chips, the clock signal provided by the extended clock source circuit can be used to meet the clock signal requirements of the multiple computing units and the multiple interface switching chips. Specifically, the clock source circuit can generate multiple clock signals, including at least one first clock signal and at least one second clock signal. Simultaneously, the clock system can be configured with multiple clock buffers, including at least one first clock buffer and at least one second clock buffer. One first clock buffer connects to one first clock signal, extending it into multiple computing unit clock signals and providing them to the connected multiple computing units to provide clock signal support. One second clock buffer connects to one second clock signal, extending it into multiple interface switching chip clock signals and providing them to the connected multiple interface switching chips to provide clock signal support.

[0040] As can be seen, the embodiments of this application can optimize resource utilization by expanding the clock signal. That is, the clock source circuit only needs to generate a small number of basic clock signals (at least one first clock signal and at least one second clock signal), and then expand them through a clock buffer to support multiple outputs. This avoids configuring a separate clock source for each computing unit and interface switching chip, thereby reducing the number and complexity of clock sources. Furthermore, a first clock buffer can expand one first clock signal into multiple outputs (i.e., multiple computing unit clock signals), covering the clock signal requirements of multiple computing units. Thus, at least one first clock buffer can meet at least one type of clock signal requirement of multiple computing units. Similarly, a second clock buffer can expand one second clock signal into multiple outputs (i.e., multiple interface switching chip clock signals), covering the clock signal requirements of multiple interface switching chips. Thus, at least one second clock buffer can meet at least one type of clock signal requirement of multiple interface switching chips. Therefore, the embodiments of this application can provide basic clock signals through a clock source circuit and then expand them through a clock buffer to achieve resource reuse and effectively reduce the deployment cost of the clock system. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0042] Figure 1 This is a structural example diagram of a multi-way interconnection of computing units;

[0043] Figure 2 This is a structural example diagram of the clock system provided in the embodiments of this application;

[0044] Figure 3 This is an example diagram of an optional structure of the clock system provided in the embodiments of this application;

[0045] Figure 4 This is an example diagram of another optional structure of the clock system provided in the embodiments of this application;

[0046] Figure 5 This is another example diagram of an optional structure of the clock system provided in the embodiments of this application. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] The processor motherboard is the core circuit board of a computer system, used to connect and coordinate the hardware components on it to ensure the operation and communication of the computer system. The processor motherboard may contain computing units, which are core components responsible for performing various computational tasks. For example, a computing unit could be a deep learning unit, a type of accelerated hardware designed for artificial intelligence and deep learning, which can speed up computational steps and complete computational tasks faster.

[0049] With the development of artificial intelligence technology, the demand for computing power is increasing. Processor motherboards need to incorporate multiple computing units and interconnect these units to meet the demands for higher-density computing power. In an optional implementation, computing units can be housed in OAM (Open Accelerator Module). OAM refers to hardware modules that conform to open computing standards, designed to provide a modular and standardized hardware platform for computing tasks such as high-performance computing and artificial intelligence computing. Multiple OAMs housing computing units can be interconnected through multiple interface switching chips, enabling communication between them. These interface switching chips are used for data exchange, distributing, aggregating, and routing data between multiple OAMs, thus providing OAMs with multi-path interconnect capabilities.

[0050] Specifically, each OAM in the multiple OAMs can be connected to a different interface switching chip. Thus, when each OAM is connected to multiple interface switching chips, the multiple interface switching chips can act as a connection intermediary between the multiple OAMs, enabling interconnection and interoperability between the multiple OAMs.

[0051] To facilitate understanding, the interconnection between multiple computing units is described below with reference to the accompanying drawings. Figure 1 This is a structural example diagram of a multi-way interconnection of computing units, where the computing units are carried by OAM, such as... Figure 1 As shown, each of the n OAMs is connected to each of the m interface switching chips, thereby enabling the n OAMs to be interconnected through the m interface switching chips; where the relationship between n and m can be either n>m or n=m.

[0052] For example, taking the eight-way interconnection of the computing unit as an example, that is, the eight OAMs carrying the computing unit are interconnected with each other, the eight OAMs can be interconnected through seven interface switching chips, and any OAM can communicate with any other OAM connected to the interface switching chip through the communication forwarding of the interface switching chip.

[0053] To ensure that multiple computing units and the multiple interface switching chips used for interconnecting these computing units can execute tasks efficiently and accurately according to a predetermined time sequence, corresponding clock signals can be provided to the computing units and interface switching chips. The clock signal is a periodically changing pulse signal in the processor motherboard, used to synchronize and coordinate the hardware components on the processor motherboard, ensuring that the hardware components operate according to a predetermined time sequence and rate, so that the computer system can execute tasks and process data efficiently and stably. Therefore, it is necessary to deploy a clock system on the processor motherboard to ensure the efficient operation of multiple computing units and multiple interface switching chips.

[0054] In view of this, embodiments of this application provide a clock system applied to a processor motherboard, the processor motherboard having multiple computing units and multiple interface switching chips, the multiple computing units being interconnected through the multiple interface switching chips; the clock system provided by embodiments of this application can reduce deployment costs.

[0055] Optionally, Figure 2 An exemplary structural diagram of the clock system provided in this application embodiment is shown below, with reference to... Figure 2 The clock system provided in this application embodiment may include a clock source circuit 200 for generating multiple clock signals, wherein the multiple clock signals include at least one first clock signal and at least one second clock signal. 。

[0056] Multiple clock buffers, including:

[0057] At least one first clock buffer 231, wherein the first clock buffer is connected to a first clock signal, expands the first clock signal into multiple computing unit clock signals, and provides them to the connected multiple computing units 210; for ease of explanation, the clock signal provided to the computing unit is called the computing unit clock signal.

[0058] In addition, at least one second clock buffer 232, wherein one second clock buffer is connected to one second clock signal, expands one second clock signal into multiple interface switching chip clock signals, and provides them to the multiple interface switching chips 220 connected to it; for ease of explanation, the clock signal provided to the interface switching chip is referred to as the interface switching chip clock signal.

[0059] The clock buffer has the function of expanding the number of clock signals. It can expand one clock signal into multiple clock signal outputs. In other words, the clock buffer can expand one input clock signal into multiple clock signal outputs for use by multiple computing units or multiple interface switching chips. Therefore, the embodiments of this application can meet the clock signal requirements of multiple computing units and multiple interface switching chips by setting the clock buffer, ensuring that the clock signals received by each computing unit and interface switching chip come from the same clock source, thereby achieving clock synchronization. At the same time, it is not necessary to deploy multiple clock sources and output clock signal channels corresponding to the computing units or interface switching chips, which simplifies the structure of the clock source circuit.

[0060] As can be seen, the embodiments of this application can optimize resource utilization by expanding the clock signal. That is, the clock source circuit only needs to generate a small number of basic clock signals (at least one first clock signal and at least one second clock signal), and then expand them through a clock buffer to support multiple outputs. This avoids configuring a separate clock source for each computing unit and interface switching chip, thereby reducing the number and complexity of clock sources. Furthermore, a first clock buffer can expand one first clock signal into multiple outputs (i.e., multiple computing unit clock signals), covering the clock signal requirements of multiple computing units. Thus, at least one first clock buffer can meet at least one type of clock signal requirement of multiple computing units. Similarly, a second clock buffer can expand one second clock signal into multiple outputs (i.e., multiple interface switching chip clock signals), covering the clock signal requirements of multiple interface switching chips. Thus, at least one second clock buffer can meet at least one type of clock signal requirement of multiple interface switching chips. Therefore, the embodiments of this application can provide basic clock signals through a clock source circuit and then expand them through a clock buffer to achieve resource reuse and effectively reduce the deployment cost of the clock system.

[0061] Furthermore, to facilitate the explanation of the structure of the clock system in the embodiments of this application, in conjunction with Figure 1 The n OAMs shown are interconnected through m interface switching chips. In this embodiment, eight computing units (i.e., n is 8) are interconnected through seven interface switching chips (i.e., m is 7) to illustrate the specific structural deployment of the clock system.

[0062] As an optional implementation Figure 3 An exemplary diagram of an optional structure of the clock system provided in an embodiment of this application is shown, with reference to... Figure 3 The eight computing units are referred to as computing unit x8, and the seven interface switching chips are referred to as interface switching chips x7; the clock source circuit may include: a crystal oscillator 201 that provides a clock source; and a clock generator 202 connected to the crystal oscillator 201 that outputs the multiple clock signals based on the clock signal of the crystal oscillator.

[0063] An external crystal oscillator is an electronic component that uses the piezoelectric effect of quartz crystals to generate a stable oscillation frequency. It can generate high-precision and high-stability clock signals to provide the operating clock frequency and timing for computing units and interface switching chips.

[0064] The clock generator uses the clock signal input from the crystal oscillator to generate multiple clock signals, which are provided to multiple computing units through a first clock buffer and to multiple interface switching chips through a second clock buffer as internal clock signals.

[0065] In an optional example, the clock system can use a 25MHz crystal oscillator 201 as the input signal. After receiving the signal, the clock generator 202 converts it into a higher frequency 100MHz differential clock signal for output through the internal PLL (Phase Locked Loop) and other frequency division circuits. The differential clock signal can be used for high-speed data transmission, providing more precise timing control and anti-interference capabilities. As an internal clock signal, it can ensure the clock synchronization and accurate operation of the computing units and interface switching chips on the processor motherboard.

[0066] Furthermore, in an optional embodiment, the computing unit (e.g., a deep computing unit) may have an interconnect interface that supports interconnection between computing units. This interconnect interface may support a memory interconnect bus between computing units for memory access and data exchange, allowing different computing units to share and access each other's memory resources. Thus, the computing unit clock signal provided to the computing unit may include the clock signal of the interconnect interface.

[0067] In optional implementations, the clock signals of the interconnect interface can be divided into top-level interconnect clock signals and bottom-level interconnect clock signals. The top-level interconnect clock signal is a clock drive signal used to support the upper-level modules (e.g., high-level logic circuits) of the computing unit, and can control the synchronous operation of the upper-level modules (e.g., high-level logic circuits). The bottom-level interconnect clock signal is a clock drive signal used to support the lower-level modules (e.g., physical layer circuits) of the computing unit, such as providing the clock for the physical interface of the computing unit and the lower-level transmission logic.

[0068] Furthermore, there is a need for functional coordination between computing units. Therefore, it is necessary to support communication and functional collaboration links between computing units over a wide area, that is, to support wide-area functional links between computing units. Based on this, the computing unit clock signal provided to the computing unit may also include a wide-area functional link clock signal (referred to as the wide-area functional link clock signal) to support wide-area functional links between computing units.

[0069] Accordingly, at least one first clock buffer may include: a clock buffer for a top-level interconnect clock signal, which interfaces with one first clock signal, expands the interfaced first clock signal into multiple top-level interconnect clock signals corresponding to the plurality of computing units, and provides them to the interfaced plurality of computing units.

[0070] The clock buffer for the underlying interconnect clock signal interfaces with a first clock signal, expands the interfaced first clock signal into multiple underlying interconnect clock signals corresponding to the multiple computing units, and provides them to the interfaced multiple computing units.

[0071] A clock buffer for a wide area function link clock signal is connected to a first clock signal, which is then expanded into multiple wide area function link clock signals corresponding to the multiple computing units and provided to the connected multiple computing units.

[0072] For example, when eight computing units and seven interface switching chips are interconnected through the above interconnect interfaces, the eight computing units require sixteen interconnect interface clock signals (eight of which are top-level interconnect clock signals and eight of which are bottom-level interconnect clock signals), as well as eight wide-area function link clock signals.

[0073] In an optional embodiment, refer to Figure 3 To meet the clock signal requirements of multiple computing units, the clock generator 202 can output three first clock signals, two of which are clock signals supporting sixteen interconnection interfaces. Specifically, one is expanded into eight top-level interconnection clock signals (represented as T x8 in the figure) through the first clock buffer U1, and another is expanded into eight bottom-level interconnection clock signals (represented as B x8 in the figure) through the first clock buffer U2; the third is expanded into eight wide-area function link clock signals (represented as W x8 in the figure) through the first clock buffer U3, and then the expanded multiple clock signals are provided to the eight connected computing units respectively.

[0074] As can be seen, the clock generator 202 generates and outputs three first clock signals, which are then divided into three different clock signals by the corresponding clock buffers. Each clock signal corresponding to a different purpose is then expanded into multiple clock signals with the same number of computing units, which are provided to the connected computing units. This simplifies the structure of the clock source circuit and reduces deployment costs.

[0075] Furthermore, since multiple computing units are interconnected through multiple interface switching chips, this embodiment of the application also needs to provide multiple interface switching chips with clock signals from the same clock source as the computing units, thereby ensuring that multiple computing units and multiple interface switching chips maintain the same clock source when interconnected through interfaces.

[0076] In an optional implementation, the interface switching chip clock signal may include: the system clock signal of the interface switching chip; correspondingly, the at least one second clock buffer may include: a clock buffer for the system clock signal, which is connected to a second clock signal generated by the clock generator, expands the connected second clock signal into multiple system clock signals corresponding to the plurality of interface switching chips, and provides them to the connected plurality of interface switching chips.

[0077] For example, when eight computing units and seven interface switching chips are interconnected through the aforementioned interconnection interface, the seven interface switching chips require seven system clock signals, as shown in the reference. Figure 3 The clock generator 202 generates and outputs a second clock signal for the interface switching chip, which is then expanded by the corresponding second clock buffer U4 into seven system clock signals of the same number as the interface switching chips, and provided to the seven interface switching chips (represented as interface switching chip x7 in the figure), thereby simplifying the structure of the clock source circuit and reducing deployment costs.

[0078] As an optional implementation Figure 4 An exemplary diagram of another optional structure of the clock system provided in the embodiments of this application is shown, with reference to... Figure 4 The clock sources for multiple computing units and multiple interface switching chips can also be directly provided by the external host 203.

[0079] In this embodiment, the clock signal input from the crystal oscillator and output from the clock generator can be used as the clock signal used internally by the system on the processor motherboard, while the clock signal provided by the external host can be used as a reference clock input to provide a benchmark for calibration and synchronization, ensuring that the interfaces of various components on the processor motherboard are synchronized with the clock of the external system, thereby ensuring the accuracy and stability of data transmission.

[0080] In an optional embodiment, the external host can provide a 100MHz differential clock signal input, which is input to multiple clock buffers, and then expanded by the clock buffers into multiple clock signals provided to multiple computing units and multiple interface switching chips.

[0081] In this embodiment, an external host can be connected via a PCIe bus. PCIe is a high-speed serial computer expansion bus standard, and the interface connected via the PCIe bus can be called a PCIe interface. The clock signal (i.e., the computing unit clock signal) provided by the external host to the computing unit may include a PCIe clock signal to support the PCIe connection of the computing unit.

[0082] Accordingly, the at least one first clock buffer may include: multiple PCIe clock buffers, wherein the PCIe clock buffers are connected to a first clock signal generated by the external HOST host and extended into a PCIe clock signal; wherein the number of PCIe clock signals extended by the multiple PCIe clock buffers corresponds to the multiple computing units, and the multiple PCIe clock signals extended by the multiple PCIe clock buffers are provided to the multiple computing units.

[0083] For example, consider eight computing units interconnected via seven interface switching chips, refer to Figure 4 The external host 203 can provide three clock signal inputs, including: a zeroth clock circuit, a first clock circuit, and a second clock circuit. The zeroth clock circuit is connected to a PCIe clock buffer (represented as U5 in the figure), and the second clock circuit is connected to a PCIe clock buffer (represented as U6 in the figure). The PCIe clock buffer U5 expands the clock signal provided by the zeroth clock circuit into four PCIe clock signals (represented as PCIe x4 in the figure) and provides them to eight computing units (represented as computing units x8 in the figure). The PCIe clock buffer U6 also expands the clock signal provided by the first clock circuit into four PCIe clock signals (represented as PCIe x4 in the figure) and provides them to multiple computing units (represented as computing units x8 in the figure).

[0084] As can be seen, the two PCIe clock buffers (U5 and U6) expand the total number of PCIe clock signals provided to multiple computing units, corresponding to the multiple computing units, thereby enabling the external host to provide clock signals to eight computing units, while simplifying the clock source circuit structure.

[0085] Furthermore, the clock system also includes a clock multiplexer (MUX) and multiple retimers connected to the clock multiplexer (MUX).

[0086] In this embodiment, during the transmission of the clock signal from the external host to the computing unit or interface switching chip, the clock signal may experience attenuation, distortion, or interference, affecting the transmission quality of the clock signal. Therefore, it is necessary to set a Retimer to detect, process, and regenerate the clock signal to ensure that the clock signal maintains good quality after long-distance transmission.

[0087] Furthermore, in the embodiments of this application, the integrity and flexibility of clock signal transmission can be improved by combining a clock multiplexer (MUX) and a retimer.

[0088] The connection structure of the clock system will be further described below with reference to the accompanying drawings.

[0089] In an optional implementation, the clock multiplexer is connected to the clock circuit provided by the external host and one of the multiple PCIe clock buffers, and outputs two clock signals based on a second clock signal provided by the external host and a first clock signal received by the PCIe clock buffer.

[0090] For example, refer to Figure 4 The clock multiplexer MUX is connected to the second clock circuit and the PCIe clock buffer U6. Based on the second clock signal provided by the second clock circuit and the first clock signal received by the PCIe clock buffer U6, it outputs two clock signals.

[0091] Furthermore, in this embodiment of the application, the clock signal provided by the external HOST host to the interface switching chip (i.e., the interface switching chip clock signal) may include the reference clock signal of the interface switching chip.

[0092] Accordingly, the at least one second clock buffer includes: a clock buffer for reference clock signals, which is connected to the clock multiplexer to expand one clock signal output by the clock multiplexer into multiple reference clock signals corresponding to the plurality of interface switching chips, and provides them to the connected plurality of interface switching chips.

[0093] Furthermore, the plurality of retimers receive another clock signal output by the clock multiplexer as a PCIe clock signal provided to the plurality of retimers.

[0094] The multiple retimers are also connected to the multiple PCIe clock buffers and receive the remaining PCIe clock signals from the multiple PCIe clock buffers. The total number of the remaining PCIe clock signals corresponds to the number of the multiple retimers.

[0095] For example, taking eight computing units interconnected through seven interface switching chips as an example, continue to refer to... Figure 4 The at least one second clock buffer includes: a clock buffer for reference clock signals (represented as second clock buffer U7 in the figure), which is connected to a clock multiplexer MUX to expand one clock signal output by the clock multiplexer MUX into seven reference clock signals corresponding to the seven interface switching chips, and provides them to the seven interface switching chips (represented as interface switching chip x7 in the figure).

[0096] This application embodiment includes eight retimers (represented as Retimer x8 in the figure). Each of the eight retimers receives another clock signal (represented as PCIe x1 in the figure) output by the clock multiplexer MUX, which serves as one PCIe clock signal provided to the eight retimers. In addition, the eight retimers also receive the remaining four clock signals (represented as PCIe x4 in the figure) extended from the PCIe clock buffer U5. That is to say, the four clock signals received by the retimers and the four PCIe clock signals received by the eight computing units come from the same clock circuit provided by the external HOST host, namely the zeroth clock circuit.

[0097] Continue to refer to Figure 4 The eight retimers also receive three clock signals from the PCIe clock buffer U6 (represented as PCIe x3 in the figure). In other words, three of the clock signals received by the retimers and the other four clock signals received by the eight computing units come from the same clock circuit provided by the external host, namely the first clock circuit.

[0098] Furthermore, in this embodiment, the clock multiplexer MUX receives two clock signals, including a second clock signal provided by the second clock circuit and a first clock signal received by the PCIe clock buffer U6. Therefore, one of the clock signals received by the multiple retimers from the clock multiplexer MUX may come from the first clock circuit or the second clock circuit, as selected by the clock multiplexer MUX.

[0099] In this embodiment, the clock multiplexer MUX employs a two-input, two-output mechanism, specifically, combined with... Figure 4 For example, the sources of one clock signal for multiple timers and the sources of clock signals for multiple interface switching chips can be categorized into four types.

[0100] First, the clock multiplexer MUX selects one first clock signal received by the PCIe clock buffer U6. In this case, among the clock signals received by the retimer, there are four clock signals (including PCIe x3 and PCIe x1) that all come from the first clock circuit.

[0101] In other words, the retimer has four clock signals and seven interface switching chips (represented as interface switching chip x7 in the figure) whose clock signals all come from the same source: the first clock signal received by the PCIe clock buffer U6.

[0102] Second, the clock multiplexer MUX selects one second clock signal provided by the second clock circuit to output. In this case, among the clock signals received by the retimer, four clock signals (PCIe x4) come from the zero clock circuit, three clock signals (PCIe x3) come from the first clock circuit, and one clock signal (PCIe x1) comes from the second clock circuit.

[0103] In other words, the re-timer has only one clock signal and the clock signals of multiple interface switching chips (represented as interface switching chip x7 in the figure) have the same source, all of which come from the second clock signal provided by the second clock circuit.

[0104] Third, the clock multiplexer MUX selects one of the first clock signals received by the output PCIe clock buffer U6 to the retimer, and at the same time selects one of the second clock signals provided by the output second clock circuit to the clock buffer of the reference clock signal (represented as the second clock buffer U7 in the figure) for expansion; in this case, among the clock signals received by the retimer, there are a total of four clock signals (including PCIe x3 and PCIe x1) all from the first clock circuit.

[0105] In other words, the clock signal of the retimer and the clock signals of multiple interface switching chips (represented as interface switching chip x7 in the figure) do not come from the same clock circuit.

[0106] Fourth, the clock multiplexer MUX selects one of the first clock signals received by the output PCIe clock buffer U6 to extend the clock buffer of the reference clock signal (shown as the second clock buffer U7 in the figure), and at the same time selects one of the second clock signals provided by the output second clock circuit to the retimer; in this case, among the clock signals received by the retimer, four clock signals (PCIe x4) come from the zero clock circuit, three clock signals (PCIe x3) come from the first clock circuit, and one clock signal (PCIe x1) comes from the second clock circuit.

[0107] In other words, the retimer has three clock signals and the clock signals of multiple interface switching chips (represented as interface switching chip x7 in the figure) all originate from the first clock signal received by the PCIe clock buffer U6.

[0108] In the embodiments of this application, by combining a clock multiplexer and a retimer, the clock signal can be dynamically adjusted under different operating conditions, achieving more precise signal control and optimization, and improving flexibility.

[0109] By connecting and deploying the aforementioned clock system, the clock signal input from the external host can be accurately provided to multiple computing units, multiple interface switching chips, and multiple retimers, providing a more flexible signal distribution mechanism. When multiple computing units and multiple interface switching chips are connected to the external host via the PCIe interface, the clock source of the PCIe interface can be kept consistent. At the same time, the clock source circuit structure is simplified, and the deployment cost is reduced.

[0110] Furthermore, Figure 5 An exemplary diagram illustrates another optional structure example of the clock system provided in the embodiments of this application. Wherein, Figure 5 and Figure 3 , Figure 4 The same structure can be found in the description of the corresponding section above.

[0111] In this embodiment of the application, the clock system further includes a Baseboard Management Controller (BMC) connected to the clock generator; correspondingly, the multiple clock signals further include a clock signal provided by the clock generator 202 to the Baseboard Management Controller.

[0112] The baseboard management controller is a dedicated microcontroller on the processor motherboard that is responsible for monitoring and managing hardware status, such as temperature, voltage, and fan speed, and provides remote management functions.

[0113] In practical implementation, the BMC can be connected to the PCIe bus through the root endpoint (RC) for management and monitoring; the clock signal is the basis for the collaborative work between the RC and the BMC, and both rely on the clock signal to ensure the synchronization of data transmission and the stability of the system.

[0114] Combination Figure 5 In this embodiment, the clock generator 202 can provide a clock signal (represented as PCIe RC in the figure) to the BMC to ensure clock synchronization. In addition, the BMC also needs a 25MHz single-ended clock for its own operation, which is represented as 25M OSC (Oscillator Circuit) in the figure.

[0115] Furthermore, the clock system also includes a field-programmable gate array (FPGA) connected to the clock generator; correspondingly, the multiple clock signals also include a system clock signal provided by the clock generator 202 to the field-programmable gate array, and an interface clock signal.

[0116] An FPGA is an integrated circuit that allows users to programmably configure the hardware structure, providing flexibility and customizability. Users can implement specific logic functions through programming.

[0117] In this embodiment, the FPGA receives two clock signals from the clock generator. One of them serves as the FPGA's system clock signal (represented as SYS in the figure), which is used to drive the internal logic circuits and processing flow of the FPGA. The other clock signal (represented as PCIe EP in the figure) is dedicated to communication between the FPGA and the PCIe interface, and is responsible for data communication between the FPGA and external PCIe devices.

[0118] Alternatively, in the PCIe architecture, an FPGA can exist as an endpoint in the PCIe link. When an FPGA acts as an endpoint, it can be directly connected to the root endpoint RC to perform specific hardware acceleration tasks or process specific data streams. The flexibility of the FPGA allows it to be adapted to different tasks and requirements by reprogramming without changing the physical hardware.

[0119] In other words, for FPGAs, the separation of these two clock signals ensures that the FPGA can efficiently process internal logic and external communication simultaneously, avoiding clock signal conflicts and interference.

[0120] As can be seen, the embodiments of this application can optimize resource utilization by expanding the clock signal. That is, the clock source circuit only needs to generate a small number of basic clock signals (at least one first clock signal and at least one second clock signal), and then expand them through a clock buffer to support multiple outputs. This avoids configuring a separate clock source for each computing unit and interface switching chip, thereby reducing the number and complexity of clock sources. Furthermore, a first clock buffer can expand one first clock signal into multiple outputs (i.e., multiple computing unit clock signals), covering the clock signal requirements of multiple computing units. Thus, at least one first clock buffer can meet at least one type of clock signal requirement of multiple computing units. Similarly, a second clock buffer can expand one second clock signal into multiple outputs (i.e., multiple interface switching chip clock signals), covering the clock signal requirements of multiple interface switching chips. Thus, at least one second clock buffer can meet at least one type of clock signal requirement of multiple interface switching chips. Therefore, the embodiments of this application can provide basic clock signals through a clock source circuit and then expand them through a clock buffer to achieve resource reuse and effectively reduce the deployment cost of the clock system.

[0121] This application provides a computer device, such as a terminal device or a server device, which includes the clock system described in the foregoing embodiments.

[0122] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0123] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A clock system, characterized in that, Applied to a processor motherboard, the processor motherboard is provided with multiple computing units and multiple interface switching chips, the multiple computing units are interconnected through the multiple interface switching chips; The clock system includes: A clock source circuit that generates multiple clock signals, wherein the multiple clock signals include at least one first clock signal and at least one second clock signal; Multiple clock buffers, including: At least one first clock buffer, wherein one first clock buffer is connected to a first clock signal, expands the first clock signal into multiple computing unit clock signals, and provides them to the connected multiple computing units; And at least one second clock buffer, wherein one second clock buffer is connected to a second clock signal, expands the second clock signal into multiple interface switching chip clock signals, and provides them to the connected multiple interface switching chips.

2. The clock system according to claim 1, characterized in that, The interconnection interface of the plurality of computing units supports the interconnection of the plurality of computing units through the plurality of interfaces; The computing unit clock signal includes: the top-level interconnect clock signal and the bottom-level interconnect clock signal of the interconnect interface; The at least one first clock buffer includes: The clock buffer of the top-level interconnect clock signal is connected to a first clock signal, which is then expanded into multiple top-level interconnect clock signals corresponding to the multiple computing units and provided to the connected multiple computing units. The clock buffer for the underlying interconnect clock signal interfaces with a first clock signal, expands the interfaced first clock signal into multiple underlying interconnect clock signals corresponding to the multiple computing units, and provides them to the interfaced multiple computing units.

3. The clock system according to claim 2, characterized in that, The computing unit clock signal also includes: the wide area function link clock signal corresponding to the wide area function link between the computing units; The at least one first clock buffer further includes: A clock buffer for a wide area function link clock signal is connected to a first clock signal, which is then expanded into multiple wide area function link clock signals corresponding to the multiple computing units and provided to the connected multiple computing units.

4. The clock system according to claim 2, characterized in that, The interface switching chip clock signal includes: the system clock signal of the interface switching chip; The at least one second clock buffer includes: The system clock signal clock buffer is connected to a second clock signal, which expands the connected second clock signal into multiple system clock signals corresponding to the multiple interface switching chips, and provides them to the connected multiple interface switching chips.

5. The clock system according to any one of claims 2-4, characterized in that, The clock source circuit includes: Crystal oscillator; A clock generator that connects to a crystal oscillator and outputs the multiple clock signals based on the crystal oscillator's clock signal.

6. The clock system according to claim 1, characterized in that, The computing unit clock signal includes a PCIe clock signal, used to support the PCIe connection of the computing unit; The at least one first clock buffer includes: a plurality of PCIe clock buffers; The PCIe clock buffer is connected to one first clock signal and extended into a PCIe clock signal; wherein, the number of PCIe clock signals extended by the multiple PCIe clock buffers corresponds to the multiple computing units, and the multiple PCIe clock signals extended by the multiple PCIe clock buffers are provided to the multiple computing units.

7. The clock system according to claim 6, characterized in that, Also includes: Clock multiplexer; The clock multiplexer interfaces with one second clock signal and one PCIe clock buffer among the plurality of PCIe clock buffers, and outputs two clock signals based on the interfaced second clock signal and the first clock signal received by the PCIe clock buffer. The interface switching chip clock signal includes the interface switching chip's reference clock signal; The at least one second clock buffer includes: A clock buffer for the reference clock signal is connected to the clock multiplexer, which expands one clock signal output by the clock multiplexer into multiple reference clock signals corresponding to the multiple interface switching chips, and provides them to the connected multiple interface switching chips.

8. The clock system according to claim 7, characterized in that, Also includes: Multiple retimers connected to the clock multiplexer receive another clock signal output by the clock multiplexer. ， This serves as a PCIe clock signal provided to the multiple re-timers; The multiple retimers are also connected to the multiple PCIe clock buffers and receive the remaining PCIe clock signals from the multiple PCIe clock buffers. The total number of the remaining PCIe clock signals corresponds to the number of the multiple retimers.

9. The clock system according to claim 5, characterized in that, Also includes: A baseboard management controller connected to the clock generator, wherein the multiple clock signals also include one clock signal provided by the clock generator to the baseboard management controller; The field-programmable gate array connected to the clock generator includes a system clock signal provided by the clock generator to the field-programmable gate array, and an interface clock signal.

10. A computer device, characterized in that, The computer device includes a clock system as described in any one of claims 1 to 9.

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