Testing equipment for portable flight control computer host

Abstract

The utility model discloses a portable flight control computer host test device, which comprises an upper computer and a test unit, and the upper computer is composed of a microcontroller and a display unit. The microcontroller is used for determining test requirements of equipment to be tested and sending the test requirements to the FPGA in the test unit through the Ethernet. A plurality of excitation signals are stored in the FPGA, and the FPGA selects an appropriate signal as a test signal according to a test requirement and transmits the test signal to a device to be tested through a 1553B protocol. The to-be-tested device generates an output signal according to the received test signal, and the display unit is responsible for analyzing and displaying the output signal. The device is small in size, convenient to carry and move and capable of being flexibly used in different places, the device to be tested does not need to be moved to a fixed testing position, and operation complexity and uncertainty caused by space and environment limitation are greatly reduced.

Description

Technical Field

[0001] This application relates to the field of computers, specifically to a test device for a portable flight control computer host. Background Technology

[0002] Currently, test equipment for flight control computer mainframes is generally characterized by its large size and complex structure. These test devices not only occupy a large area but also contain numerous sophisticated testing instruments and complex circuit systems, resulting in a lack of portability in their design. This portability makes moving the test equipment between different testing locations extremely difficult, if not practically feasible. Therefore, in practice, it is usually preferable to move the flight control computer mainframe under test to a fixed test device rather than moving the test device to the location of the device under test.

[0003] This testing method may not have a significant impact when dealing with a single or small number of devices under test (DUTs), but it becomes extremely inconvenient when testing a large number of DUTs. Before each test, staff need to frequently move the DUTs from their original work locations to the testing location. This not only consumes a lot of time and manpower but may also increase the complexity and uncertainty of the operation due to limitations in space and environment. Especially when multiple DUTs need to be tested in parallel, frequent device relocation and test location selection can become bottlenecks to efficiency improvement, leading to delays and wasted resources in the testing process.

[0004] Therefore, improving the portability and flexibility of flight control computer host testing equipment to reduce the inconvenience and resource waste caused by frequent handling of the equipment under test is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0005] In view of this, embodiments of this application provide a test device for a portable flight control computer host, so as to improve the portability and flexibility of the flight control computer host test device and reduce the inconvenience and resource waste caused by frequent handling of the device under test.

[0006] To address the above problems, the technical solutions provided in this application are as follows:

[0007] A test device for a portable flight control computer host, the device comprising: a host computer and a test unit; the test unit comprising a field-programmable gate array (FPGA); the host computer comprising a microcontroller and a display unit;

[0008] The microcontroller is communicatively connected to the display unit, the FPGA, and the device under test (DUT); the FPGA is connected to the DUT; the display unit is connected to the DUT; the DUT includes a flight control computer host; the FPGA stores various excitation signals for testing the flight control computer host;

[0009] The microcontroller is used to receive the test requirements of the device under test and send the test requirements to the FPGA via Ethernet;

[0010] The FPGA is used to output test signals for the device under test (DUT) based on the test requirements, and to send the test signals to the DUT based on the 1553B protocol, so that the DUT generates an output signal based on the test signals; the test signal is one of the excitation signals.

[0011] The display unit is used to analyze and display the output signal.

[0012] In one possible implementation, the microcontroller is also used to monitor whether the working status of each module in the device under test is normal;

[0013] The display unit is also used to display the names of modules in the device under test that are malfunctioning.

[0014] In one possible implementation, the test unit further includes: an application-specific integrated circuit (ASIC); the ASIC is connected to both the FPGA and the device under test (DUT).

[0015] The FPGA is also used to send the test signal to the dedicated integrated circuit based on the RS485 protocol when the signal form of the test signal does not conform to the target signal form.

[0016] The dedicated integrated circuit is used to convert the signal form of the test signal into the target signal form to obtain a converted signal, and to send the converted signal as a test signal to the device under test based on the data acquisition protocol DA protocol.

[0017] In one possible implementation, the display unit includes a decoder and a display screen;

[0018] The decoder is used to receive the output signal based on the Pulse Code Modulation (PCM) code stream, and to perform signal analysis on the output signal to obtain the analyzed signal.

[0019] The display screen is used to display the parsed signal.

[0020] In one possible implementation, the display unit further includes a signal generator:

[0021] A signal generator is used to generate a prompt signal and send the prompt signal to the device under test based on the Low Voltage Differential Signaling (LVDS) protocol to prompt the device under test to issue the output signal.

[0022] In one possible implementation, the device further includes a power supply unit; the power supply unit is connected to both the host computer and the test unit.

[0023] The power supply unit is used to supply power to the host computer and the test unit.

[0024] In one possible implementation, the device further includes: an indicator light; the indicator light is connected to the power supply unit;

[0025] The indicator light illuminates when the power unit outputs power; otherwise, the indicator light is off.

[0026] In one possible implementation, the host computer further includes a memory; the memory is connected to the microcontroller.

[0027] The memory is used to store the test data and output signal data generated by the device under test during the test.

[0028] In one possible implementation, the device further includes a Cyclic Redundancy Check (CRC) checker connected between the device under test and the decoder.

[0029] The CRC checker is used to perform integrity verification on the output signal to ensure that the output signal conforms to the expected target signal form and that there is no signal loss or error.

[0030] In one possible implementation, the microcontroller is also used for;

[0031] The system detects faults in the host computer and the test unit during the testing process and generates fault reports based on the test results.

[0032] Therefore, the embodiments of this application have the following beneficial effects:

[0033] The portable flight control computer host test device of this application mainly consists of a host computer and a test unit. The host computer includes a microcontroller and a display unit, and the microcontroller communicates with the display unit, the test unit, and the device under test (DUT). The test unit includes a field-programmable gate array (FPGA), which is connected to the DUT and stores various excitation signals for testing the flight control computer host. The microcontroller is responsible for determining the test requirements of the DUT and sending these requirements to the FPGA via Ethernet. According to the test requirements, the FPGA selects an appropriate test signal from the stored excitation signals and sends the test signal conforming to the target signal form to the DUT via the 1553B protocol, causing the DUT to generate an output signal based on the target signal. The target signal form corresponds to the control signal form of the DUT. The display unit is responsible for parsing and displaying the generated output signal. Because the portable flight control computer host test device of this application has a simple structure and centralized control, it is easier to operate and does not require frequent switching between multiple test devices and working environments. Staff only need to carry portable testing equipment to different testing points, reducing the frequency of moving the equipment under test and thus saving significant labor and time costs. Therefore, testing personnel do not need to frequently disassemble and move the equipment under test, avoiding the efficiency bottlenecks caused by frequent transportation and equipment scheduling in traditional testing methods. This application converts the pressure signal of the fire extinguisher into a warning message to alert the user that the vehicle-mounted fire extinguisher is malfunctioning and needs immediate attention. This can prevent the fire extinguisher from over-pressurizing and potentially exploding, and also prevent the vehicle-mounted fire extinguisher from becoming unusable due to insufficient pressure in unexpected situations. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings used in the description of the embodiment or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic diagram of a test device for a portable flight control computer host provided in an embodiment of this application;

[0036] Figure 2 A schematic diagram of the test device structure for another portable flight control computer host provided in the embodiments of this application;

[0037] Figure 3 A schematic diagram of the test device structure for another portable flight control computer host provided in the embodiments of this application;

[0038] Figure 4 A schematic diagram of the test device structure for another portable flight control computer host provided in an embodiment of this application. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0040] Currently, flight control computer mainframe testing equipment is generally bulky and complex, occupying a significant amount of space and containing precision instruments and intricate circuitry, lacking portability. This makes transferring equipment between different testing locations extremely difficult, typically requiring the device under test (DUT) to be moved to a fixed testing facility rather than the testing facility being moved to the DUT. While this approach has minimal impact when testing a single or small number of devices, when a large number of devices need to be tested in parallel, frequent equipment relocation and location selection not only increase time and labor costs but may also lead to operational complexity and efficiency bottlenecks due to space and environmental limitations, further delaying the testing process and wasting resources.

[0041] To address this issue, this application provides a test device for a portable flight control computer host, comprising a host computer and a test unit. The host computer includes a microcontroller and a display unit. The microcontroller is connected to the display unit, the test unit, and the device under test (DUT) via communication. The FPGA in the test unit is connected to the DUT and stores various excitation signals for testing the flight control computer host. The microcontroller transmits the test requirements of the DUT to the FPGA via Ethernet. The FPGA selects a suitable excitation signal based on the test requirements and sends a test signal conforming to the target signal format to the DUT via the 1553B protocol. The DUT generates an output signal based on this signal. The display unit is responsible for parsing and displaying the output signal. This application's device is compact, portable, and mobile, allowing for flexible use in different locations without requiring the DUT to be moved to a fixed test position, significantly reducing the operational complexity and uncertainty caused by space and environmental limitations.

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0043] See Figure 1 , Figure 1 This is a schematic diagram of the test device structure for a portable flight control computer host provided in an embodiment of this application.

[0044] The testing equipment provided in this embodiment includes a host computer 110 and a testing unit 120, and has the following characteristics:

[0045] First, the host computer 110 is the "brain" of the device, responsible for signal processing and result display throughout the testing process. The host computer 110 includes a microcontroller 111 and a display unit 112. The microcontroller 111 is mainly used to communicate with the test unit 120 and the device under test 130, receiving information from the test unit 120, receiving test requirements from the device under test 130, and sending these test requirements to the FPGA 121 in the test unit 120 via Ethernet. Furthermore, the microcontroller 111 works in conjunction with the display unit 112 to perform real-time analysis and display of various data during the testing process, providing operators with clear visual feedback and facilitating immediate adjustments to testing strategies.

[0046] Secondly, the FPGA 121 in test unit 120 plays a crucial role in the entire test. The FPGA 121 pre-stores various excitation signals, specifically designed for testing the flight control computer host (i.e., the device under test 130), covering various possible operating states and functional requirements. Based on the test requirements transmitted from the microcontroller 111, the FPGA 121 selects the most suitable signal type from this excitation signal library and generates the corresponding test signal according to the test requirements. After selecting the appropriate excitation signal, the FPGA 121 sends the signal to the device under test 130 via the 1553B protocol to ensure the accuracy and stability of signal transmission. At this point, the device under test 130 generates the corresponding output signal based on the received signal, thereby completing the performance verification and debugging of the device.

[0047] More importantly, the application of the 1553B protocol in this test equipment greatly improves the reliability of signal transmission. The 1553B protocol is a mature avionics communication protocol with high reliability and strong anti-interference capabilities, making it particularly suitable for testing flight control computer mainframes requiring high precision and stability. Through this protocol, the FPGA121 can transmit precise test signals to the device under test (DUT) 130. The DUT 130 then generates its control signals based on these test signals and performs corresponding outputs. Since the target signal form of the DUT 130 is typically its control signal form, the correctness of the signal is crucial during transmission, and the use of the 1553B protocol effectively ensures this.

[0048] Finally, the display unit 112 is responsible for real-time analysis and display of test results. The display unit 112 processes and visualizes the output signals generated by the device under test 130, helping operators quickly understand the device status and make necessary adjustments. In this way, testers can not only monitor the entire testing process but also ensure that each step meets the predetermined test standards, thereby improving the accuracy and efficiency of the test.

[0049] In one possible implementation, the microcontroller 111 can also ensure that each module of the device under test 130 can function normally during the generation of output signals, avoiding any potential faults or anomalies that could affect the accuracy and reliability of the test results. Specifically, the operating logic of the microcontroller 111 can be divided into several key steps.

[0050] First, the connection between the microcontroller 111, the device under test (DUT) 130, and the display unit 112 forms a closed-loop monitoring system. Through real-time communication with the DUT 130, the microcontroller 111 can obtain the status information of each module of the DUT 130. These modules may include different parts such as signal processing modules, output modules, and input modules, each responsible for executing different functions within the device. While the DUT 130 is operating, the microcontroller 111 continuously monitors the status of these modules to ensure they operate as expected.

[0051] During the test, the device under test (DUT) 130 generates output signals according to the predetermined test requirements. The task of the microcontroller 111 is to monitor the operating status of each module in real time during this process, paying particular attention to any abnormalities or faults. For example, if a module malfunctions or fails to work properly, the microcontroller 111 will quickly detect this abnormality and promptly provide relevant information.

[0052] Once the microcontroller 111 detects an malfunction in a module of the device under test 130, it will interact with the display unit 112 to show the operator the specific fault information. The main task of the display unit 112 is to clearly display the name of the malfunctioning module and the possible fault type on the interface, enabling the operator to quickly identify the problem and take appropriate corrective measures. In this way, the operator can effectively supervise the entire testing process, ensuring that problems can be detected and corrected in a timely manner at any time.

[0053] The microcontroller 111 plays a crucial role in the host computer 110. It not only helps operators continuously monitor the working status of each module of the device under test 130, but also provides detailed fault information when anomalies occur, and displays the name of the problematic module through the display unit 112. This design greatly improves the reliability of the entire test equipment, effectively avoiding deviations in test results due to equipment failure, thereby ensuring the accuracy and efficiency of the test.

[0054] In one possible implementation, the design of test unit 120 also includes an application-specific integrated circuit 122. For example... Figure 2 As shown, the application-specific integrated circuit 122 is connected to both the FPGA 121 and the device under test 130. The application-specific integrated circuit 122 plays a crucial role. Its function is to ensure that signals between different modules can be accurately converted and transmitted, enabling effective testing of the device under test 130. The cooperation and working principles of the various components in the test unit 120 will be explained in detail below.

[0055] First, the application-specific integrated circuit (ASIC) 122 establishes connections with both the FPGA 121 and the device under test (DUT) 130. The primary responsibility of ASIC 122 is to convert the test signals from the FPGA 121 into a target signal format that the DUT 130 can receive. Therefore, communication between the FPGA 121 and ASIC 122 is fundamental to the entire testing process, ensuring that the test signals are transmitted to ASIC 122 in the correct format.

[0056] Specifically, FPGA121 first generates test signals, the format of which may not directly match the input requirements of the device under test (DUT) 130. In this case, FPGA121 needs to process the signals to ensure their format matches the target signal format. If the test signal format does not meet the requirements of the target device, FPGA121 will send it to application-specific integrated circuit (ASIC) 122 using the RS485 (Recommended Standard 485) protocol. RS485 is a serial communication protocol widely used in industrial control systems, characterized by long-distance transmission and multi-point communication, thus effectively ensuring stable transmission of test signals within the device.

[0057] When the application-specific integrated circuit (ASIC) 122 receives the test signal transmitted by the FPGA 121 via the RS485 protocol, its main task is to convert the signal. ASIC 122 needs to convert the received test signal format into the target signal format according to the requirements of the device under test (DUT) 130. This conversion process is crucial because the DUT 130 typically only accepts signals in specific formats; any format mismatch will cause the device to malfunction. Therefore, ASIC 122 must accurately perform this conversion.

[0058] After signal conversion, the application-specific integrated circuit 122 sends the converted signal to the device under test 130 in the form of a Data Acquisition Protocol (DA protocol). The DA protocol is a communication protocol used for data transmission between the test system and the device under test 130. This protocol is typically used to enable signal and data exchange between devices, ensuring interoperability in different communication environments.

[0059] The application-specific integrated circuit 122 acts as a bridge within the entire test unit 120, ensuring smooth signal transmission from the FPGA 121 to the device under test (DUT) 130. By converting the test signals, it ensures that the signal transmission format meets the requirements of the DUT 130, thereby guaranteeing the effectiveness and accuracy of the testing process. Simultaneously, the application of RS485 and digital audio protocols (DA protocols) guarantees stable signal transmission, ensuring the efficient operation of the entire test equipment.

[0060] In one possible implementation, the display unit 112 mainly consists of two parts: a decoder 1121 and a display screen 1122 (e.g., ...). Figure 3 (As shown). They work together to process, analyze, and visualize the input signal. The functions and working principles of these two parts will be explained in detail below.

[0061] First, the decoder 1121 is one of the core components of the display unit 112. Its main function is to receive the output signal and analyze it. The output signal is transmitted based on Pulse Code Modulation (PCM) bitstream, therefore the decoder 1121 needs to be able to recognize and process the PCM bitstream. PCM is a digital audio encoding method commonly used to represent analog signals. It converts analog signals into digital signals by sampling, quantizing, and encoding them. After receiving the output signal based on the PCM bitstream, the decoder 1121 first decodes the signal, restoring it to a digital signal that can be further processed.

[0062] Signal parsing involves detailed analysis of the PCM bitstream. Parsing the signal involves extracting key data such as frequency and amplitude. This process is crucial for accurate decoding and reconstructing the signal content. Based on the structure of the PCM bitstream, decoder 1121 can accurately extract relevant information, ensuring that the parsing results fully reflect the characteristics of the original signal.

[0063] After parsing, decoder 1121 generates a new signal, which is the processing result of the original signal. At this point, the parsed signal is ready to be passed to display screen 1122 for display. The quality of the parsed signal directly affects the display effect; therefore, decoder 1121 must ensure the accuracy and completeness of the parsing so that display screen 1122 can accurately reflect the required information.

[0064] Next, the display screen 1122's function is to present the decoded signal to the user in a visual form. Based on the decoded signal received from the decoder 1121, the display screen 1122 converts it into images, text, or other visual formats to intuitively display the signal content. The display screen 1122 can be an LCD screen, etc., depending on the device design requirements. Regardless of the type of display screen 1122, it needs to clearly present the data transmitted from the decoder 1121 and ensure that the user can accurately interpret this data.

[0065] The display unit 112 is designed so that complex input signals can be parsed and transformed into easily understandable and viewable information through the collaborative work of the decoder 1121 and the display screen 1122. The decoder 1121 provides in-depth analysis of the output signal, while the display screen 1122 is responsible for converting these analysis results into a visual form, providing users with accurate and clear display information.

[0066] In one possible implementation, the display unit 112 further includes a signal generator, which generates a prompt signal and sends it to the device under test 130 via a Low-Voltage Differential Signaling (LVDS) protocol. This process is a crucial part of the entire device, ensuring smooth collaboration and information transmission between devices.

[0067] First, the signal generator produces a prompt signal. This prompt signal serves to provide the device under test (DUT) 130 with a control command or notification, informing it that it needs to perform certain operations. The prompt signal not only acts as a "starter" for information flow within the device, but its transmission is also a crucial step in coordinating the entire signal generator process.

[0068] Once the alert signal is generated, the decoder 1121 will send it to the device under test 130 based on the LVDS protocol. LVDS is a high-speed, low-power digital signal transmission method widely used in high-precision and high-bandwidth signal transmission applications. Compared to traditional single-ended signal transmission, LVDS can effectively reduce signal interference, suppress noise, and ensure stable signal transmission. Therefore, choosing the LVDS protocol to send the alert signal ensures the efficiency and accuracy of signal transmission between devices.

[0069] The prompt signal transmitted via the LVDS protocol will reach the device under test 130. After receiving this signal, the device under test 130 will respond according to the content of the prompt signal. For example, the device under test 130 may start sending output signals according to the instructions of the signal generator to proceed with the next step.

[0070] In one possible implementation, the device further includes a power supply unit 140. For example... Figure 4 As shown, the power supply unit 140 is connected to both the host computer 110 and the testing unit 120. The power supply unit 140 plays a crucial role in the entire device. Its core function is to provide a stable and reliable power supply to all components within the device, ensuring their normal operation. Specifically, the power supply unit 140 provides the necessary power support.

[0071] First, the host computer 110, as the core control unit of the device, is responsible for coordinating and managing the operation of the entire device. The host computer 110 typically requires a relatively stable and sufficient power supply to support the operation of its processor, memory, and other auxiliary components. The test unit 120, on the other hand, is used to perform actual signal testing, data acquisition, and processing tasks, and its stable operation also depends on a continuous power supply. Therefore, the power supply unit 140 needs to be connected to both the host computer 110 and the test unit 120 via power lines to ensure that they both receive the necessary power support.

[0072] In the design of the power supply unit 140, the power consumption requirements of the device are typically considered, providing sufficient current and voltage output. To ensure the efficiency and reliability of the entire device, the power supply unit 140 is often equipped with multiple output ports, providing different voltage and current outputs to meet the power requirements of the host computer 110 and the test unit 120. Furthermore, the power supply unit 140 may also be equipped with certain protection measures, such as overcurrent protection, short-circuit protection, and overvoltage protection, to prevent abnormal situations during power supply and ensure the safe and stable operation of the device.

[0073] The power supply unit 140 is not only the energy source for the entire device, but its stability and reliability are also crucial for the normal operation of the device. If the power supply unit 140 fails or cannot provide sufficient power, the entire device may experience insufficient power or lose power, resulting in the device's inability to operate normally or an interruption in operation. Therefore, the power supply unit 140 should be designed with sufficient consideration of redundancy configuration and fault tolerance mechanisms to ensure the continuous and stable operation of the device.

[0074] The power supply unit 140, through its connection with the host computer 110 and the test unit 120, provides them with stable power support, ensuring the normal operation of all devices within the equipment. The design of the power supply unit 140 directly affects the reliability, stability, and long-term service life of the equipment; therefore, factors such as power output, protection functions, and redundancy design must be fully considered to achieve an efficient and safe power supply.

[0075] In one possible implementation, the device further includes an indicator light 150, such as... Figure 4 As shown, the indicator light 150 is connected to the power supply unit 140 and is used to display the real-time operating status of the power supply unit 140. Specifically, the working principle of the indicator light 150 is closely related to the output status of the power supply unit 140. When the power supply unit 140 is normally outputting power, the indicator light 150 will light up, indicating that the device has successfully started and begun normal operation. This design helps users intuitively understand whether the power supply is providing power normally, thereby determining whether the device is in normal operating condition.

[0076] Conversely, when power supply unit 140 is not outputting power, indicator light 150 will turn off. This usually means that power supply unit 140 is not working or is faulty, possibly due to power failure, current interruption, or other electrical faults. The indicator light 150 turning off provides intuitive feedback, quickly reminding operators or users to check power supply unit 140 and ensuring the equipment can be restored to normal operation in a timely manner.

[0077] The connection between indicator light 150 and power supply unit 140 serves as a signal indicator in the device. When power supply unit 140 outputs power, indicator light 150 lights up; otherwise, it turns off. This design effectively reflects the status of power supply unit 140, helping users quickly understand whether the device is working properly, thereby improving the operability of the device and the convenience of troubleshooting.

[0078] In one possible implementation, the host computer 110 also includes a memory connected to the microcontroller 111, which plays a crucial role. Specifically, the memory is one of the core components of the device, specifically used to store various data generated during the testing process, including test data and output signal data of the device under test 130. This design greatly enhances the functionality of the host computer 110, enabling the entire device to effectively record, process, and analyze test data.

[0079] First, during the test, the microcontroller 111 is responsible for receiving signals from the device under test (DUT) 130 in real time and processing these signals. These processed signals may include changes in various physical quantities, calculation results of test parameters, and the response of the DUT 130 under different conditions. The task of the microcontroller 111 is not only to perform preliminary processing of these signals, but may also include data filtering, signal amplification, noise suppression, and other operations to ensure the accuracy and reliability of the data.

[0080] After the microcontroller 111 completes signal processing, the processed data is transferred to the memory. The memory can be a hard disk, solid-state drive, or other type of storage medium, used to store this test data for a long time. This storage method allows users to access historical test data at any time for analysis, comparison, or report generation. Especially in scenarios involving long-term or complex testing, the memory provides sufficient space to store large amounts of test data, ensuring the integrity and continuity of the testing process.

[0081] During multiple tests of the device under test (DUT) 130, the memory not only saves the results of each test but also records the output signal data. The output signal data typically consists of the response signals emitted by the DUT 130 during the test, reflecting its operating status or performance under specific conditions. By storing this output signal data, users can perform detailed analysis later to evaluate the performance of the DUT 130 and determine whether it meets design or operating standards.

[0082] Furthermore, the memory works closely with other modules of the host computer 110, enabling the host computer 110 to achieve comprehensive monitoring and management of the entire testing process. By retrieving and analyzing data from the memory, the host computer 110 can provide users with detailed test reports, trend analysis charts, data comparisons, and other functions, helping users to make scientific evaluations and judgments about the performance of the device under test 130.

[0083] The memory plays a crucial role in the host computer 110. Through its close connection with the microcontroller 111, the memory can accurately record and save the test data and output signal data generated during the testing process. This not only provides necessary data support for subsequent analysis and decision-making, but also improves the traceability and manageability of the testing process, ensures the integrity and reliability of the test data, and enhances the overall performance and efficiency of the equipment.

[0084] In one possible implementation, the device further includes a Cyclic Redundancy Checker (CRC checker), which plays a crucial role in the signal parsing process and is connected between the device under test (DUT) 130 and the decoder 1121. Specifically, the main function of the CRC checker is to perform integrity verification on the received output signal to ensure its accuracy and reliability. In actual testing or application scenarios, the output signal typically undergoes complex transmission, processing, and conversion processes, which may introduce various interferences or errors, affecting signal quality. Therefore, the introduction of a CRC checker effectively ensures that the final output signal meets the predetermined target signal requirements.

[0085] A CRC checker first performs an integrity check on the output signal using a series of techniques. Integrity checking means comparing each component of the signal one by one to check for any loss, damage, or tampering. For example, during data transmission, factors such as noise, bandwidth limitations, and transmission medium quality may lead to packet loss, incorrect bit sequences, or signal distortion. These problems not only affect signal quality but may even distort the entire test result. To prevent this, the CRC checker verifies all aspects of the signal to ensure it is free of any abnormalities.

[0086] More specifically, the CRC checker also needs to check the form of the output signal to ensure it conforms to the expected target signal form. The target signal form is usually specified according to equipment design standards or specific application requirements. For example, the amplitude, frequency, and waveform of the output signal should all meet specific technical parameter requirements. In actual use, any deviation from the signal may indicate equipment failure or substandard performance. The CRC checker ensures consistency with the expected target by analyzing and comparing the characteristics of the output signal in real time, thereby effectively avoiding misjudgments and erroneous operations caused by signal anomalies.

[0087] Furthermore, the CRC checker's function extends beyond simply detecting signal integrity and compliance; it also provides alarm or feedback mechanisms. When a missing, erroneous, or inconsistent signal is detected in the output signal, the module immediately issues an alarm or performs corresponding corrective actions. This allows the device to promptly identify and address signal anomalies, preventing erroneous signals from further impacting subsequent data analysis or decision-making.

[0088] Through these verification functions, the CRC checker ensures the high quality and availability of the output signal. In practical applications, signal integrity directly affects the reliability of data and the accuracy of analysis results; therefore, the role of the CRC checker is indispensable. It not only improves the stability and reliability of the equipment but also provides a solid foundation for subsequent signal processing and data analysis, ensuring the normal operation and high efficiency of the entire device.

[0089] In one possible implementation, the microcontroller 111 plays a crucial role in the overall operation of the device. This module can also promptly detect and report any potential faults or anomalies during testing, thereby preventing performance degradation or distorted test results due to malfunctions. Through close connection with the host computer 110 and the test unit 120, the microcontroller 111 monitors the operating status of these critical components in real time, quickly detects potential faults, and generates detailed fault reports, providing necessary decision-making support for maintenance and operation personnel.

[0090] First, the microcontroller 111 ensures that monitoring and diagnostics of the entire device cover all critical components. The host computer 110 is typically responsible for data processing, analysis, and display, while the test unit 120 executes specific test tasks and signal acquisition. During normal device operation, these two components need to work in close coordination. However, in complex testing environments, any malfunction in any part can affect the entire testing process. Therefore, the primary task of the microcontroller 111 is to continuously monitor the operating status of the host computer 110 and the test unit 120, including checks on hardware status, software operation, and signal transmission.

[0091] The microcontroller 111, through its built-in monitoring algorithms and diagnostic logic, can quickly respond when abnormal signals, communication failures, hardware malfunctions, or software crashes are detected in real time. For example, when data communication between the host computer 110 and the test unit 120 is interrupted or lost, the microcontroller 111 will recognize this phenomenon and trigger an alarm mechanism; similarly, when a sensor in the test unit 120 malfunctions or displays abnormal data, the module can compare the sensor's output signal with the expected standard, detect the anomaly, and issue a warning.

[0092] Upon detecting a fault, the microcontroller 111 doesn't stop at simply identifying the fault; it further generates a detailed fault report based on the detection results. The fault report typically includes the time of the fault, the type of fault, the specific component affected, and possible causes. This information is crucial for subsequent fault analysis and maintenance. Operators can quickly locate the problem based on the fault report and take appropriate repair or adjustment measures, thereby reducing equipment downtime and improving equipment stability and reliability.

[0093] Furthermore, the intelligent and automated features of the microcontroller 111 enable it to automatically select appropriate diagnostic strategies based on different types of faults. For example, for hardware faults, it may activate hardware diagnostic tools to analyze current and voltage fluctuations on the circuit board; while for software faults, it may check software logs and analyze the stack information of program crashes. Through the comprehensive application of multiple methods, the microcontroller 111 can determine the nature and location of faults as accurately as possible, avoiding errors caused by human diagnosis.

[0094] In summary, the microcontroller 111 can not only promptly detect and identify various faults in the host computer 110 and the test unit 120 during the testing process, but also generate detailed fault reports, providing a scientific basis for subsequent repairs and improvements. Through early warning and accurate diagnosis of faults, it significantly improves the reliability of the equipment, ensures the stability of the testing process and the accuracy of the data, and is an indispensable and important component for ensuring the normal operation of the equipment.

[0095] The portable flight control computer host testing device provided in this application embodiment is small in size, easy to carry and move, and can be used flexibly in different locations. It does not require moving the device under test to a fixed test location, which greatly reduces the operational complexity and uncertainty caused by space and environmental limitations.

[0096] The above provides a detailed description of a test device for a portable flight control computer host provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0097] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0098] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A testing device for a portable flight control computer host, characterized in that, The device includes: a host computer and a testing unit; the testing unit includes a field-programmable gate array (FPGA); the host computer includes a microcontroller and a display unit; The microcontroller is communicatively connected to the display unit, the FPGA, and the device under test (DUT); the FPGA is connected to the DUT; the display unit is connected to the DUT; the DUT includes a flight control computer host; the FPGA stores various excitation signals for testing the flight control computer host; The microcontroller is used to receive the test requirements of the device under test and send the test requirements to the FPGA via Ethernet; The FPGA is used to output test signals for the device under test (DUT) based on the test requirements, and to send the test signals to the DUT based on the 1553B protocol, so that the DUT generates an output signal based on the test signals; the test signal is one of the excitation signals. The display unit is used to analyze and display the output signal.

2. The device according to claim 1, characterized in that, The microcontroller is also used to monitor whether the working status of each module in the device under test is normal. The display unit is also used to display the names of modules in the device under test that are malfunctioning.

3. The device according to claim 1, characterized in that, The test unit further includes: an application-specific integrated circuit (ASIC); the ASIC is connected to both the FPGA and the device under test (DUT). The FPGA is also used to send the test signal to the dedicated integrated circuit based on the RS485 protocol when the signal form of the test signal does not conform to the target signal form. The dedicated integrated circuit is used to convert the signal form of the test signal into the target signal form to obtain a converted signal, and to send the converted signal as a test signal to the device under test based on the data acquisition protocol DA protocol.

4. The device according to claim 1, characterized in that, The display unit includes a decoder and a display screen; The decoder is used to receive the output signal based on the Pulse Code Modulation (PCM) code stream, and to perform signal analysis on the output signal to obtain the analyzed signal. The display screen is used to display the parsed signal.

5. The device according to claim 4, characterized in that, The display unit also includes a signal generator: A signal generator is used to generate a prompt signal and send the prompt signal to the device under test based on the Low Voltage Differential Signaling (LVDS) protocol to prompt the device under test to issue the output signal.

6. The device according to claim 1, characterized in that, The device further includes a power supply unit; the power supply unit is connected to the host computer and the test unit respectively. The power supply unit is used to supply power to the host computer and the test unit.

7. The device according to claim 6, characterized in that, The device further includes: an indicator light; the indicator light is connected to the power supply unit; The indicator light illuminates when the power unit outputs power; otherwise, the indicator light is off.

8. The device according to claim 1, characterized in that, The host computer also includes a memory; the memory is connected to the microcontroller. The memory is used to store the test data and output signal data generated by the device under test during the test.

9. The device according to claim 4, characterized in that, The device also includes a Cyclic Redundancy Check (CRC) checker; the CRC checker is connected between the device under test and the decoder. The CRC checker is used to perform integrity verification on the output signal to ensure that the output signal conforms to the expected target signal form and that there is no signal loss or error.

10. The device according to claim 1, characterized in that, The microcontroller is also used for; The system detects faults in the host computer and the test unit during the testing process and generates fault reports based on the test results.

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