Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel. The array substrate comprises a first conductive layer, a second conductive layer and a third conductive layer, a first insulating layer is arranged between the first conductive layer and the second conductive layer; a second insulating layer is arranged between the second conductive layer and the third conductive layer; the first conductive layer comprises a first signal line, the second conductive layer comprises a first switching part, and the second conductive layer comprises a second switching part; the first insulating layer is provided with a first via hole, and the first switching part is filled in the first via hole and is electrically connected with the first signal line. A second via hole is formed in the second insulating layer, and the second switching part is filled in the second via hole and electrically connected with the first switching part; in the thickness direction of the array substrate, the orthographic projection of the second via hole on the first conductive layer is located outside the orthographic projection of the first via hole on the first conductive layer. The display panel can solve the problem of poor display.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the development of display technology, array substrates are being used more and more widely, and the requirements for array substrates are becoming increasingly stringent.

[0003] In some array substrates, such as liquid crystal array substrates employing FFS (Fringe Field Switching) architecture, the array substrate typically has multiple conductive layers, some of which require transition structures. For example... Figures 1 to 4 As shown, Figures 1 to 4 This diagram illustrates the product structure formed by the main steps in the fabrication of an array substrate in the related art. The array substrate includes a first conductive layer 11', a second conductive layer 13', a third conductive layer 15', a first insulating layer 12', and a second insulating layer 14'. The second conductive layer 13' and the third conductive layer 15' contain transition structures to electrically connect related structures in the conductive layers (not shown) on the side of the first conductive layer 11' and the third conductive layer 15' away from the first conductive layer 11'. In the related art, both the first insulating layer 12' and the second insulating layer 14' include an insulating material layer and a slope modification layer. The etching rates of the slope modification layer and the insulating material layer are different, leading to undercutting issues at the slope modification layer. Therefore, the first insulating layer 12' and the second insulating layer 14' cannot be etched together. Furthermore, to avoid contact with the slope modification layer of the first insulating layer 12' during the etching of the second insulating layer 14', the second conductive layer 13' is used as an etching barrier layer.

[0004] However, as Figure 3 As shown, in related technologies, the opening in the second insulating layer 14' is located within the area where the opening in the first insulating layer 12' is located. Within the opening in the first insulating layer 12', the second conductive layer 13' is not a flat surface, but rather has corners, i.e. Figure 3 In the Z1 region, during the etching of the second insulating layer 14', a lateral etching process occurs. Due to the influence of the corner topography of the second conductive layer 13', the second insulating layer 14' will have an undercut problem in the Z1 region. Figure 4 As shown, when the third conductive layer 15' is subsequently filled into the opening of the second insulating layer 14', the third conductive layer 15' will have a breakage problem in the Z1 region, which will cause the display panel to have display defects and seriously affect the yield of the array substrate. Utility Model Content

[0005] This invention provides an array substrate and a display panel to improve the problem of poor display quality in display panels.

[0006] According to one aspect of the present invention, an array substrate is provided, the array substrate comprising: a first conductive layer, a second conductive layer and a third conductive layer;

[0007] A first insulating layer is disposed between the first conductive layer and the second conductive layer; a second insulating layer is disposed between the second conductive layer and the third conductive layer; the first conductive layer includes a first signal line, the second conductive layer includes a first transition portion, and the second conductive layer includes a second transition portion;

[0008] The first insulating layer has a first via, and the first adapter portion is filled into the first via and electrically connected to the first signal line; the second insulating layer has a second via, and the second adapter portion is filled into the second via and electrically connected to the first adapter portion.

[0009] Along the thickness direction of the array substrate, the orthographic projection of the second via on the first conductive layer is located outside the orthographic projection of the first via on the first conductive layer.

[0010] Optionally, along the thickness direction of the array substrate, the orthographic projection of the first via on the first conductive layer lies within the orthographic projection of the second insulating layer on the first conductive layer.

[0011] Optionally, the array substrate includes a display area and a non-display area at least partially surrounding the display area; the first transition portion and the second transition portion are located in the non-display area.

[0012] Optionally, the array substrate includes a plurality of pixel circuits located in the display area, each pixel circuit including a transistor, the gate of the transistor being located in the first conductive layer;

[0013] The array substrate further includes pixel electrodes and a common electrode located in the display area, the common electrode being located in the second conductive layer and the pixel electrodes being located in the third conductive layer.

[0014] Optionally, the first insulating layer includes a gate insulating layer and a first passivation layer; the gate insulating layer is located between the first conductive layer and the first passivation layer.

[0015] Optionally, the first passivation layer includes a first insulating material layer and a first slope modification layer stacked on the gate insulating layer.

[0016] Optionally, the second insulating layer includes an anti-reduction layer, a second insulating material layer, and a second slope modification layer sequentially stacked on the second conductive layer.

[0017] Optionally, the first conductive layer is a metal layer; the second conductive layer is an indium tin oxide layer; and the third conductive layer is an indium tin oxide layer.

[0018] Optionally, the array substrate further includes bonding pads located on the side of the second transition portion away from the first conductive layer and electrically connected to the second transition portion.

[0019] According to another aspect of the present invention, a display panel is provided, the display panel comprising the array substrate described above.

[0020] The technical solution of this utility model embodiment uses an array substrate comprising a first conductive layer, a second conductive layer, and a third conductive layer; a first insulating layer is disposed between the first and second conductive layers; a second insulating layer is disposed between the second and third conductive layers; the first conductive layer includes a first signal line, the second conductive layer includes a first transition portion, and the second conductive layer includes a second transition portion; a first via is formed in the first insulating layer, and the first transition portion is filled into the first via and electrically connected to the first signal line; a second via is formed in the second insulating layer, and the second transition portion is filled into the second via and electrically connected to the first transition portion; along the thickness direction of the array substrate, the orthographic projection of the second via on the first conductive layer is located outside the orthographic projection of the first via on the first conductive layer. The second via is disposed in the area outside the first via. At this time, along the thickness direction of the array substrate, the portion of the second conductive layer within the orthographic projection of the second via is a flat structure, and there is no undercutting problem when etching the second insulating layer to form the second via. Therefore, the second transition structure formed by subsequent covering will not break, thereby improving the display defect problem of the display panel and greatly improving the yield of the display panel.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1 to 4 This is a schematic diagram of the product structure formed by the main steps in the fabrication of an array substrate in a related technology.

[0024] Figure 5This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present utility model;

[0026] Figure 7 A cross-sectional view of a display panel provided for an embodiment of this utility model;

[0027] Figure 8 A schematic diagram of the structure of a first passivation layer provided in an embodiment of this utility model;

[0028] Figure 9 This is a schematic diagram of the structure of a second insulating layer provided in an embodiment of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] Figure 5 This is a schematic diagram of an array substrate provided in an embodiment of the present invention, with reference to... Figure 5The array substrate includes a first conductive layer 11, a second conductive layer 13, and a third conductive layer 15; a first insulating layer 12 is disposed between the first conductive layer 11 and the second conductive layer 13; a second insulating layer 14 is disposed between the second conductive layer 13 and the third conductive layer 15; the first conductive layer 11 includes a first signal line 111, the second conductive layer 13 includes a first transition portion 131, and the third conductive layer 15 includes a second transition portion 151; the first insulating layer 12 has a first via 121, the first transition portion 131 is filled into the first via 121 and electrically connected to the first signal line 111; the second insulating layer 14 has a second via 141, the second transition portion 151 is filled into the second via 141 and electrically connected to the first transition portion 131; along the thickness direction of the array substrate, the orthographic projection of the second via 141 on the first conductive layer 11 is located outside the orthographic projection of the first via 121 on the first conductive layer 11.

[0032] Specifically, the array substrate is, for example, an array substrate corresponding to a liquid crystal display panel. The multilayer conductive layers of the array substrate can be configured with structures such as thin-film transistors and pixel electrodes corresponding to sub-pixels. The first signal line 111 in the first conductive layer 11 can be a signal line in the array substrate used to transmit signals to the pixel circuit, such as a scan signal line or a data signal line. At least some of the signal lines in the array substrate can be configured as double-layer traces to save wiring space and reduce bezel size. The double-layer traces are connected by a second conductive layer 13 and a third conductive layer 15. Alternatively, the first signal line 111 can be connected to a pad through a connection structure in the second conductive layer 13 and the third conductive layer 15, and electrically connected to the driver chip through the pad, thereby enabling the driver chip to provide corresponding signals to the first signal line.

[0033] The portion of the second conductive layer 13 electrically connected to the first signal line 111 can be understood as the first transition structure 131. It is also understood that the second conductive layer 13 may contain other structures insulated from the first transition structure 131, such as the common electrode of a sub-pixel. Similarly, the portion of the third conductive layer 15 electrically connected to the first transition structure 131 can be understood as the second transition structure 151; of course, the third conductive layer 15 may also contain other structures insulated from the second transition structure 151, such as the pixel electrode of a sub-pixel. A first via 121 is formed on the first insulating layer 12, exposing the first signal line 111, thus electrically connecting the first transition structure 131 to the first signal line 111. The portion of the first transition structure 131 located in the first via 121 has a corner, and the flat portion at the bottom has a small area. If the second insulating layer 14 inside the first via 121 is etched to expose the first transition structure 131 inside the first via 121, the etched second insulating layer 14 will have an undercut problem, causing the second transition structure in the subsequently formed third conductive layer 15 to break.

[0034] In this embodiment, the orthographic projection of the second via 141 on the first conductive layer 11 is outside the orthographic projection of the first via 121 on the first conductive layer 111. That is, the second via 141 is disposed in the area outside the first via 121. At this time, along the thickness direction of the array substrate, the portion of the second conductive layer 13 within the orthographic projection of the second via 141 is a flat structure. There is no undercut problem when etching the second insulating layer 14 to form the second via 141. Therefore, the second transition structure 151 formed by subsequent covering will not break, thereby improving the display defect problem of the display panel and greatly improving the yield of the display panel.

[0035] The technical solution of this embodiment uses an array substrate comprising a first conductive layer, a second conductive layer, and a third conductive layer; a first insulating layer is disposed between the first and second conductive layers; a second insulating layer is disposed between the second and third conductive layers; the first conductive layer includes a first signal line, the second conductive layer includes a first transition portion, and the second conductive layer includes a second transition portion; a first via is formed in the first insulating layer, and the first transition portion is filled into the first via and electrically connected to the first signal line; a second via is formed in the second insulating layer, and the second transition portion is filled into the second via and electrically connected to the first transition portion; along the thickness direction of the array substrate, the orthographic projection of the second via on the first conductive layer is located outside the orthographic projection of the first via on the first conductive layer. The second via is disposed in the area outside the first via. At this time, along the thickness direction of the array substrate, the portion of the second conductive layer within the orthographic projection of the second via is a flat structure, and there is no undercutting problem when etching the second insulating layer to form the second via. Therefore, the second transition structure formed by subsequent covering will not break, thereby improving the display defect problem of the display panel and greatly improving the yield of the display panel.

[0036] Along the thickness direction of the array substrate, the orthographic projection of the second via 141 on the first conductive layer 11 is outside the orthographic projection of the first via 121 on the first conductive layer 11. This can be achieved by forming a corresponding opening on the mask corresponding to the second via 141, located outside the corresponding opening on the mask corresponding to the first via 121. During etching, even if the actual second via 141 overlaps with the first via 121 due to process errors, the etching direction of the second insulating layer is downwards from the center of the second via 141 and outwards to both sides. Therefore, even if the second via 141 exposes the corner of the first transition structure 131, the insulating layer above the corner of the first transition structure 131 is etched away, and no undercutting problem occurs on the second insulating layer.

[0037] Optionally, continue to refer to Figure 5Along the thickness direction of the array substrate, the orthographic projection of the first via 121 onto the first conductive layer 11 lies within the orthographic projection of the second insulating layer 14 onto the first conductive layer 11. That is, the second insulating layer 14 filling the first via 121 is not perforated, so that the first conductive layer corresponding to the first via 121 is protected by an insulating layer (the second insulating layer 14), while the other parts of the first conductive layer are protected by the first insulating layer 12. Therefore, this embodiment ensures that the first conductive layer 11 is entirely protected by an insulating layer, thereby improving the corrosion resistance of the circuitry within the first conductive layer 11.

[0038] Optionally, Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present utility model. Figure 7 This is a cross-sectional view of a display panel provided in an embodiment of the present invention. (Reference) Figure 6 and Figure 7 The display panel includes an array substrate, a liquid crystal layer 16, and a color filter substrate 17. The array substrate includes a display area AA and a non-display area NAA that at least partially surrounds the display area AA. A first transition portion 131 and a second transition portion 151 are located in the non-display area NAA.

[0039] Specifically, such as Figure 7As shown, the array substrate also includes a substrate 10, an active layer 20, and a fifth conductive layer 21. The portion of the array substrate 10 located in the display area AA includes multiple pixel circuits, each pixel circuit including a transistor, the gate of which is located in the first conductive layer 11. The array substrate also includes pixel electrodes 152 and a common electrode 132 located in the display area. The common electrode 132 is located in the second conductive layer 13, and the pixel electrode 152 is located in the third conductive layer 15. The substrate 10 is made of materials such as glass, quartz, silicon, acrylic, or polycarbonate; alternatively, the substrate 10 may be a flexible substrate made of materials such as polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET), or combinations thereof. Scan lines and data lines can be disposed in the first conductive layer 11. The first conductive layer 11 can be made of materials such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of these metals such as Al / Mo or Cu / Mo. The first insulating layer 12 includes a gate insulating layer 121 and a first passivation layer 122; the gate insulating layer 121 is located between the first conductive layer 11 and the first passivation layer 122. The gate insulating layer 121 can be made of materials such as silicon oxide or silicon nitride. The source and drain of a transistor can be formed in the fifth conductive layer 21. It is understood that other films, such as a planarization layer, may also be disposed between the first passivation layer 122 and the second conductive layer 13. In the non-display area (NAA), the gate insulating layer 121 and the first passivation layer 122 are in direct contact.

[0040] It should be noted that, as Figure 7 As shown, the liquid crystal layer 16 includes multiple liquid crystal molecules. An electric field, approximately parallel to the light-emitting surface of the display panel, can be generated between the pixel electrode 152 and the common electrode 132, meaning the display panel is an FFS (Freeform-Film) structure display panel. The color filter substrate 17 includes a color filter and a black matrix BM. The color filter includes, for example, a red color filter R, a green color filter G, and a blue color filter B. Light emitted from the liquid crystal layer 16, after passing through the red color filter R, is emitted only as red light; light emitted from the liquid crystal layer 16, after passing through the green color filter, is emitted only as green light; and light emitted from the liquid crystal layer 16, after passing through the blue color filter B, is emitted only as blue light.

[0041] Optionally, Figure 8 A schematic diagram of the structure of a first passivation layer provided in an embodiment of this utility model is shown below. Figure 8The first passivation layer 122 includes a first insulating material layer 1221 and a first slope modification layer 1222 stacked on the gate insulating layer 121. The materials of the first insulating material layer 1221 and the first slope modification layer 1222 can be silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. The etch rate of the first slope modification layer 1222 (etch rate of approximately 24000 A / min) is greater than the etch rate of the first insulating material layer 1221 (etch rate of approximately 12000 A / min). For example, the etch rate of the first slope modification layer 1222 is twice that of the first insulating material layer 1221, thereby forming a chamfer at the opening of the first aperture 121 to reduce the slope of the inner wall of the aperture, thereby avoiding the problem of the first transition structure 131 breaking within the first aperture 121.

[0042] Optionally, Figure 9 This is a schematic diagram of the structure of a second insulating layer provided in an embodiment of the present invention, with reference to... Figure 9 The second insulating layer includes an anti-reduction layer 141, a second insulating material layer 142, and a second slope modification layer 143, which are sequentially stacked on the second conductive layer.

[0043] Specifically, the materials of the anti-reduction layer 141, the second insulating material layer 142, and the second slope modification layer 143 can be silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. The etching rate of the second slope modification layer 143 (approximately 24,000 Å / min) is greater than that of the second insulating material layer 142 (approximately 12,000 Å / min). For example, the etching rate of the second slope modification layer 143 is twice that of the second insulating material layer 142, thereby forming a chamfer at the opening of the second aperture 141 to reduce the slope of the inner wall of the aperture, thus preventing the second transition structure 151 from breaking within the second aperture 141. The etching rate of the anti-reduction layer 141 can be slightly greater than that of the second insulating material layer 142. The anti-reduction layer 141 is used to protect the second conductive layer 13 and prevent it from being etched.

[0044] Optionally, in the above embodiment, the first conductive layer 11 is a metal layer, the second conductive layer 13 is an indium tin oxide (ITO) layer, and the third conductive layer 15 is an ITO layer. Both the second conductive layer 13 and the third conductive layer 15 are transparent conductive layers, which can avoid obstructing the optical fiber. Since the conductivity of the ITO layer is weaker than that of the metal layer, it can serve as a transition layer in the non-display area. The signals in the array substrate are mainly transmitted in the metal layer, thereby reducing the bezel of the display panel without affecting the stability of signal transmission.

[0045] Optionally, the array substrate further includes bonding pads (not shown), which are located on the side of the second transition portion away from the first conductive layer and are electrically connected to the second transition portion.

[0046] Specifically, the bonding pads, such as metal pads, are used to bond with the driver chip. The driver chip then electrically connects to the first signal line via the bonding pads, the second adapter structure, and the first adapter structure, enabling it to transmit electrical signals to the first signal line. Of course, in some other embodiments, the second adapter structure can also be an electrical connection to the signal line that forms a double-metallic layer signal trace with the first signal line.

[0047] Based on the same inventive concept, this utility model also provides a display panel, such as... Figure 6 As shown. The display panel includes the array substrate provided in any embodiment of this utility model. The display panel can be a display panel in a mobile phone, tablet computer, MP3 player, MP4 player, smartwatch, smart helmet, or other wearable device. Since the display panel provided in the embodiments of this utility model includes the array substrate provided in any embodiment of this utility model, it also has the same beneficial effects, which will not be described again here.

[0048] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0049] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. An array substrate, characterized in that, The array substrate includes: a first conductive layer, a second conductive layer, and a third conductive layer; A first insulating layer is disposed between the first conductive layer and the second conductive layer; a second insulating layer is disposed between the second conductive layer and the third conductive layer; the first conductive layer includes a first signal line, the second conductive layer includes a first transition portion, and the second conductive layer includes a second transition portion; The first insulating layer has a first via, and the first adapter portion is filled into the first via and electrically connected to the first signal line; the second insulating layer has a second via, and the second adapter portion is filled into the second via and electrically connected to the first adapter portion. Along the thickness direction of the array substrate, the orthographic projection of the second via on the first conductive layer is located outside the orthographic projection of the first via on the first conductive layer.

2. The array substrate according to claim 1, characterized in that, Along the thickness direction of the array substrate, the orthographic projection of the first via on the first conductive layer lies within the orthographic projection of the second insulating layer on the first conductive layer.

3. The array substrate according to claim 1, characterized in that, The array substrate includes a display area and a non-display area that at least partially surrounds the display area; the first transition portion and the second transition portion are located in the non-display area.

4. The array substrate according to claim 3, characterized in that, The array substrate includes a plurality of pixel circuits located in the display area, each pixel circuit including a transistor, the gate of the transistor being located in the first conductive layer; The array substrate further includes pixel electrodes and a common electrode located in the display area, the common electrode being located in the second conductive layer and the pixel electrodes being located in the third conductive layer.

5. The array substrate according to claim 1, characterized in that, The first insulating layer includes a gate insulating layer and a first passivation layer; the gate insulating layer is located between the first conductive layer and the first passivation layer.

6. The array substrate according to claim 5, characterized in that, The first passivation layer includes a first insulating material layer and a first slope modification layer stacked on the gate insulating layer.

7. The array substrate according to claim 1, characterized in that, The second insulating layer includes an anti-reduction layer, a second insulating material layer, and a second slope modification layer, which are sequentially stacked on the second conductive layer.

8. The array substrate according to claim 1, characterized in that, The first conductive layer is a metal layer; the second conductive layer is an indium tin oxide layer; and the third conductive layer is an indium tin oxide layer.

9. The array substrate according to claim 1, characterized in that, The array substrate further includes bonding pads, which are located on the side of the second transition portion away from the first conductive layer and are electrically connected to the second transition portion.

10. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1-9.

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