Semiconductor device

Abstract

A semiconductor device includes a first wafer including a first wafer edge and a first wafer seal ring, a second wafer bonded to the first wafer, the second wafer including a second wafer edge and a second wafer seal ring, and a test line portion including at least one of a first wafer test line portion in the first wafer and a second wafer test line portion in the second wafer. The first wafer test line is partially located in the first wafer and located between the first wafer end edge and the first wafer sealing ring, or the second wafer test line is partially located in the second wafer and located between the second wafer end edge and the second wafer sealing ring.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Wafers (such as semiconductor wafers) may include sealing rings that also serve as dicing line seals or cut seals. Sealing rings can be used for a variety of purposes and functions. They may serve as boundaries surrounding the wafer, encapsulating active circuitry and other components, and protecting the circuitry from external contamination, moisture, and mechanical damage. Sealing rings may also provide electronic and thermal isolation between the active circuitry on the wafer and components outside the sealing ring. Sealing rings may also increase the structural strength of the wafer and thus inhibit wafer deformation or cracking.

[0003] The sealing ring may also include alignment marks or positioning to aid in the precise positioning of the wafer during assembly and packaging, thereby improving the overall quality and reliability of the device containing the wafer. The sealing ring may also provide dicing lines as guides for the dicing tool to precisely cut the wafer into chips. Utility Model Content

[0004] According to some embodiments of this disclosure, a semiconductor device includes a first wafer, a second wafer, and a test line portion. The first wafer includes a first wafer edge and a first wafer sealing ring. The second wafer is bonded to the first wafer and includes a second wafer edge and a second wafer sealing ring. The test line portion includes a first wafer test line portion located within the first wafer, between the first wafer edge and the first wafer sealing ring, and a second wafer test line portion located within the second wafer, between the second wafer edge and the second wafer sealing ring.

[0005] According to some embodiments of this disclosure, a semiconductor device includes a first wafer, a second wafer, and a test line portion. The first wafer includes a first wafer edge and a first wafer sealing ring. The second wafer is bonded to the first wafer and includes a second wafer edge and a second wafer sealing ring. The test line portion includes a first wafer test line portion located within the first wafer, between the first wafer edge and the first wafer sealing ring, and a second wafer test line portion located within the second wafer, between the second wafer edge and the second wafer sealing ring. The second wafer test line portion includes a test line portion metallic feature disposed on a test tool electrically coupled to it.

[0006] According to some embodiments of this disclosure, a semiconductor device includes a first wafer, a second wafer, and a test line portion. The first wafer includes a first wafer edge and a first wafer sealing ring. The second wafer is bonded to the first wafer and includes a second wafer edge and a second wafer sealing ring. The test line portion includes a first wafer test line portion located within the first wafer, between the first wafer edge and the first wafer sealing ring, and a second wafer test line portion located within the second wafer, between the second wafer edge and the second wafer sealing ring. The second wafer further includes a wafer substrate and a conductive post located within the wafer substrate, the conductive post being configured to electrically couple the second wafer to the first wafer. Attached Figure Description

[0007] The best understanding of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1A A vertical cross-sectional view of a semiconductor device is provided to illustrate the embodiments described herein;

[0009] Figure 1B This is a schematic diagram of a semiconductor device from top to bottom in the Z direction, according to the embodiments herein;

[0010] Figure 1C This is a schematic diagram illustrating an exploded view of a semiconductor device according to embodiments herein;

[0011] Figure 2A According to the embodiments herein, the intermediate structure includes a first bonding film on a carrier substrate;

[0012] Figure 2B According to the embodiments herein, the intermediate structure includes a first wafer and a third wafer on a first bonding film;

[0013] Figure 2C According to the embodiments herein, the intermediate structure includes a first sealing layer on the first bonding film;

[0014] Figure 2D According to the embodiments herein, the intermediate structure includes a second layer on a second carrier substrate;

[0015] Figure 2E According to the embodiments herein, the intermediate structure includes a second layer on top of the first layer;

[0016] Figure 2F To illustrate the intermediate structure after removing the second carrier substrate according to the embodiments herein;

[0017] Figure 2GAccording to the embodiments herein, the intermediate structure includes multiple openings in the passivation layer and the second bonding film;

[0018] Figure 2H According to the embodiments described herein, the embodiment structure includes metal protrusions on a wafer bonding pad in a multilayer opening;

[0019] Figure 3 To illustrate the process of forming a semiconductor device according to the embodiments herein;

[0020] Figure 4 This is a schematic diagram illustrating a semiconductor device testing method according to the embodiments described herein;

[0021] Figure 5A A vertical cross-sectional view of a semiconductor device having a first alternative design is illustrated according to embodiments herein.

[0022] Figure 5B This is a schematic diagram illustrating a test method for a semiconductor device having a first alternative design, according to embodiments herein;

[0023] Figure 6 A flowchart illustrating a semiconductor device testing method is provided below, based on the embodiments described herein.

[0024] Figure 7 A vertical cross-sectional view of a semiconductor device having a second alternative design is provided according to embodiments herein.

[0025] Figure 8 A vertical cross-sectional view of a semiconductor device having a third alternative design is provided in accordance with the embodiments herein.

[0026] [Symbol Explanation]

[0027] 10: First floor

[0028] 20: Second layer

[0029] 100: Semiconductor devices

[0030] 100a: Sidewall

[0031] 102: First carrier substrate

[0032] 102a: Sidewall

[0033] 103: Contact gasket

[0034] 104: Gap-filling dielectric layer

[0035] 105: Wafer bonding film

[0036] 107: Chip bonding pad

[0037] 108: Chip substrate

[0038] 109: Gate electrode

[0039] 110: First chip

[0040] 110a: First chip edge

[0041] 110b: Rear side

[0042] 110f: Front side

[0043] 112: Interlayer dielectric layer

[0044] 113: Backside Etching Stop Layer

[0045] 114: Intermetallic dielectric layer

[0046] 114a: Etching Stop Layer

[0047] 116: Metallic characteristics

[0048] 116T: Metallic characteristics of the test line

[0049] 117-1: First wafer sealing ring

[0050] 117-2: Second wafer sealing ring

[0051] 117T: Test lead sealing ring

[0052] 118: First encapsulation layer

[0053] 118a: Sidewall

[0054] 119: Passivation layer

[0055] 120: Second chip

[0056] 120a: Second chip edge

[0057] 120b: Dorsal side

[0058] 120f: Front

[0059] 128: Second encapsulation layer

[0060] 128a: Sidewall

[0061] 129: Through-silicon vias

[0062] 130: Third chip / Dummy chip

[0063] 138: Passivation layer

[0064] 141: First bonding film

[0065] 142: Second bonding film

[0066] 143: First wafer bonding layer

[0067] 144: Third wafer bonding layer

[0068] 145: Alignment Mark

[0069] 150: Bonding layer

[0070] 157: Joint layer joint gasket

[0071] 170: Functional Circuit Section

[0072] 180-2: Second wafer test line section

[0073] 190: Metal bumps

[0074] 202: Second carrier substrate

[0075] 310: Steps

[0076] 320: Steps

[0077] 330: Steps

[0078] OT: Opening

[0079] 400: Wafer Acceptance Testing Tools

[0080] 401: Cable

[0081] 402: Probe

[0082] 410: Processing device

[0083] 420: Memory device

[0084] 430: Monitor

[0085] 440: Input / output device

[0086] 607: Test lead joint gasket

[0087] 610: Steps

[0088] 620: Steps

[0089] 629: Through Silicon Via

[0090] 630: Steps

[0091] 640: Steps

[0092] 657: Joint layer joint gasket Detailed Implementation

[0093] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define relationships between the various embodiments and / or configurations discussed.

[0094] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0095] Related chips (e.g., semiconductor chips, stacks of integrated semiconductor chips, chiplets, etc.) such as central processing unit (CPU) chips or static random access memory (SRAM) chips may include a hermetically sealed ring design. In these related chips, there may be no metal patterns or devices located outside the hermetically sealed ring (e.g., between the chip edge and the hermetically sealed ring). In these related chips, a portion of the chips located outside the hermetically sealed ring may be substantially uniformly distributed around the chip. That is, the distance variation between the chip edge and the hermetically sealed ring may be around 10% (e.g., not exceeding 10%).

[0096] The embodiments disclosed herein may include a novel semiconductor device comprising a test line portion (e.g., a wafer overhang test line portion). The embodiments disclosed herein may include the test line portion within at least one wafer (e.g., a semiconductor wafer) of a wafer module (e.g., a small wafer stack) of multiple stacked wafers to provide design variability. The test line portion may be located between a sealing ring in the wafer and the wafer edge (e.g., a wafer edge).

[0097] The test lead portion may contain test lead electrical connection designs that can be used for tool testing. In this embodiment, the test lead portion may be configured to allow testing of the semiconductor device, such as through a wafer acceptance testing (WAT) apparatus. In this embodiment, the test lead portion may be used to monitor the effects of a process (e.g., manufacturing process) on the semiconductor device (e.g., the effect on integrated circuits within the semiconductor device). In this embodiment, the test lead portion may be used to monitor the damaging effects of discharge on the semiconductor device. The test lead portion may be observable from a cross-section of the semiconductor device.

[0098] In the embodiments described herein, the test line portion may be included within a wafer protrusion structure (e.g., a portion of the wafer outside the wafer sealing ring) and may be referred to as a wafer protrusion structure test line portion. The wafer protrusion structure test line portion may share the same substrate (e.g., a semiconductor substrate; a silicon substrate) as other portions of the wafer. In the wafer protrusion structure test line portion, the distance between the sealing ring and the wafer edge may be greater than in other portions of the wafer. The wafer protrusion structure test line portion may include a metal layer pattern. In the embodiments described herein, the wafer protrusion structure test line portion may include test lines outside the wafer sealing ring surrounding a functional circuit portion of the wafer. The wafer protrusion structure test line portion may be provided as a process monitor. The wafer protrusion structure test line portion may or may not include its own sealing ring (e.g., a sealing ring outside the wafer sealing ring).

[0099] The test line section may offer innovative designs. The test locations for the test line section may be provided by performing a lithography process. In the lithography process, a passivation layer may be etched through openings in a patterned mask via an etching process to expose the test terminals. In the embodiments described herein, the etching process may expose metal pads (e.g., aluminum pads), which may be used for tool testing such as wafer acceptance testing (WAT) tool testing.

[0100] In the embodiments described herein, the semiconductor device may include a first wafer and a second wafer bonded to the first wafer. The semiconductor device may include a substrate and the first wafer possibly located at a first horizontal position on the substrate. The second wafer may be located at a second horizontal position adjacent to the first horizontal position, and the width of the second wafer is greater than the width of the first wafer. A third wafer may also be located at a first horizontal position adjacent to the first wafer. The third wafer may include a dummy wafer (e.g., a non-functional wafer).

[0101] In the embodiments described herein, the second wafer may include a second wafer test line portion. The second wafer may be electrically coupled to the first wafer via an electrical connection (e.g., through a through-silicon via; TSV). The second wafer test line portion in the second wafer may therefore be used as a test line. Specifically, the second wafer test line portion in the second wafer may therefore be used to monitor the effects of processes (e.g., manufacturing processes) on the semiconductor device (e.g., the first and second wafers) and on the integrated circuits within the semiconductor device. Specifically, test locations may be formed in the second wafer by an etching process. For example, test locations may include metal pads (e.g., aluminum pads) exposed during the etching process. Specifically, the metal pads may contact one or more probes of a testing tool (e.g., a wafer acceptance test (WAT) tool).

[0102] In some embodiments herein, the first wafer may include a first wafer test line portion. The first wafer may be electrically coupled to the second wafer via an electrical connection (e.g., through a through-silicon via (TSV)). The first wafer test line in the first wafer can therefore be used as a test line. In particular, the first wafer test line portion in the first wafer may be used to monitor the effects of the process on the semiconductor device (e.g., the first wafer and the second wafer) and on the integrated circuits in the semiconductor device. Similarly, test locations may be formed in the second wafer as described above and electrically coupled to the first wafer test line portion in the first wafer.

[0103] In some embodiments herein, the first wafer may include a first wafer test line portion. However, the first wafer test line portion may not be electrically coupled to the first wafer and / or the second wafer. In this case, the first wafer test line portion may not be used for testing but may serve as, for example, a heat dissipation structure. The first wafer test line portion may also be used to reduce the area of ​​the third wafer. In some embodiments herein, the first wafer test line portion may completely eliminate the need for the third wafer. This may help reduce costs and balance pressures (e.g., pressures caused by a mismatch in coefficients of thermal expansion (CTEs)) at the horizontal position of the first wafer (e.g., at the same horizontal position, with the same structure).

[0104] In some embodiments described herein, the first wafer may include a first wafer test line portion, and the second wafer may include a second wafer test line portion. This may allow for separate monitoring of the first and second wafers. In particular, this may allow for easier analysis of the first and second wafers through different wafer acceptance tests (WAT). Separate monitoring may have particular advantages when the first and second wafers are manufactured using different processes. Electrical die sorting (EDS) may affect the workload of the wafer module.

[0105] See Figure 1A This is a vertical cross-sectional view of a semiconductor device 100 according to an embodiment of the present document. The semiconductor device 100 may include a wafer stack (e.g., a small wafer stack) containing multiple wafers (e.g., semiconductor wafers). Figure 1A As shown, the semiconductor device 100 may include a first layer 10, which includes a first packaging layer 118 and a first chip 110 within the first packaging layer 118. The semiconductor device 100 may also include a second layer 20, which includes a second packaging layer 128 and a second chip 120 within the second packaging layer 128. The second chip 120 may be electrically coupled to the first chip 110. The first chip 110 and the second chip 120 may together form an integrated circuit in the semiconductor device 100.

[0106] like Figure 1A As shown, the first chip 110 and the second chip 120 may be arranged in a front-to-back configuration in the semiconductor device 100. In particular, the front side 120f of the second chip 120 may be bonded to the rear side 110b of the first chip 110. The rear side 120b of the second chip 120 may face away from the first chip 110, and the front side 110f of the first chip 110 may face away from the second chip 120.

[0107] In some embodiments herein, the first wafer 110 and / or the second wafer 120 may include a second wafer test line portion 180-2. The second wafer test line portion 180-2 may provide the semiconductor device 100 for testing (e.g., allowing monitoring of the effects of the process on the semiconductor device 100).

[0108] like Figure 1AAs shown, the first wafer 110 may include a wafer substrate 108. The wafer substrate 108 may contain semiconductor materials such as silicon, germanium, silicon-germanium, etc. In some embodiments herein, the first wafer 110 may be constructed on a silicon wafer in a wafer-level process. The first wafer 110 may be formed by dicing a silicon wafer into multiple wafers, which include the first wafer 110. The first wafer 110 may therefore include portions of the silicon wafer such as the wafer substrate 108. Dividing the silicon wafer into multiple wafers may also form a first wafer edge 110a of the first wafer 110. The first wafer edge 110a may form around the entire periphery of the first wafer 110. One or more active devices may be formed inside and / or on the first wafer 110. The active devices may include one or more gate electrodes 109 formed on the wafer substrate 108. The gate electrodes 109 may be formed of a conductive material such as metal, polysilicon, etc.

[0109] The first wafer 110 may also include one or more interlayer dielectric (ILD) layers 112 on the wafer substrate 108. The gate electrode 109 may be located on the wafer substrate 108 within the interlayer dielectric layer 112. The interlayer dielectric layer 112 may include, for example, undoped silicon glass (USG), fluorosilicate glass (FSG), or silicon oxide (Si). x O y Materials such as hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), tetraethyl orthosilicate (TEOS), and hydrogen silsesquoxane (HSQ) can be used for the interlayer dielectric layer 112. The interlayer dielectric layer 112 may be formed using suitable deposition methods, such as chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or lamination.

[0110] One or more intermetallic dielectric layers 114 (IMDs) may be formed on top of intermetallic dielectric layer 112. The IMD may also contain materials such as undoped silicon glass (USG), fluorosilicate glass (FSG), hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), tetraethylsiloxane (TEOS), and silsesquioxane (HSQ). Other suitable dielectric materials may be used for the IMD. The IMD may be separated by one or more etch stop layers 114a. The etch stop layers 114a may contain materials such as silicon nitride (Si). x N y Materials such as silicon carbide, etc., may be used. Other suitable materials may be used for the etch stop layer 114a. The intermetallic dielectric layer 114 and the etch stop layer 114a may be formed by suitable deposition methods, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination.

[0111] The first wafer 110 may also include one or more metallic features 116 in the intermetallic dielectric layer 114. The metallic features 116 may be electrically connected to the gate electrode 109. The metallic features 116 may include, for example, metallic conductive pillars and metallic traces. The metallic conductive pillars may be formed between the metallic traces and internally connected to the metallic traces in different intermetallic dielectric layers 114. The metallic features 116 may be formed of suitable materials, such as copper, copper alloys, aluminum, aluminum alloys, or other combinations thereof. Other suitable metallic conductive materials for the metallic features 116 are also within the scope of this disclosure.

[0112] Please refer to Figure 1A and Figure 1BThe first wafer 110 may also include a first wafer sealing ring 117-1 extending through the inter-metal dielectric layer 114 and into the inter-metal dielectric layer 112. The first wafer sealing ring 117-1 may contact the wafer substrate 108. The first wafer sealing ring 117-1 may be electrically isolated from the metal feature 116 and formed to surround (e.g., around) the functional circuit portion 170 of the first wafer 110. The first wafer sealing ring 117-1 may provide protection to features of the first wafer 110 from water, compounds, residues, and / or contaminants during the first wafer 110 process. The first wafer sealing ring 117-1 may be formed in a conductive material (e.g., a metallic material), and more specifically, formed in the same material, at the same time, and through the same process as the metal feature 116. More specifically, the first wafer sealing ring 117-1 may include interconnected conductive lines and conductive pillar structures, and may be formed simultaneously with the metal lines and conductive pillars of the metal feature 116. For example, the first wafer sealing ring 117-1 may contain an atomic percentage of copper greater than 80%, such as greater than 90%, and / or greater than 95%, however, larger or smaller percentages may also be used.

[0113] In some embodiments, the metal feature 116 and / or the first wafer sealing ring 117-1 may be formed by a dual damascene process or a variety of single damascene processes. A single damascene process may typically form and fill a single feature with copper in a single damascene stage. A dual damascene process generally forms and fills two features with metal (e.g., copper) simultaneously in a single step. For example, in a dual damascene process, trenches and vias can be filled by a single metal deposition. In some embodiments, the metal feature 116 and / or the first wafer sealing ring 117-1 may be formed by an electroplating process.

[0114] In some embodiments, the metal feature 116 and / or the first wafer sealing ring 117-1 may be formed by a damascene process, wherein the intermetallic dielectric layer 114 is patterned in the damascene process (e.g., by photolithography) to form openings such as trenches and / or vias (e.g., conductive post vias). The metal layer (e.g., a copper layer) may then be deposited using a suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination. A planarization process, such as chemical-mechanical planarization (CMP), may then be performed to remove excess metal (e.g., overcoating).

[0115] Patterning, metal deposition, and planarization processes may be performed on each of the dielectric layers of the inter-metal dielectric layer 114 to form an interconnect structure made of the metal feature 116. For example, the dielectric layer of the inter-metal dielectric layer 114 may be deposited on the inter-layer dielectric layer 112 using a suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination. One or more openings may be subsequently formed in the dielectric layer. For example, the openings may be formed using a photolithography process. In the process, a photoresist mask (not shown) may be formed on the upper surface of the inter-layer dielectric layer 112. The photoresist mask may be photolithographically patterned to include one or more openings. Etching processes (such as wet etching and dry etching) may be subsequently used to form one or more openings through the photoresist mask in the dielectric layer. The photoresist mask may be subsequently removed by ashing, dissolving the photoresist mask, or consumed in the etching process.

[0116] Suitable deposition methods (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination, etc.) may be subsequently performed to fill the openings in the dielectric layer of the intermetallic dielectric layer 114. A planarization process may be subsequently performed to remove the overcoat and form the metal feature 116 in the dielectric layer. These process steps may be repeated to form the intermetallic dielectric layer 114, the corresponding metal feature, and the first wafer sealing ring 117-1, thereby completing the interconnect structure and the first wafer sealing ring 117-1.

[0117] Passivation layer 119 may be formed on the intermetallic dielectric layer 114. In some embodiments, passivation layer 119 may comprise silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), or a combination thereof. Other suitable dielectric materials are also within the scope of this disclosure. Passivation layer 119 may be formed by a suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination.

[0118] One or more contact pads 103 may be formed above the metal feature 116 and the first wafer sealing ring 117-1 through openings in the passivation layer 119. The contact pads 103 may contain metals such as aluminum and copper. The contact pads 103 may be formed by performing a lithography process (similar to the lithography process described above for forming the metal feature 116 on the first wafer 110) to form the openings, and depositing a metal layer in the openings using a suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination.

[0119] The gap-filling dielectric layer 104 may be formed subsequently on the passivation layer 119 and surround the contact pad 103. The gap-filling dielectric layer 104 may be formed of the same material as the intermetallic dielectric layer 114 (e.g., undoped silicon glass (USG), fluorosilicate glass (FSG), silicon oxide (Si). x O y Materials such as hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), tetraethylsiloxane (TEOS), and silsesquioxane (HSQ) can be used. The interstitial dielectric layer 104 can be formed by suitable deposition methods, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination.

[0120] The back-side etch stop layer 113 may be formed on top of the gap-filling dielectric layer 104. The back-side etch stop layer 113 may contain, for example, silicon nitride (Si). x N y Materials such as silicon carbide and others may be used for the back-side etch stop layer 113. The back-side etch stop layer 113 may be formed using suitable deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination.

[0121] A wafer bonding film 105 (e.g., a hybrid bonding film) may be formed on the back etch stop layer 113. The wafer bonding film 105 may contain an oxide, such as silicon oxide. The wafer bonding film 105 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). One or more wafer bonding pads 107 may be successively formed to penetrate multiple layers, including openings in the wafer bonding film 105, openings in the back etch stop layer 113, openings in the gap-filling dielectric layer 104, and openings in the passivation layer 119, as well as metal features 116 in the contact metal interlayer dielectric layer 114. The wafer bonding pads 107 may be formed of a material similar to the metal features 116. The wafer bonding pad 107 may be formed by performing a lithography process (similar to the lithography process for forming the metal feature 116 on the first wafer 110 described above) to form a multilayer opening including an opening in the wafer bonding film 105, an opening in the back etch stop layer 113, an opening in the gap-filling dielectric layer 104, and an opening in the passivation layer 119, and depositing a metal layer in the multilayer opening by a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination.

[0122] The first layer 10 of the semiconductor device 100 may include a third wafer 130 within the first packaging layer 118. The third wafer 130 may include a dummy wafer (e.g., a non-functional wafer). The third wafer 130 may have a thickness substantially the same as the first wafer 110 along the Z direction. The third wafer 130 may include, for example, a silicon wafer. Other suitable dielectric materials are also within the scope of this disclosure.

[0123] A first encapsulation layer 118 may be formed on the first wafer 110 and the third wafer 130 to encapsulate at least a portion of the first wafer 110 and at least a portion of the third wafer 130. The first encapsulation layer 118 may contain organic materials such as molding compound materials (e.g., formed by encapsulation) or inorganic materials (e.g., formed by physical vapor deposition (PVD)). The first encapsulation layer 118 may contain, for example, silicon oxide. The first encapsulation layer 118 may contain, for example, undoped silicon glass (USG), fluorosilicate glass (FSG), silicon carbide, silicon oxynitride, silicon nitride, silicon carbonitride, low dielectric constant film, very low dielectric constant (ELK) film, phosphor-silicate glass (PSG), and tetraethylsiloxane (TEOS). Other dielectric materials used in the first encapsulation layer 118 are also within the scope of this disclosure. The first encapsulation layer 118 may or may additionally contain one or more molding compounds such as epoxy molding compounds (EMC).

[0124] Same reference Figure 1A The first layer 10 of the semiconductor device 100 may include a first bonding film 141 (e.g., a fusion bonding film). The semiconductor device 100 may also include a first carrier substrate 102. The first carrier substrate 102 may be bonded to the first layer 10 (e.g., a first wafer 110, a third wafer 130, and a first packaging layer 118) via the first bonding film 141. The function of the first bonding film 141 may include bonding the first wafer 110 and the third wafer 130, and bonding the first wafer 110 and the third wafer 130 to the first carrier substrate 102. The first bonding film 141 may contain, for example, silicon oxynitride and silicon oxide. Other dielectric materials suitable for the first bonding film 141 are also within the scope of this disclosure.

[0125] The first layer 10 of the semiconductor device 100 may also include a first wafer bonding layer 143. The first wafer 110 may be bonded to the first bonding film 141 via the first wafer bonding layer 143. The first wafer bonding layer 143 may have a substantially the same width as the first wafer 110. The first wafer bonding layer 143 may have a substantially the same thickness as the first bonding film 141.

[0126] The first layer 10 of the semiconductor device 100 may also include a third wafer bonding layer 144. The third wafer 130 may be bonded to the first bonding film 141 via the third wafer bonding layer 144. The third wafer bonding layer 144 may have substantially the same width as the third wafer 130. The third wafer bonding layer 144 may have substantially the same thickness as the first bonding film 141.

[0127] Each of the first wafer bonding layer 143 and the third wafer bonding layer 144 may comprise, for example, silicon oxynitride and silicon oxide. Other dielectric materials suitable for the first wafer bonding layer 143 and the third wafer bonding layer 144 are also within the scope of this disclosure.

[0128] Alignment mark 145 may be located within the first bonding film 141. Alignment mark 145 may be located above a portion of the first encapsulation layer 118. Alignment mark 145 may have a width smaller than the width of a portion of the first encapsulation layer 118. Alignment mark 145 may have a thickness substantially the same as the first bonding film 141. In some embodiments, alignment mark 145 may comprise a die-to-wafer alignment mark. Alignment mark 145 may comprise a metal such as copper. Other suitable materials may be used in alignment mark 145.

[0129] The second wafer 120 may have a structure substantially similar to that of the first wafer 110. The second wafer 120 may also be formed by a method substantially similar to that used to form the first wafer 110. Similar to the first wafer 110, the second wafer 120 may be fabricated on a silicon wafer in a wafer-level process. The second wafer 120 may be formed in such a manner that it comprises multiple wafers diced from the silicon wafer. The second wafer 120 thus includes a portion of the silicon wafer as in the wafer substrate 108. Dividing the silicon wafer into wafers may also form the second wafer edge 120a of the second wafer 120. The second wafer edge 120a may be formed around the entire periphery of the second wafer 120.

[0130] The second wafer 120 may also include one or more active devices within and / or on the wafer substrate 108, including one or more gate electrodes 109. The second wafer 120 may also include one or more interlayer dielectric layers 112 on the wafer substrate 108, and one or more metal interlayer dielectric layers 114 on the interlayer dielectric layers 112. The metal interlayer dielectric layers 114 may be separated by one or more etch stop layers 114a.

[0131] The second wafer 120 may also include one or more metal features 116 and a second wafer sealing ring 117-2 in the intermetallic dielectric layer 114. The structure and function of the second wafer sealing ring 117-2 may be substantially similar to those of the first wafer sealing ring 117-1 in the first wafer 110. The second wafer sealing ring 117-2 may be electrically isolated from the metal feature 116 and formed to surround (e.g., around) the functional circuit portion 170 of the second wafer 120.

[0132] The second wafer 120 may additionally include one or more through-silicon vias (TSVs) 129 (e.g., second wafer conductive pillars) contacting one or more metal features 116. The TSV 129 may extend through at least a portion of the metal interlayer dielectric layer 114, the interlayer dielectric layer 112, and the wafer substrate 108. The surface of the TSV 129 may be substantially coplanar with the wafer substrate 108 in the second wafer 120. The TSV 129 may contain, for example, copper, gold, silver, aluminum, or other similar materials, or alloys of these metals such as aluminum-copper (AlCu) alloys. Other dielectric materials suitable for the TSV 129 are also within the scope of this disclosure.

[0133] The second wafer 120 may also include a passivation layer 119 over the intermetallic dielectric layer 114, and one or more contact pads 103 may be formed in the openings of the passivation layer 119 and surround the contact pads 103. The second wafer 120 may also include a back-side etch stop layer 113 over the gap-filling dielectric layer 104.

[0134] A second encapsulation layer 128 may be formed on the second wafer 120 to encapsulate at least a portion of the second wafer 120. The second encapsulation layer 128 may comprise organic materials such as molding compounds (e.g., formed by molding) or inorganic materials (e.g., formed by physical vapor deposition (PVD)). The second encapsulation layer 128 may comprise, for example, silicon oxide. The second encapsulation layer 128 may comprise, for example, undoped silicon glass (USG), fluorosilicate glass (FSG), silicon carbide, silicon oxynitride, silicon nitride, silicon carbonitride, low dielectric constant film, very low dielectric constant (ELK) film, phosphosilicate glass (PSG), and tetraethylsiloxane (TEOS). Other dielectric materials used in the second encapsulation layer 128 are also within the scope of this disclosure. The second encapsulation layer 128 may or may additionally comprise one or more molding compounds such as epoxy molding compounds (EMC).

[0135] The second layer 20 of the semiconductor device 100 may include a wafer bonding film 105 and one or more wafer bonding pads 107 within the wafer bonding film 105. The wafer bonding pads 107 may contact one or more contact pads 103 on the metal feature 116. A second wafer 120 and a second packaging layer 128 may be located on the wafer bonding film 105. The second layer 20 may also include a passivation layer 138. The wafer bonding film 105 may be located on the passivation layer 138. The passivation layer 138 may contain, for example, silicon nitride, undoped silicon glass (USG), or silicon dioxide. Other materials used for the passivation layer 138 are also within the scope of this disclosure. The second layer 20 may also include a second bonding film 142 (e.g., a hybrid bonding film). The passivation layer 138 may be located on the second bonding film 142. The function of the second bonding film 142 may include bonding elements of the second layer 20 (e.g., the second wafer 120) to the second carrier substrate 202. The second bonding film 142 may be formed using the same material and process as the first bonding film 141. The second bonding film 142 may contain, for example, silicon oxynitride or silicon dioxide. Other suitable dielectric materials used for the second bonding film 142 are also within the scope of this disclosure. One or more metal bumps 190 may be formed in the passivation layer 138 and the second bonding film 142 to contact the wafer bonding pad 107 (located in the wafer bonding film 105) of the metal feature 116 connected to the second wafer 120. The metal bumps 190 may be used to electrically couple the semiconductor device 100 to a separate substrate.

[0136] The second layer 20 of the semiconductor device 100 may also include a bonding layer 150. The bonding layer 150 may include a hybrid bonding film and serve as a hybrid bonding interface. The second layer 20 of the semiconductor device 100 may be bonded to the first layer 10 of the semiconductor device 100 via the bonding layer 150. The bonding layer 150 may extend the entire width of the semiconductor device 100 in the x-direction. The bonding layer 150 may also include, for example, silicon oxynitride and silicon oxide. Other suitable dielectric materials used for the bonding layer 150 are also within the scope of this disclosure. The bonding layer 150 may include bonding layer pads 157 connected to the silicon via 129 in the second wafer 120, and wafer bonding pads 107 connected to the first wafer 110. The bonding layer pads 157 may be formed of the same material as the wafer bonding pads 107. Other suitable materials are also within the scope of this disclosure. In some embodiments, the bonding between the first layer 10 and the second layer 20 may include a mixed bonding (e.g., an oxide bonding layer and a metal bonding layer) comprising a bonding layer 150 and a bonding layer bonding pad 157.

[0137] A redistribution layer structure (not shown in the figure) may be selectively formed in the bonding layer 150. The selective redistribution layer structure may be used to interconnect wafers in the first layer 10 (e.g., connecting the first wafer 110 to other wafers in the first layer 10). The selective redistribution layer structure may also be used to connect wafers in the first layer 10 (e.g., the first wafer 110) to wafers in the second layer 20 (e.g., the second wafer 120).

[0138] like Figure 1A As shown, the semiconductor device 100 may include a sidewall 100a extending along the entire height of the semiconductor device 100 from the second bonding film 142 to the first carrier substrate 102. The sidewall 100a may primarily include the sidewall 128a of the second encapsulation layer 128, the sidewall 118a of the first encapsulation layer 118, and the sidewall 102a of the first carrier substrate 102. The sidewall 100a may include the edge of the second bonding film 142, the edge of the passivation layer 138, the edge of the bonding layer 150, and the edge of the first bonding film 141.

[0139] The second wafer test line portion 180-2 may be integrally formed as a continuous unit and the remainder of the second wafer 120. The second wafer test line portion 180-2 may be relative to the functional circuit portion 170 adjacent to the second wafer 120. The second wafer test line portion 180-2 may be joined to the outer boundary (e.g., in the xy plane) via the functional circuit portion 170, and to the remaining three outer boundaries via the second wafer edge 120a. In some embodiments, the second wafer test line portion 180-2 may be located in a region of the second wafer 120, and its distance between the second wafer sealing ring 117-2 and the second wafer edge 120a may be greater than that of other portions of the second wafer 120.

[0140] Figure 1A The dashed lines in the diagram may be considered as a fictitious boundary between the functional circuit portion 170 and the second wafer test line portion 180-2. The second wafer 120 may not be separated by a boundary, but rather formed continuously across the boundary. The wafer substrate 108 is included in the functional circuit portion 170 and may extend into and be formed in the second wafer test line portion 180-2, and the interlayer dielectric layer 112 is included in the functional circuit portion 170 and may extend into and be formed in the second wafer test line portion 180-2, etc.

[0141] The second wafer test line portion 180-2 may include one or more test line portion metal features 116T, and the test line portion metal features 116T are substantially similar to the metal feature 116 in the functional circuit portion 170. The test line portion metal feature 116T may have substantially the same structure and composition as the metal feature 116 in the functional circuit portion 170. The test line portion metal feature 116T may be formed simultaneously with and in the same process step as the metal feature 116.

[0142] The second wafer test line portion 180-2 may have the same configuration as the functional circuit portion 170 of the second wafer 120. In some embodiments, the second wafer test line portion 180-2 may contain a metal pattern that is substantially the same as the functional circuit portion 170 of the second wafer 120.

[0143] The test line portion metal feature 116T may be electrically coupled to the metal feature 116 of the functional circuit portion 170. The second wafer test line portion 180-2 may be electrically coupled to the first wafer 110 through the functional circuit portion 170 of the second wafer 120. In particular, the second wafer test line portion 180-2 may be electrically coupled to the first wafer 110 through the through-silicon via 129 of the metal feature 110 and the functional circuit portion 170, and bonded to the bonding pad 157 in the bonding layer 150.

[0144] The second wafer test line portion 180-2 may include one or more test line portion sealing rings 117T, and the test line portion sealing rings 117T substantially have the same structure and composition as the second wafer sealing ring 117-2 in the functional circuit portion 170. The test line portion sealing ring 117T may have a structure substantially similar to that of the second wafer sealing ring 117-2. The second wafer sealing ring 117-2 may be formed simultaneously with and in the same process steps as the second wafer sealing ring 117-2.

[0145] The second wafer sealing ring 117-2 and / or the test lead sealing ring 117T may also be included as alignment marks or positioning elements during assembly and packaging to help accurately position the second wafer 120, thereby improving the overall quality and reliability of the semiconductor device 100. The second wafer sealing ring 117-2 and / or the test lead sealing ring 117T may also provide tangents as guide cutting tools for precise cutting of the second wafer 120 from other semiconductor devices formed on the first bulk substrate 102.

[0146] The second wafer test line portion 180-2 may include a test line electrical connection design that allows for tooling testing of the semiconductor device 100. In some embodiments, the second wafer test line portion 180-2 may be configured to allow testing of the semiconductor device 100 (e.g., testing of all functional wafers in the semiconductor device 100), such as via a wafer acceptance test (WAT) apparatus. In some embodiments, the second wafer test line portion 180-2 may be used to monitor process effects on the semiconductor device 100. In some embodiments, the second wafer test line portion 180-2 may be used to monitor charge buildup damage effects on the semiconductor device 100.

[0147] Figure 1B This is a top view (Z direction) of a semiconductor device 100 according to one or more embodiments of the present disclosure. Figure 1B The relative lateral positions (e.g. in the xy plane) of the first wafer 110, the second wafer 120, the third wafer 130, and the first carrier substrate 102 in the semiconductor device 100 are described. Figure 1B The relative lateral positions of the first wafer sealing ring 117-1, the second wafer sealing ring 117-2, and the test line portion sealing ring 117T in the semiconductor device 100 are also described. For ease of understanding, the first packaging layer 118 and the second packaging layer 128 are... Figure 1B Omitted in . Figure 1A for Figure 1B Vertical cross-section along line A-A'.

[0148] like Figure 1B As shown, the area of ​​the first wafer 110 may be smaller than the area of ​​the third wafer 130. The length of the first wafer 110 along the x-direction may be smaller than the length of the first carrier substrate 102 along the x-direction. The width of the second wafer 120 along the y-direction may be smaller than the width of the first carrier substrate 102 along the y-direction.

[0149] The area of ​​the second wafer 120 may be larger than the combined area of ​​the first wafer 110 and the third wafer 130. The combined length of the first wafer 110 and the third wafer 130 in the x-direction may be smaller than the length of the second wafer 120 in the x-direction. The maximum width of the first wafer 110 and the third wafer 130 in the y-direction may be smaller than the width of the second wafer 120 in the y-direction. In some embodiments, each of the first wafer 110 and the third wafer 130 may be laterally located within an area of ​​the second wafer 120 (e.g., within the edge 120a of the second wafer).

[0150] The area of ​​the first carrier substrate 102 may be larger than the area of ​​the second wafer 120. The length of the second wafer 120 along the x-direction may be less than the length of the first carrier substrate 102 along the x-direction. The width of the second wafer 120 in the y-direction may be less than the width of the first carrier substrate 102 in the y-direction. In some embodiments, the second wafer 120 may be laterally located within the area of ​​the first carrier substrate 102.

[0151] like Figure 1B As shown, the first wafer 110 may be located within the second wafer sealing ring 117-2. The third wafer 130 may include a first portion located above the functional circuit portion 170 of the second wafer 120, and a second portion located above the second wafer test line portion 180-2 of the second wafer 120. The second wafer test line portion 180-2 may include multiple test line portion sealing rings 117T and multiple test line portion metal features 116T. The multiple test line portion metal features 116T may be located within and / or outside the test line portion sealing rings 117T.

[0152] Figure 1C This is an exploded perspective view of a semiconductor device 100 according to some embodiments herein. For ease of interpretation, the first bonding film 141, bonding layer 150, passivation layer 138, second bonding film 142, and metal bump 190 are omitted. Figure 1C middle.

[0153] Figure 1C The dashed line along the z-direction is used to identify the center point of the semiconductor device 100. The center point of each of the first layer 10, the second layer 20, and the first carrier substrate 102 may be substantially aligned with the center point of the semiconductor device 100. In some embodiments, the sidewall 118a of the first encapsulation layer 118 may be substantially aligned with the sidewall 128a of the second encapsulation layer 128 and the sidewall 102a of the first carrier substrate 102 surrounding the entire periphery of the semiconductor device 100.

[0154] In the first layer 10 of the semiconductor device 100, a first packaging layer 118 may surround the entire periphery of the first wafer 110 and the entire periphery of the third wafer 130. The first layer 10 may include a substantially uniform upper surface. The upper surface of the first wafer 110 may be formed by the upper surface of the wafer substrate 108 in the first wafer 110. In some embodiments, the first packaging layer 118 may be substantially coplanar with the upper surface of the wafer substrate 108 in the first wafer 110 and the upper surface of the third wafer 130.

[0155] In the second layer 20 of the semiconductor device 100, the second packaging layer 128 may surround the entire periphery of the second wafer 120. The second layer 20 may include a substantially uniform upper surface. The upper surface of the second wafer 120 may be composed of the upper surface of the wafer substrate 108 in the second wafer 120. In some embodiments, the second packaging layer 128 may be substantially coplanar with the upper surface of the wafer substrate 108 in the second wafer 120.

[0156] Generally, a semiconductor device 100 may be formed by forming a first layer 10 on a first carrier substrate 102 and forming a second layer 20 on the first layer 10. In some embodiments, the semiconductor device 100 may be formed in a process in which multiple semiconductor devices are simultaneously formed on the carrier substrate. In this process, the first layer 10 may be formed by mounting multiple first wafers 110 and multiple third wafers 130 on the carrier substrate and encapsulating the first wafers 110 and third wafers 130 in a first packaging layer 118. The second layer 20 may then be formed by mounting multiple second wafers 120 on the first layer 10 and encapsulating the first layer 10 in a second packaging layer 128. A dicing process may then be performed to dic the multiple semiconductor devices 100.

[0157] Figures 2A to 2H To illustrate different intermediate structures in the method of forming semiconductor device 100 according to some embodiments. Figure 2A According to some embodiments, the intermediate structure includes a first bonding film 141 on the first carrier substrate 102.

[0158] In some embodiments, the first bonding film 141 may be formed by depositing a bonding material using a suitable deposition method, such as chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or lamination. The bonding material may then be planarized (e.g., by wet etching and dry etching) to form the first bonding film 141.

[0159] Alignment marks 145 may be subsequently formed in the first bonding film 141. Openings for the alignment marks 145 may be formed in the first bonding film 141 by a photolithography process. The photolithography process may be similar to the photolithography process described above for forming the metal features 116 in the first wafer 110. In the photolithography process, a photoresist mask (not shown) may be formed on the surface of the first bonding film 141. The photoresist mask may have an opening after photolithography patterning. An etching process (e.g., wet etching and dry etching) may subsequently form an opening in the first bonding film 141 through the opening in the photoresist mask. The opening in the first bonding film 141 may be formed on the surface exposing the first carrier substrate 102. The photoresist mask may subsequently be removed by ashing, dissolving the photoresist mask, or consumed during the etching process.

[0160] A layer of metallic material (e.g., copper) may be subsequently deposited (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes) over the first bonding film 141 and into openings in the first bonding film 141. Excess metallic material may be subsequently removed (e.g., by chemical mechanical planarization (CMP) or other suitable planarization processes) to form alignment marks 145 that are substantially coplanar with the surface of the first bonding film 141.

[0161] Figure 2B This disclosure describes an intermediate structure comprising a first wafer 110 and a third wafer 130 disposed on a first bonding film 141, according to one or more embodiments. In some embodiments, the first wafer 110 may be disposed on the first bonding film 141 by an electromechanical pick-and-place (PNP) machine. The third wafer 130 may be disposed on the first bonding film 141, respectively, as with the first wafer 110 (e.g., in separate steps). The third wafer 130 may be disposed on the first bonding film 141 adjacent to the first wafer 110 by a PNP machine. The third wafer 130 may be disposed opposite to the first bonding film 141, and the first wafer 110 may be disposed on the first bonding film 141 and adjacent to the third wafer 130. The third wafer 130 may be disposed opposite to the first wafer 110 simultaneously on the first bonding film 141 in a single step. In some embodiments, a first alignment mark 145 may be used to assist in proper alignment (e.g., placement and configuration) of the first wafer 110 and / or the third wafer 130.

[0162] like Figure 2BAs shown, the first wafer 110 and the third wafer 130 may be disposed on the first bonding film 141 to provide sufficient separation between the first wafer 110 and the third wafer 130. This separation may allow a sufficient number of first packaging layers 118 to be formed in the gap between the first wafer 110 and the third wafer 130 (see reference). Figure 1C This separation may allow the first encapsulation layer 118 to fill the gap (e.g., completely fill the gap) without leaving any residual air bubbles in the gap. The first wafer 110 and the third wafer 130 may also be disposed on the first bonding film 141 such that the sum of the lengths of the first wafer 110 and the third wafer 130 in the x-direction is less than the length of the second wafer 120 in the x-direction (see reference). Figure 1A ).

[0163] Figure 2C This disclosure describes an intermediate structure including a first encapsulation layer 118 according to one or more embodiments. The first encapsulation layer 118 may be formed on a first bonding film 141 to encapsulate (e.g., at least partially encapsulate) a first wafer 110 and a third wafer 130. The first encapsulation layer 118 (e.g., encapsulation material) may be deposited on the first bonding film 141. The first encapsulation layer 118 may be deposited by a suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination, etc.

[0164] In some embodiments, the first packaging layer 118 may be formed to have a height in the z-direction greater than the height of the first wafer 110 and greater than the height of the third wafer 130. After the formation of the first packaging layer 118, a planarization process (e.g., chemical mechanical planarization (CMP)) may be subsequently performed to planarize the upper surfaces of the first packaging layer 118, the first wafer 110, and the third wafer 130. The upper surfaces of the first packaging layer 118, the first wafer 110, and the third wafer 130 may be made coplanar during the planarization process. The planarization process may also complete the formation of the first layer 10 (excluding a dicing step to separate the semiconductor device 100).

[0165] Figure 2D For the purposes of this disclosure, an intermediate structure of a second layer 20 included on a second carrier substrate 202 is described according to one or more embodiments. The second carrier substrate 202 may be substantially similar to the first carrier substrate 102. The second layer 20 may be formed on the second carrier substrate 202 in a manner substantially similar to the formation of the first layer 10 on the first carrier substrate 102 (e.g., see reference). Figures 2A to 2C ).

[0166] An adhesive layer (not shown in the figures) may be applied to the upper surface of the second carrier substrate 202. The second carrier substrate 202 may comprise an optically transparent material such as glass or gallium nitride (sapphire). The adhesive layer may comprise, for example, a light-to-heat conversion (LTHC) layer or a thermally degradable adhesive material. Other suitable thermally degradable adhesive materials are also within the scope of this disclosure.

[0167] The second bonding film 142 may be formed on the adhesive layer above the upper surface of the second carrier substrate 202. The second bonding film 142 may be formed using the same method as the first bonding film 141. In some embodiments, the second bonding film 142 may be formed by depositing a bonding material using a suitable deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination. The bonding material may then be planarized (e.g., by wet etching and dry etching) to form the second bonding film 142.

[0168] Passivation layer 138 may be formed subsequently on the second bonding film 142. Passivation layer 138 may be formed on the second layer 20. Passivation layer 138 may be formed by deposition (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition methods) of one or more layers of passivation material comprising silicon oxide, silicon nitride, low dielectric constant material such as carbon-doped oxide, very low dielectric constant material such as porous carbon-doped silicon dioxide, and combinations thereof or other suitable materials. Passivation layer 138 may be subsequently planarized (e.g., by wet etching and dry etching) to form passivation layer 138.

[0169] The wafer bonding film 105 may be formed subsequently on the passivation layer 138. In some embodiments, the wafer bonding film 105 may be formed by depositing a bonding material, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination. The bonding material may be subsequently planarized (e.g., by wet etching and dry etching) to form the wafer bonding film 105.

[0170] The second wafer 120 may subsequently be disposed on the wafer bonding film 105 using a wafer pick-and-place (PNP) machine. The second wafer 120 may be inverted so that the back side of the second wafer 120 contacts the wafer bonding film 105. In particular, the back side etch stop layer 113 may be aligned with the wafer bonding film 105 so that the contact pads 103 exposed in the second wafer 120 contact the wafer bonding pads 107 in the wafer bonding film 105.

[0171] The second encapsulation layer 128 may be formed on the second wafer 120 using a method similar to that used to form the first encapsulation layer 118. Specifically, the second encapsulation layer 128 may be formed on the second wafer 120 and surrounding the second wafer 120 on the passivation layer 138, for encapsulating (e.g., at least partially encapsulating) the second wafer 120. The second encapsulation layer 128 (e.g., encapsulation material) may be deposited on the second wafer 120 and on the passivation layer 138. The second encapsulation layer 128 may be deposited using suitable deposition methods, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination.

[0172] In some embodiments, the second packaging layer 128 may be formed with a height in the z-direction greater than the height of the second wafer 120. After the second packaging layer 128 is sufficiently formed, a planarization process (e.g., chemical mechanical planarization (CMP)) may be subsequently performed to planarize the surfaces of the second packaging layer 128 and the second wafer 120. The surfaces of the second packaging layer 128 and the second wafer 120 may be coplanar through the planarization process.

[0173] The bonding layer 150 may be formed successively on the surface of the second encapsulation layer 128 and the surface of the second wafer 120. The bonding layer 150 may be formed using methods similar to those used to form the first bonding film 141 and the second bonding film 142. In some embodiments, the bonding layer 150 may be formed on the surface of the second encapsulation layer 128 and the surface of the second wafer 120. In some embodiments, the bonding layer 150 may be formed using suitable deposition methods, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination. In some embodiments, the bonding material may be deposited by chemical vapor deposition (CVD), and one of the raw materials for the bonding material may comprise a gas or liquid (e.g., tetraethylsiloxane (TEOS)).

[0174] Bonding pads 157 may be subsequently formed in bonding layer 150. Openings may be formed in bonding layer 150 using a photolithography process. This photolithography process may be similar to the aforementioned photolithography process used to form the metal feature 116 in the first wafer 110. In the photolithography process, a photoresist mask (not shown) may be formed on the surface of bonding layer 150. The photoresist mask may be photolithographically patterned to include openings above the through-silicon via 129. Etching processes (e.g., wet etching and dry etching) may be subsequently used to form openings in bonding layer 150 via the openings in the photoresist. Openings in bonding layer 150 may be formed to expose the surface of the through-silicon via 129. The photoresist mask may be subsequently removed by ashing, dissolving the photoresist mask, or consumed during the etching process.

[0175] A metal layer may be formed subsequently on the bonding layer 150, in the openings of the bonding layer 150, and above the surface of the silicon via 129. The metal layer may be formed using a suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), spin coating, or lamination. The metal layer may be followed by a planarization process (e.g., chemical mechanical planarization (CMP)) to make the surface of the bonding pad 157 substantially coplanar with the surface of the bonding layer 150. The formation of the bonding pad 157 completes the configuration of the second layer 20.

[0176] Figure 2E This disclosure describes an intermediate structure of the second layer 20 according to one or more embodiments. In some embodiments, the second layer 20 may be bonded to the first layer 10 in a wafer-to-wafer bonding process.

[0177] The second layer 20 may be configured above the first layer 10, for example, via a chip pick-and-place (PNP) machine. Specifically, Figure 2D The intermediate structure may be inverted and located above the first layer 10, so that the second layer 20 is located between the first layer 10 and the second carrier substrate 202. The second layer 20 may then be lowered above the first layer 10 so that the bonding layer 150 in the second layer 20 contacts the first packaging layer 118, the wafer bonding film 105 formed on the back side of the first wafer 110, and the third wafer 130. The second layer 20 may also be located above the first layer 10 so that the bonding layer bonding pad 157 in the bonding layer 150 contacts the wafer bonding pad 107 in the first wafer 110.

[0178] The second layer 20 may also be located above the first layer 10, so that the second chip 120 is situated above the first chip 110 and the third chip 130. In some embodiments, the second chip 120 may be configured such that the second chip 120 is situated entirely above the first chip 110 and entirely above the third chip 130 (see reference). Figure 1B The second layer 20 may also be configured such that the first wafer sealing ring 117-1 in the first wafer 110 is located within 117-2 in the second wafer 120 (see reference). Figure 1B ).

[0179] The bonding process may be performed sequentially through bonding layer 150 to bond the second layer 20 to the first layer 10. The bonding process may form, for example, a hybrid bond, in which bonding layer bonding pads 157 in bonding layer 150 are bonded to wafer bonding pads 107 in the first wafer 110, and bonding layer 150 is bonded to wafer bonding film 105 in the first wafer 110. Bonding layer 150 may also be bonded to the first encapsulation layer 118 of the first layer 10. The bonding process may be performed at room temperature (room temperature bonding) or at elevated temperatures (thermal bonding), depending on the specific bonding technique used.

[0180] Figure 2F This disclosure describes, according to one or more embodiments, an intermediate structure after the removal of the second carrier substrate 202. The second carrier substrate 202 may detach from the second bonding film 142, for example, by rendering the adhesive layer (not shown) adhering the second carrier substrate 202 to the second bonding film 142 ineffective. The adhesive layer may detach, for example, by thermal annealing at elevated temperatures or by exposing the adhesive layer to ultraviolet light.

[0181] Figure 2G This disclosure describes, according to one or more embodiments, an intermediate structure comprising multiple openings O120 in a passivation layer 138 and a second bonding film 142. The multiple openings O120 may be formed in the passivation layer 138 and the second bonding film 142 by a photolithography process. The photolithography process may be similar to the photolithography process described above for forming the metal feature 116 in the first wafer 110. In the photolithography process, a photoresist mask (not shown) may be formed on the upper surface of the second bonding film 142. The photoresist mask may be photolithographically patterned to include openings above the wafer bonding pad 107. Etching processes (e.g., wet etching and dry etching) may be subsequently used to form multiple openings O120 in the second bonding film 142 and the passivation layer 138 through the openings in the photoresist. The multiple openings O120 in the second bonding film 142 and the passivation layer 138 may be formed to expose the upper surface of the wafer bonding pad 107. The photoresist mask may be subsequently removed by ashing, dissolving the photoresist mask, or consumed in the etching process.

[0182] It is worth noting that (e.g., prior to the bump loop process), tests such as wafer acceptance testing (WAT) may be performed on semiconductor device 100. In this case, test openings similar to multilayer openings O120 may be formed. Figure 2G Within the intermediate structure. Test openings may be formed in the second bonding film 142, passivation layer 138, and wafer bonding film 105 to expose the surface of contact pad 103, wherein contact pad 103 is electrically coupled (e.g., in contact) to the test line portion metal feature 116T in the second wafer test line portion 180-2 of the second wafer 120. Test probes of one or more wafer acceptance test (WAT) tools may be subsequently inserted into the test openings to contact contact pad 103 and perform semiconductor device testing. It is worth noting that the timing of wafer acceptance test (WAT) is not limited but may be performed at other stages of the manufacturing process. More testing details are provided below via wafer acceptance test (WAT) (e.g., refer to...). Figure 4 ).

[0183] Figure 2H To illustrate an intermediate structure of a metal bump 190 included in a multilayer opening O120 on a wafer bonding pad 107, according to one or more embodiments. The metal bump 190 may include, for example, a bump C4 containing solder balls formed on the wafer bonding pad 107. The metal bump 190 may be formed, for example, by one or more processes including ball mounting, electroplating, solder printing, solder immersion, and solder injection. The metal bump 190 may contact the wafer bonding pad 107 and the sidewalls of the multilayer opening O120 in the passivation layer 138 and the second bonding film 142. In some embodiments, one or more under-bump metallization (UBM) layers (not shown) may be formed on the wafer bonding pad 107. The metal bump 190 may be subsequently formed such that it contacts the wafer bonding pad 107 through the under-bump metallization (UBM) layer.

[0184] After the metal bumps 190 are formed, a dicing process can be performed to separate the semiconductor device 100 from other semiconductor devices (e.g., the carrier substrate) formed on the first carrier substrate 102. The dicing process may result in the formation of sidewalls 100a of the semiconductor device 100, including sidewalls 128a of the second encapsulation layer 128, sidewalls 118a of the first encapsulation layer 118, and sidewalls 102a of the first carrier substrate 102.

[0185] Figure 3This is a flowchart illustrating a method for forming a semiconductor device according to one or more embodiments. (Refer to...) Figure 1A , Figure 2H , Figure 5A , Figure 7 and Figure 8 Step 310 includes forming a first layer 10 including a first wafer 110, wherein the first wafer 110 includes a first wafer edge 110a and a first wafer sealing ring 117-1. Step 320 includes forming a second layer 20 including a second wafer 120, wherein the second wafer 120 includes a second wafer edge 120a and a second wafer sealing ring 117-2, wherein at least one of the first wafers 110 includes a first wafer test line portion 180-1 between the first wafer edge 110a and the first wafer sealing ring 117-1, or the second wafer 120 includes a second wafer test line portion 180-2 between the second wafer edge 120a and the second wafer sealing ring 117-2. Step 330 includes attaching the first layer 10 to the second layer 20 such that the back side 120b of the second wafer 120 is opposite to the first wafer 110.

[0186] Figure 4 To illustrate a testing method for a semiconductor device 100 according to one or more embodiments. In some embodiments, the testing of the semiconductor device 100 may utilize a second wafer test line portion 180-2 in a second wafer 120. In some embodiments, the testing of the semiconductor device 100 may include wafer acceptance testing (WAT). In some embodiments, a wafer acceptance testing tool 400 may be used to perform the testing of the semiconductor device 100.

[0187] Wafer Acceptance Testing (WAT) plays a crucial role in semiconductor device manufacturing by helping to confirm the quality and reliability of semiconductor wafers before proceeding with subsequent manufacturing processes. This may be performed, for example, near the end of a semiconductor device manufacturing process (e.g., wafer fabrication) or after the semiconductor device manufacturing process is completed.

[0188] The objective of wafer acceptance testing (WAT) may include identifying any deficiencies, errors, or deviations in the electronic or physical characteristics of semiconductor device 100. Testing may include evaluating the functionality, performance, and overall quality of semiconductor device 100. Testing may be performed using wafer acceptance testing equipment 400 and may involve testing structures designed to measure different parameters and performance of integrated circuits (ICs) in one or more of the first wafer 110 and second wafer 120 of semiconductor device 100.

[0189] The wafer acceptance test tool 400 may perform electronic tests, such as those on the semiconductor device 100. This may include probing the integrated circuits (ICs) in the semiconductor device 100 to measure their electronic characteristics. Various tests may be performed by the wafer acceptance test tool 400, such as measuring current-voltage (IV) curves, identifying short circuits and connections, checking power supply voltages, and analyzing the functionality of different circuit components.

[0190] The wafer acceptance test tool 400 may also perform parametric tests to measure key electronic parameters of integrated circuits (ICs), such as voltage level, current, time, and capacitance. These parameters may help confirm that the integrated circuits (ICs) meet specific performance requirements.

[0191] The wafer acceptance test tool 400 may also perform functional tests to evaluate the overall functionality of integrated circuits (ICs) by inputting specific stimuli and verifying expected output responses. This may help confirm the correctness of the integrated circuits (ICs) in performing their intended functions.

[0192] The wafer acceptance test tool 400 may also perform reliability tests to assess the durability and stability of integrated circuits (ICs) under different operating conditions over a long period. These tests include temperature cycling tests, burn-in tests, electrostatic discharge tests, and other stress tests to simulate real-world usage scenarios and verify potential failure mechanisms.

[0193] The wafer acceptance test tool 400 may also perform defect detection to inspect for physical defects in the semiconductor device 100, using techniques such as optical microscopy, scanning electron microscopy (SEM), and other non-destructive testing methods. Defects such as contamination, particles, scratches, or irregular patterns may be inspected and classified by the wafer acceptance test tool 400.

[0194] The wafer acceptance test tool 400 may also use data obtained through statistical analysis of the test semiconductor device 100 to assess the overall quality of a batch of semiconductor devices 100. Data from a batch of semiconductor devices 100 may be collected and analyzed to evaluate process variation, yield, and verify any systemic issues that need to be addressed. A batch of semiconductor devices 100 may be accepted or rejected based on the test results obtained through the wafer acceptance test tool 400.

[0195] Please refer to the same. Figure 4In some embodiments, the wafer acceptance test tool 400 may be implemented via a computer, server, etc. The wafer acceptance test tool 400 may include processing devices 410, such as a central processing unit (CPU) and a microprocessor. The wafer acceptance test tool 400 may also include memory devices 420 (e.g., random access memory (RAM) and read-only memory (ROM)). The memory device 420 may store data and programs, including instructions for performing various operations, within the wafer acceptance test tool 400. The memory device 420 may also store data generated during testing performed by the wafer acceptance test tool 400. The processing device 410 may access data and programs in the memory device 420 and execute operating instructions to perform various methods, including testing (e.g., wafer acceptance testing), of semiconductor devices. The processing device 410 may also store test data generated during testing performed by the wafer acceptance test tool 400 in the memory device 420. The processing device 410 may also perform analysis of test data via the wafer acceptance test tool 400, and store the generated test analysis data in the memory device 420. The wafer acceptance test tool 400 may also include a display 430 (e.g., a display device), and the processing device 410 may generate display signals on the display 430, including test data and test analysis data.

[0196] The wafer acceptance test tool may also include input / output (I / O) devices 440 (e.g., signal transmitters / receivers) to transmit test signals generated by the processing device 410 or according to operating instructions generated by the processing device 410. The input / output devices 440 may also receive signals from the semiconductor device 100 in response to the test signals.

[0197] The wafer receiving test tool 400 may include one or more test probes 402 connected to the input / output device 440 via a signal transmission cable 401. Other forms of transmitted signals, such as wireless signals, may be used. Methods for testing the semiconductor device 100 may include forming one or more test openings O. T The second chip test line section 180-2 of the functional circuit section 170 and the second chip 120. Test opening O. T It may be formed, for example, by performing a lithography process (similar to the lithography process used to form the metal feature 116 in the first wafer 110). Test opening O T It may include multiple openings formed in the back-side etch stop layer 113 and the gap-filling dielectric layer 104. Test opening O TA surface may be formed to expose the contact pad 103, wherein the contact pad 103 is electrically coupled (e.g., in contact) to a metallic feature 116 in a functional circuit portion 170 of the second wafer 120. Test opening O T It may also be formed to expose the surface of the contact pad 103, wherein the contact pad 103 is electrically coupled (e.g., in contact) to the test line portion metal feature 116T in the second wafer test line portion 180-2 of the second wafer 120.

[0198] Test probe 402 may be inserted into test opening O. T The test probe 402 may contact one or more contact pads 103 exposed in the two-wafer test line section 180-2. The wafer receiving test tool 400 may electrically couple to the contact pads 103 via a signal transmitting cable 401. The wafer receiving test tool 400 may subsequently transmit test signals to expose the contact pads 103 via the signal transmitting cable 401 and the test probe 402. The test signals may be emitted from the contact pads 103 via integrated circuits included in the first wafer 110 and the second wafer 120. Other test probes 402 contacting other exposed contact pads 103 may detect responses to the test signals and transmit responses back to the wafer receiving test tool 400 via other signal transmitting cables 401.

[0199] Figure 5A A vertical cross-sectional view of a semiconductor device 100 having a first alternative design is illustrated according to one or more embodiments. Figure 5A As shown, the first alternative design of the semiconductor device 100 may be substantially the same as... Figure 1A The original design is similar. However, in the first alternative design, the semiconductor device 100 includes a first wafer test line portion 180-1 within the first wafer 110. The first wafer test line portion 180-1 may be adjacent to the functional circuit portion 170 within the first wafer 110. The first wafer test line portion 180-1 may be substantially related to... Figure 1A The second wafer test line section 180-2 in the original design is similar.

[0200] To accommodate the first wafer test line portion 180-1, the length of the first wafer 110 in the x-direction may be greater than [missing information]. Figure 1A The length of the first wafer 110 in the x-direction of the original design. The length of the third wafer 130 in the x-direction may be greater than... Figure 1A The length of the third wafer 130 in the x-direction of the original design.

[0201] The first wafer test line portion 180-1 may be obtained through the second wafer 120 during wafer receiving testing. To allow access to the first wafer test line portion 180-1, it may include a test line portion contact pad 107T in the wafer bonding film 105 of the first wafer 110. The test line portion contact pad 107T may be substantially similar to the wafer bonding pad 107 in the wafer bonding film 105 of the first wafer 110. The semiconductor device 100 may include a bonding layer bonding pad 657 in the bonding layer 150. The bonding layer bonding pad 657 may contact the test line portion contact pad 107T. The bonding layer bonding pad 657 may be substantially similar to the bonding layer bonding pad 157 in the bonding layer 150. The second wafer 120 may also include a through-silicon via 629 electrically coupled to the bonding layer bonding pad 657 in the bonding layer 150 and the metal feature 116 in the second wafer 120. The through-silicon via 629 may be substantially similar to the through-silicon via 129 in the second wafer 120. The first wafer test line portion 180-1 may be electrically coupled to the second wafer 120 (e.g., a functional circuit region of the second wafer 120).

[0202] The first wafer test line portion 180-1 in the first wafer 110 may therefore be used as a test line. In particular, the first wafer test line portion 180-1 may be used to monitor the impact on the process of the semiconductor device 100, wherein the semiconductor device 100 has a first design and integrated circuits in the semiconductor device.

[0203] In a first alternative design, the semiconductor device 100 may include connection structures including a test line portion bonding pad 607, a bonding layer bonding pad 657 in the bonding layer 150, and a through-silicon via 629 in the second wafer 120. However, it should be noted that the semiconductor device 100 may include multiple connection structures between the first wafer test line portion 180-1 and the second wafer 120. That is, the semiconductor device 100 may include multiple test line portion bonding pads 607, bonding layer bonding pads 657, and through-silicon vias 629.

[0204] Figure 5B This is a schematic diagram illustrating a test method for a semiconductor device 100 having a first alternative design, according to one or more embodiments. The test method for the semiconductor device 100 having the first alternative design may be substantially similar to... Figure 1A (see Figure 4 The testing methods for the semiconductor device 100 with the original design are similar. In some embodiments, the testing methods for the semiconductor device 100 may use a first wafer test line portion 180-1 in the first wafer 110. In some embodiments, a wafer acceptance test tool 400 may be used to perform tests on the semiconductor device 100.

[0205] like Figure 5B As shown, test probe 402 may be inserted into test opening O. T In the process, a contact pad 103 is electrically coupled to a silicon through-hole 629. A test probe 402 may electrically couple a wafer receiving test tool 400 to the contact pad 103 via a cable 401. The wafer receiving test tool 400 may subsequently transmit test signals to the exposed contact pad 103 via the cable 401 and the test probe 402. The test signals may be transmitted from the contact pad 103 through an integrated circuit including a first wafer 110 and a second wafer 120. The test probe 402 may detect test signal responses and transmit the responses back to the wafer receiving test tool 400 via the cable 401.

[0206] Figure 6 This is a schematic diagram illustrating a testing method for a semiconductor device 100 according to one or more embodiments. Step 610 includes exposing a contact pad, wherein the contact pad is electrically coupled to a test line portion in a wafer of the semiconductor device. Step 620 includes contacting a probe of a wafer acceptance test tool to the exposed contact pad. Step 630 includes transmitting a test signal from the wafer acceptance test tool to the probe. Step 640 includes transmitting a response of the test signal from the probe to the wafer acceptance test tool.

[0207] Figure 7 A vertical cross-sectional schematic diagram of a semiconductor device 100 having a second alternative design is provided to illustrate one or more embodiments. Figure 7 As shown, the second alternative design of the semiconductor device 100 may be substantially the same as... Figure 5A The first alternative design is similar. In particular, the first chip 110 may include a first chip test line section 180-1.

[0208] However, in the second alternative design, the semiconductor device 100 may not include the connection structure between the first wafer test line portion 180-1 and the second wafer 120. That is, the semiconductor device 100 may not be included in... Figure 5A The first alternative design includes test line bonding pad 607, bonding layer bonding pad 657, and silicon via 629.

[0209] That is, the first wafer test line portion 180-1 may not be electrically coupled to the second wafer 120. In this case, the first wafer test line portion 180-1 may not be used for testing, but may be used as, for example, a heat dissipation structure. The first wafer test line portion 180-1 may also be used to reduce the area of ​​the third wafer 130. In some embodiments, the first wafer test line portion 180-1 may completely eliminate the need for the third wafer 130. This may help reduce costs and balance pressures (e.g., pressures caused by mismatched coefficients of thermal expansion (CTEs)) at the horizontal position of the first wafer (e.g., at the same horizontal position, with the same structure).

[0210] Figure 8 A vertical cross-sectional schematic diagram of a semiconductor device 100 having a third alternative design is provided according to one or more embodiments. Figure 8 As shown, a third alternative design for the semiconductor device 100 may include a first wafer test line portion 180-1 in the first wafer 110 and a second wafer test line portion 180-2 in the second wafer 120. Furthermore, in Figure 5A The first alternative design includes a connection structure between the first wafer test line portion 180-1 and the second wafer 120. Specifically, the semiconductor device 100 may include a test line portion bonding pad 607, a bonding layer bonding pad 657, and a through-silicon via 629. Therefore, the first wafer test line portion 180-1 may be electrically coupled to the second wafer 120 via the connection structure.

[0211] Figure 8 A third alternative design could allow for separate monitoring of the first wafer 110 and the second wafer 120. In particular, this design could allow for simplified analysis of the first wafer 110 and the second wafer 120 through separate testing using wafer acceptance testing tools (see [reference]). Figure 4 and Figure 5B Separate monitoring may be particularly beneficial for the formation of the first wafer 110 and the second wafer 120 in different processes. Separate monitoring may improve the electronic wafer sorting (EDS) process and may affect the workload of the semiconductor device 100.

[0212] See Figures 1A to 8The semiconductor device 100 may include a first wafer 110, including a first wafer edge 110a and a first wafer sealing ring 117-1; a second wafer 120 bonded to the first wafer 110 and including a second wafer edge 120a and a second wafer sealing ring 117-2; and a test line portion including at least one of the following: a first wafer test line portion 180-1 located in the first wafer 110 between the first wafer edge 110a and the first wafer sealing ring 117-1; or a second wafer test line portion 180-2 located in the second wafer 120 between the second wafer edge 120a and the second wafer sealing ring 117-2. The test line portion may include the second wafer test line portion 180-2, and the second wafer test line portion 180-2 may include a test line portion metal feature 116T disposed electrically coupled to a test tool. The second wafer test line portion 180-2 may also include a test line portion sealing ring 117T surrounding the test line portion metal feature 116T. The second wafer test line portion 180-2 may be located in a first direction between the second wafer edge 120a and the second wafer sealing ring 117-2, and the distance between the second wafer edge 120a and the second wafer sealing ring 117-2 in the first direction may be greater than the distance between the second wafer edge 120a and the second wafer sealing ring 117-2 in a second direction perpendicular to the first direction. The first wafer sealing ring 117-1 has a first wafer sealing ring length and a first wafer sealing ring width in the first direction, which may be smaller than the first wafer sealing ring length in the second direction. The second wafer sealing ring 117-2 may have a second wafer sealing ring length and a second wafer sealing ring width in the first direction, which are smaller than the second wafer sealing ring length in the second direction, and the second wafer sealing ring length may be greater than the first wafer sealing ring length. The second wafer 120 may also include a wafer substrate 108 and conductive pillars 129 in the wafer substrate 108, and are configured to electrically couple the second wafer 120 to the first wafer 110. Semiconductor device 100 may further include a bonding layer 150 between a first wafer 110 and a second wafer 120, and a bonding layer bonding pad 157 in the bonding layer 150 and bonded to a conductive post 129. The first wafer 110 may include a wafer bonding film 105 and a wafer bonding pad 107 in the wafer bonding film 105, wherein the wafer bonding pad 107 may be bonded to the bonding layer bonding pad 157. Semiconductor device 100 may further include a dummy wafer 130 adjacent to the first wafer 110 and bonded to the second wafer 120 via the bonding layer 150, and a first encapsulation layer 118 encapsulating the dummy wafer 130 and the first wafer 110. Semiconductor device 100 may further include a second encapsulation layer 128 encapsulating the second wafer 120, wherein the second encapsulation layer 128 may be bonded to the first encapsulation layer 118 via the bonding layer 150.The test line portion may include a first wafer test line portion 180-1, and the first wafer test line portion 180-1 may include a test line portion metal feature 116T configured to be electrically coupled to a test tool via a second wafer 120. The second wafer 120 may also include a wafer substrate 108, and conductive pillars 129 in the wafer substrate 108 and configured to electrically couple the second wafer 120 to the first wafer test line portion 180-1. The first wafer test line portion 180-1 may be electrically isolated from the second wafer 120. The test line portion may include a first wafer test line portion 180-1 and a second wafer test line portion 180-2.

[0213] Same reference Figures 1A to 8 A method of manufacturing a semiconductor device 100 may include forming a first layer 10 including a first wafer 110 including a first wafer edge 110a and a first wafer sealing ring 117-1, forming a second layer 20 including a second wafer 120 including a second wafer edge 120a and a second wafer sealing ring 117-2, wherein at least one of the following is true: the first wafer 110 includes a first wafer test line portion 180-1 located between the first wafer edge 110a and the first wafer sealing ring 117-1, or the second wafer 120 includes a second wafer test line portion 180-2 located between the second wafer edge 120a and the second wafer sealing ring 117-2; attaching the first layer 10 to the second layer 20 such that the back side 120b of the second wafer 120 is opposite to the first wafer 110. Attaching the first layer 10 to the second layer 20 may include attaching the first layer 10 to the second layer 20 such that the first wafer 110 is electrically coupled to a silicon via 129 in the second wafer 120. The second wafer 120 may include a second wafer test line portion 180-2, which may include a test line portion metal feature 116T. The formation of the second layer 20 may include forming a second layer 20 such that the test line portion metal feature 116T is accessible through an opening in the passivation layer 138 of the second wafer 120. The first wafer 110 may include a first wafer test line portion 180-1, and attaching the first layer 10 to the second layer 20 such that the first wafer test line portion 180-1 is electrically coupled to a through-silicon via 629 in the second wafer 120.

[0214] Same reference Figures 1A to 8The test method package may include providing a semiconductor device 100 including a first wafer 110 including a first wafer edge 110a and a first wafer sealing ring 117-1, a second wafer 120 bonded to the first wafer 110 and including a second wafer edge 120a and a second wafer sealing ring 117-2, and a test line portion including at least one of the following: the first wafer 110 including a first wafer test line portion 180-1 located between the first wafer edge 110a and the first wafer sealing ring 117-1, or the second wafer 120 including a second wafer test line portion 180-2 located between the second wafer edge 120a and the second wafer sealing ring 117-2; etching the second wafer 120 to expose a contact pad 103 electrically coupled to a metal feature 116 in the second wafer 120; and attaching a test probe 402 of a wafer receiving test tool 400 to the exposed contact pad 103 to electrically couple the wafer receiving test tool 400 to the test line portion.

[0215] This document discloses various embodiments that provide a semiconductor device that may include simplified methods to allow testing of different functions or portions of the semiconductor device 110 and / or dummy wafer 130. By providing test line portions (first wafer test line portion 180-1 / second wafer test line portion 180-2) on either the first wafer 110 or the second wafer 120, the design of the semiconductor device 110 may be more flexible and may increase the ability to monitor the semiconductor device 110 during manufacturing. The test line portions (first wafer test line portion 180-1 / second wafer test line portion 180-2) may allow the wafer acceptance test tool 400 to test different functions or portions of the first wafer 110 and the second wafer 120, and to determine whether physical stress or thermal expansion during manufacturing will degrade or damage the semiconductor device 100. This may allow the wafer acceptance test tool 400 to monitor the impact of the manufacturing process on the semiconductor device 100. This document discloses different embodiments for forming a semiconductor device 100 having a first wafer 110 and a second wafer 120 stacked together, wherein at least one of the second wafer 120 includes a test line portion (first wafer test line portion 180-1 / second wafer test line portion 180-2). Furthermore, this document discloses different testing methods using the test line portions (first wafer test line portion 180-1 / second wafer test line portion 180-2) to test different functions and / or structures of the semiconductor device 100.

[0216] According to some embodiments of this disclosure, a semiconductor device includes a first wafer, a second wafer, and a test line portion. The first wafer includes a first wafer edge and a first wafer sealing ring. The second wafer is bonded to the first wafer and includes a second wafer edge and a second wafer sealing ring. The test line portion includes at least one of the following: the first wafer test line portion is located within the first wafer, between the first wafer edge and the first wafer sealing ring; or the second wafer test line portion is located within the second wafer, between the second wafer edge and the second wafer sealing ring.

[0217] In some embodiments, the test line portion includes a second wafer test line portion, and the second wafer test line portion includes a test line portion metallic feature disposed on a test tool electrically coupled to it.

[0218] In some embodiments, the second wafer test line portion further includes a test line portion sealing ring surrounding the metal features of the test line portion.

[0219] In some embodiments, the second wafer test line portion is located between the second wafer edge and the second wafer sealing ring along the first direction, and the distance between the second wafer edge and the second wafer sealing ring along the first direction is greater than the distance between the second wafer edge and the second wafer sealing ring along the second direction perpendicular to the first direction.

[0220] In some embodiments, the first wafer sealing ring has a first wafer sealing ring length along a first direction and a first wafer sealing ring width along a second direction that is less than the first wafer sealing ring length.

[0221] In some embodiments, the second wafer sealing ring has a second wafer sealing ring length along a first direction and a second wafer sealing ring width along a second direction that is smaller than the second wafer sealing ring length, and the second wafer sealing ring length is larger than the first wafer sealing ring length.

[0222] In some embodiments, the second wafer further includes a wafer substrate and conductive pillars located in the wafer substrate, configured to electrically couple the second wafer to the first wafer.

[0223] In some embodiments, the semiconductor device further includes a bonding layer located between the first wafer and the second wafer, and a bonding layer bonding pad in the bonding layer and bonded to a conductive pillar.

[0224] In some embodiments, the first wafer includes a wafer bonding film and a wafer bonding pad in the bonding film, wherein the wafer bonding pad is bonded to a bonding layer bonding pad.

[0225] In some embodiments, the semiconductor device further includes a dummy wafer adjacent to the first wafer and bonded to the second wafer via a bonding layer, and a first packaging layer encapsulating the dummy wafer and the first wafer.

[0226] In some embodiments, a second encapsulation layer is further included to encapsulate the second wafer, wherein the second encapsulation layer is bonded to the first encapsulation layer via a bonding layer.

[0227] In some embodiments, the test line portion includes a first wafer test line portion, and the first wafer test line portion includes a test line portion metal feature disposed on a test tool electrically coupled to it.

[0228] In some embodiments, the second wafer further includes a wafer substrate and conductive pillars in the wafer substrate and disposed in a portion electrically coupling the second wafer to the first wafer test line.

[0229] In some embodiments, the first wafer test line portion is electrically isolated from the second wafer.

[0230] In some embodiments, the test line portion includes a first wafer test line portion and a second wafer test line portion.

[0231] According to some embodiments of this disclosure, a method of manufacturing a semiconductor device includes forming a first layer and a second layer. The first layer includes a first wafer, the first wafer including a first wafer edge and a first wafer sealing ring. The second layer includes a second wafer, the second wafer including a second wafer edge and a second wafer sealing ring, wherein at least one of the following is true: the first wafer includes a first wafer test line portion between the first wafer edge and the first wafer sealing ring, or the second wafer includes a second wafer test line portion between the second wafer edge and the second wafer sealing ring; and the first layer is attached to the second layer such that the back side of the second wafer is relative to the first wafer.

[0232] In some embodiments, the attachment of the first layer to the second layer includes attaching the first layer to the second layer such that the first wafer is electrically coupled to a silicon via in the second wafer.

[0233] In some embodiments, the second wafer includes a second wafer test line portion, the second wafer test line portion includes test line portion metal features and the formation of a second layer, wherein the formation of the second layer makes the test line portion metal features accessible through an opening in the second wafer isolation layer.

[0234] In some embodiments, the first wafer includes a first wafer test line portion, and the attachment of the first layer to the second layer includes attaching the first layer to the second layer such that the first wafer test line portion is electrically coupled to a silicon via in the second wafer.

[0235] According to some embodiments of this disclosure, a method for testing a semiconductor device includes providing a semiconductor device comprising a first wafer, a second wafer, and a test line portion. The first wafer includes a first wafer edge and a first wafer sealing ring. The second wafer is bonded to the first wafer and includes a second wafer edge and a second wafer sealing ring. The test line portion includes at least one of the following: the first wafer test line portion is located within the first wafer and between the first wafer edge and the first wafer sealing ring; or the second wafer test line portion is located within the second wafer and between the second wafer edge and the second wafer sealing ring. The second wafer is etched to expose contact pads electrically coupled to metallic features in the second wafer, and a test probe of a test tool is attached to the exposed contact pads to electrically couple the test tool to the test line portion.

[0236] According to some embodiments of this disclosure, a semiconductor device includes a first wafer, a second wafer, and a test line portion. The first wafer includes a first wafer edge and a first wafer sealing ring. The second wafer is bonded to the first wafer and includes a second wafer edge and a second wafer sealing ring. The test line portion includes a first wafer test line portion located within the first wafer, between the first wafer edge and the first wafer sealing ring, and a second wafer test line portion located within the second wafer, between the second wafer edge and the second wafer sealing ring. The second wafer test line portion includes a test line portion metallic feature disposed on a test tool electrically coupled to it.

[0237] According to some embodiments of this disclosure, a semiconductor device includes a first wafer, a second wafer, and a test line portion. The first wafer includes a first wafer edge and a first wafer sealing ring. The second wafer is bonded to the first wafer and includes a second wafer edge and a second wafer sealing ring. The test line portion includes a first wafer test line portion located within the first wafer, between the first wafer edge and the first wafer sealing ring, and a second wafer test line portion located within the second wafer, between the second wafer edge and the second wafer sealing ring. The second wafer further includes a wafer substrate and a conductive post located within the wafer substrate, the conductive post being configured to electrically couple the second wafer to the first wafer.

[0238] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A first chip, comprising a first chip edge and a first chip sealing ring; A second chip, bonded to the first chip, and including a second chip edge and a second chip sealing ring; and A test line section includes at least one of the following: A first wafer test line portion is located within the first wafer, between the edge of the first wafer and the sealing ring of the first wafer; or A second wafer test line is located within the second wafer, between the edge of the second wafer and the sealing ring of the second wafer.

2. The semiconductor device as claimed in claim 1, characterized in that, The test line portion includes the second wafer test line portion, and the second wafer test line portion includes a test line portion metal feature disposed in an electrical coupling with a test tool.

3. The semiconductor device as claimed in claim 2, characterized in that, The second wafer test line portion also includes a test line portion sealing ring surrounding the metallic features of the test line portion.

4. The semiconductor device as claimed in claim 2, characterized in that, The second wafer test line portion is located between the second wafer edge and the second wafer sealing ring along a first direction, and the distance between the second wafer edge and the second wafer sealing ring along the first direction is greater than the distance between the second wafer edge and the second wafer sealing ring along a second direction perpendicular to the first direction.

5. The semiconductor device as claimed in claim 4, characterized in that, The first wafer sealing ring has a first wafer sealing ring length along the first direction and a first wafer sealing ring width that is smaller than the first wafer sealing ring length along the second direction.

6. The semiconductor device as claimed in claim 5, characterized in that, The second wafer sealing ring has a second wafer sealing ring length along the first direction and a second wafer sealing ring width along the second direction that is smaller than the second wafer sealing ring length, and the second wafer sealing ring length is larger than the first wafer sealing ring length.

7. The semiconductor device as claimed in claim 2, characterized in that, The second chip also includes: A chip substrate; and A conductive post is located in the wafer substrate and is configured to electrically couple the second wafer to the first wafer.

8. The semiconductor device as claimed in claim 7, characterized in that, Also includes: A bonding layer is located between the first wafer and the second wafer; and A bonding layer is attached to the bonding layer and is bonded to the conductive post.

9. A semiconductor device, characterized in that, Include: A first chip, comprising a first chip edge and a first chip sealing ring; A second chip, bonded to the first chip, and including a second chip edge and a second chip sealing ring; and One test line section includes: A first wafer test line portion, located within the first wafer, between the edge of the first wafer and the sealing ring of the first wafer; and A second wafer test line portion is located within the second wafer, between the edge of the second wafer and the sealing ring of the second wafer, wherein the second wafer test line portion includes a test line portion metallic feature disposed in an electrical coupling with a test tool.

10. A semiconductor device, characterized in that, Include: A first chip, comprising a first chip edge and a first chip sealing ring; A second chip, bonded to the first chip, and including a second chip edge and a second chip sealing ring; and One test line section includes: A first wafer test line portion, located within the first wafer, between the edge of the first wafer and the sealing ring of the first wafer; and A second wafer test line is located in the second wafer, between the edge of the second wafer and the sealing ring of the second wafer. The second wafer also includes a wafer substrate and a conductive post located in the wafer substrate. The conductive post electrically couples the second wafer to the first wafer.

Images