Leveling detection circuit for chuck and probe card and wafer aging test system

Abstract

The utility model discloses a leveling detection circuit used for a chuck and a probe card and a wafer aging test system, leveling probes are arranged on the probe card, each leveling probe is connected with the chuck through a circuit conduction detection chip and a power supply, when the height of each jack on the chuck changes, the leveling probes are contacted with the chuck, and when the height of each jack on the chuck changes, the leveling probes are in contact with the chuck. The leveling probe in contact with the chuck, the circuit conduction detection chip, the power supply and the chuck form a conduction loop; when the height difference between the first jacking height corresponding to the first conducted first input end in the circuit conduction detection chip and the second jacking height corresponding to the last conducted first input end is smaller than the preset height difference, the upper computer determines that the chuck is parallel to the probe card. When the leveling probe is in contact with the chuck, the trigger circuit conducts the conduction of the corresponding first input end of the detection chip, so that the upper computer is triggered to determine whether the chuck and the probe card are parallel to each other or not, and the control and judgment accuracy of leveling of the chuck and the probe card is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of power electronic technology test, especially relates to a kind of for chuck and probe card leveling detection circuit and wafer burn-in test system. BACKGROUND

[0002] In wafer test, chuck is usually used to carry wafer, and a plurality of probes are provided on probe card, and the probes on probe card contact the pads or bumps on wafer to test the electrical properties of wafer. If probe card and chuck are not parallel, the probes on probe card cannot contact all pads on wafer, or the pressure of some probes is too large, which accelerates the wear of probes and affects the service life of probe card, while the other probes are not in good contact, which leads to inaccurate wafer test results or even damage to wafer. Therefore, before wafer test, chuck and probe card need to be leveled.

[0003] In the prior art, when leveling chuck and probe card, one leveling probe is provided on each of the four edges of probe card, each leveling probe is connected to external power supply through an LED (light-emitting diode), and the external power supply is connected to chuck. By adjusting the lifting height of chuck, the leveling probe contacts chuck. When one of the leveling probes contacts chuck, the leveling probe in contact with chuck, LED and external power supply form a conducting loop with chuck. Then, the LED connected to the leveling probe in contact with chuck is lit, and the operator can determine whether chuck and probe card are parallel by observing whether the four LEDs are lit and the height difference of the lifting height of chuck when the four LEDs are lit. Then, chuck and probe card are leveled. However, this method relies on the naked eye observation of the operator, and cannot guarantee the leveling efficiency, precision and accuracy of chuck and probe card. UTILITY MODEL CONTENTS

[0004] The utility model aims to provide a leveling detection circuit for chuck and probe card and wafer burn-in test system. When leveling probe contacts chuck, the conduction of the corresponding first input end of the detection chip is triggered by the conduction of the trigger circuit, and then the host computer determines whether chuck and probe card are parallel, which improves the control and judgment accuracy of chuck and probe card leveling.

[0005] To solve the above technical problems, the utility model provides a leveling detection circuit for chuck and probe card, which comprises a plurality of leveling probes, a circuit conduction detection chip, a power supply and a host computer.

[0006] Any leveling probe in the plurality of leveling probes is arranged on a probe card; each of the leveling probes is connected with a corresponding first input end of the circuit conduction detection chip; a second input end of the circuit conduction detection chip is connected with a first end of the power supply; a second end of the power supply is connected with the chuck; the circuit conduction detection chip is connected with a communication end of the upper computer;

[0007] Each first input end of the circuit conduction detection chip simultaneously changes in height of each jacking of the chuck until the corresponding leveling probe is in contact with the chuck and is turned on; when a height difference between a first height of the first jacking corresponding to the first input end that is first turned on and a second height of the second jacking corresponding to the last input end that is last turned on is less than a preset height, the upper computer determines that the chuck and the probe card are parallel to each other.

[0008] Preferably, the power supply is a wafer test low-voltage source table, which is used to supply low voltage to a circuit in which the first input end of the circuit conduction detection chip is turned on, or to supply low voltage to a circuit composed of the probe card and the wafer when wafer low-voltage testing is performed.

[0009] Preferably, the control switch board further comprises a first power supply end and a second power supply end.

[0010] The first power supply end of the control switch board is connected with each second input end of the circuit conduction detection chip, the second power supply end is connected with the chuck, the first power supply end is connected with a first output end of the wafer test low-voltage source table, and the second power supply end is connected with a second output end of the wafer test low-voltage source table, so as to close the circuit between the circuit conduction detection chip, the wafer test low-voltage source table and the chuck.

[0011] Preferably, the control switch board further comprises a high-voltage isolation circuit.

[0012] Each first input end of the high-voltage isolation circuit is connected with each leveling probe, and each second input end is connected with each first input end of the circuit conduction detection chip, so as to be turned off when wafer low-voltage testing and wafer high-voltage testing are performed, and to be closed when leveling detection of the chuck and the probe card is performed.

[0013] The third power supply end of the control switch board is connected with the first output end of the wafer test high-voltage source table, the fourth power supply end is connected with the second output end of the wafer test high-voltage source table, and the control switch board is further used for closing in a first mode to make a circuit formed by the probe card, the wafer and the wafer test low-voltage source table closed when wafer low-voltage test is performed, closing in a second mode to make a circuit formed by the probe card, the wafer and the wafer test high-voltage source table closed when wafer high-voltage test is performed, and closing in a third mode to make a circuit between the circuit conduction detection chip, the wafer test low-voltage source table and the chuck closed when leveling detection of the chuck and the probe card is performed.

[0014] Preferably, the high-voltage isolation circuit comprises a plurality of high-voltage isolation switches, the first end of each of the high-voltage isolation switches is a first input end of the high-voltage isolation circuit, the second end of each of the high-voltage isolation switches is a second input end of the high-voltage isolation circuit, and the control end of each of the high-voltage isolation switches is a control end of the high-voltage isolation circuit.

[0015] Preferably, the high-voltage isolation switch is an NMOS.

[0016] Preferably, the high-voltage isolation circuit comprises a plurality of contacts of a relay and a coil of the relay.

[0017] The first end of each of the contacts is a first input end of the high-voltage isolation circuit, and the second end of each of the contacts is a second input end of the high-voltage isolation circuit.

[0018] The coil of the relay is used to be electrified when the leveling detection of the chuck and the probe card is performed, so that the coil of the relay attracts each of the contacts of the relay.

[0019] Preferably, the high-voltage isolation circuit further comprises a high-voltage isolation control chip.

[0020] The output end of the high-voltage isolation control chip is connected with the coil of the relay, and is used to control the coil of the relay to be electrified when the leveling detection of the chuck and the probe card is performed, so that the coil of the relay attracts each of the contacts of the relay.

[0021] Preferably, a plurality of indicator lights are further included, each of the indicator lights corresponds to each of the leveling probes one by one.

[0022] The indicator light is connected between the corresponding leveling probe and the first input end of the corresponding circuit conduction detection chip, and is used to be lighted when the first input end of the corresponding circuit conduction detection chip is conducted.

[0023] To solve the above technical problems, the utility model provides a wafer aging test system, including the leveling detection circuit for chuck and probe card as described above.

[0024] The application provides a leveling detection circuit for a chuck and a probe card and a wafer aging test system, leveling probes are arranged on the probe card, each leveling probe is connected with the chuck through a circuit conduction detection chip and a power supply, when the height of each jack on the chuck changes, the leveling probe contacts the chuck, the leveling probe contacting the chuck, the circuit conduction detection chip, the power supply and the chuck form a conduction loop, and the host computer determines that the chuck and the probe card are parallel to each other when the height difference between the first height of the jack corresponding to the first input end of the first conduction in the circuit conduction detection chip and the second height of the jack corresponding to the first input end of the last conduction is less than a preset height difference. The conduction of the corresponding first input end of the circuit conduction detection chip is triggered when the leveling probe contacts the chuck, and then the host computer is triggered to determine whether the chuck and the probe card are parallel to each other, thereby improving the control and judgment accuracy of the leveling of the chuck and the probe card. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the utility model, the drawings needed in the embodiments will be simply introduced below, and obviously, the drawings in the following description are only some embodiments of the utility model, and other drawings can be obtained according to these drawings without creative labor for those skilled in the art.

[0026] Figure 1 A structural schematic diagram of the leveling detection circuit for the chuck and the probe card is provided for the utility model,

[0027] Figure 2 A specific structural schematic diagram of the leveling detection circuit for the chuck and the probe card is provided for the utility model. DETAILED DESCRIPTION

[0028] The core of the utility model is to provide a leveling detection circuit for a chuck and a probe card and a wafer aging test system, the conduction of the corresponding first input end of the circuit conduction detection chip is triggered when the leveling probe contacts the chuck, and then the host computer is triggered to determine whether the chuck and the probe card are parallel to each other, thereby improving the control and judgment accuracy of the leveling of the chuck and the probe card.

[0029] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be described clearly and completely in combination with the drawings in the embodiments of the utility model below. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.

[0030] Please refer to Figure 1 , Figure 1 The utility model provides a kind of for the structural diagram of leveling detection circuit of chuck and probe card, including multiple leveling probes 1, circuit conduction detection chip 2, power supply 3 and host computer 4;

[0031] Any leveling probe 1 in multiple leveling probes 1 is arranged on probe card 6;Each leveling probe 1 is connected with the corresponding first input end of circuit conduction detection chip 2 respectively;The second input end of circuit conduction detection chip 2 is connected with the first end of power supply 3;The second end of power supply 3 is connected with chuck 7;Circuit conduction detection chip 2 is connected with the communication end of host computer 4;

[0032] Each first input end of circuit conduction detection chip 2 simultaneously changes in the height of each jacking 5 of chuck until the corresponding leveling probe 1 is in contact with chuck and is conducted, when the height difference between the first height of the first jacking 5 corresponding to the first conducted first input end in circuit conduction detection chip 2 and the second height of the second jacking 5 corresponding to the last conducted first input end is less than preset height difference, host computer 4 determines that chuck 7 and probe card 6 are mutually parallel.

[0033] Wafer test, also known as wafer probe test, is a key step in semiconductor manufacturing process, before chip packaging. The core purpose of wafer test is to detect the electrical performance of each integrated circuit chip on the wafer, to screen out the chips with normal function and functional defects. The chips with normal function will enter the subsequent packaging process, while the chips with functional defects will be marked as invalid and discarded, thereby saving chip packaging and assembly cost, and improving the yield of final chip product.

[0034] The probe card 6 is an interface device connecting the tester and the wafer, which is composed of a plurality of precisely arranged metal probes. Each probe corresponds to a pad of the chip. During testing, the probe is pressed to contact the pad. The tester transmits test signals to the chip through the probe card 6 and receives feedback. The chuck 7 (wafer stage) is a platform for carrying and fixing the wafer. It can usually perform vacuum adsorption on the wafer. The wafer is fixed by negative pressure to prevent displacement of the wafer and ensure accurate alignment of each chip on the wafer with the probe card 6. During the wafer testing process, the wafer is placed on the chuck 7 and fixed by vacuum. The alignment mark of the wafer is identified through the optical system. The position is adjusted to align the pads of the chip with the probes. The probes are brought into contact with the pads by controlling the chuck 7 to rise or the probe card 6 to press down. The tester applies test signals to the chip through the probes and collects response data. The test results are analyzed according to the response data, and the chip is marked when it is determined to be a failed chip.

[0035] It can be seen that, in order to ensure the accuracy of the wafer test results, the leveling detection between the probe card 6 and the chuck 7 is a key step to ensure that the probes of the probe card 6 and the surface of the wafer are parallel to each other. If the probe card 6 or the chuck 7 is inclined, some probes may not contact the pads, resulting in an open circuit, and other probes may be pressed too much, causing damage to the pads or bending of the probes. Therefore, by detecting whether the probe card 6 and the chuck 7 are leveled, it can be ensured that all the probes are uniformly stressed, and the stability of signal transmission during the wafer testing process is ensured.

[0036] In the present application, in order to detect whether the probe card 6 and the chuck 7 are leveled, a plurality of leveling probes 1 are arranged on the probe card 6, the leveling probes 1 are connected with the circuit conduction detection chip 2, the circuit conduction detection chip 2 is connected with the power supply 3, the power supply 3 is connected with the chuck 7, that is, the leveling probes 1, the circuit conduction detection chip 2, the power supply 3 and the chuck 7 are connected in sequence. When the chuck 7 contacts any one of the leveling probes 1 on the probe card 6 due to the change in the height of the chuck 7, the leveling probe 1 in contact with the chuck 7, the circuit conduction detection chip 2, the power supply 3 and the chuck 7 form a loop, therefore, the first input end connected with the leveling probe 1 in contact with the chuck 7 in the circuit conduction detection chip 2 has current passing through, that is, the first input end connected with the leveling probe 1 in contact with the chuck 7 is conducted. The height of the jacking 5 of the chuck 7 continues to change until each leveling probe 1 on the probe card 6 contacts the chuck 7, so that each first input end in the circuit conduction detection chip 2 has current passing through, that is, each first input end is conducted. Based on this, the first height of the jacking 5 corresponding to the first input end that is first conducted and the second height corresponding to the last conducted first input end in the circuit conduction detection chip 2 are calculated, and the height difference between the first height and the second height is calculated, such as the height difference obtained by subtracting the first height from the second height, the height difference is a positive number after taking the absolute value, if the height difference is less than a preset height difference, then the host computer 4 can be triggered to determine that the probe card 6 and the chuck 7 are parallel to each other; and if the height difference is not less than the preset height difference, then the host computer 4 can be triggered to determine that the probe card 6 and the chuck 7 do not maintain parallel to each other.

[0037] It should be noted that each leveling probe 1 can be arranged at each preset position on the probe card 6, and each preset position can be but not limited to the edge positions of different directions on the probe card 6, that is, each preset position can be the position of the probe card 6 at the edges in the up, down, left and right four directions, when the probe card 6 and the chuck 7 are parallel to each other, the distances between the probe card 6 in the up, down, left and right four directions and the chuck 7 are consistent or less than a preset distance, therefore, the time difference of each leveling probe 1 contacting the chuck 7 and causing each first input end in the circuit conduction detection chip 2 to be conducted is less than a preset time; and when the probe card 6 and the chuck 7 do not maintain parallel to each other, then an inclination alarm can be given, or the jacking 5 at different positions of the chuck 7 can be adjusted, so as to adjust the relative height between the side of the probe card 6 and the chuck 7 which do not maintain relative horizontal due to the large distance between the probe card 6 and the chuck 7, until the probe card 6 and the chuck 7 are parallel to each other. The length of the leveling probe 1 can be longer than the length of the test probe for wafer detection, so as to avoid the test probe being bent and damaged due to excessive pressure in the leveling process.

[0038] The control signal output end of the upper computer 4 can be connected with each of the jacks 5 of the chuck 7, so that the upper computer 4 adjusts the height of each of the jacks 5 of the chuck 7 to adjust the height of the chuck 7, or the height of the jack 5 can be manually adjusted by a worker, which is not limited in the application. The chip can not be placed on the chuck 7 during the leveling detection, so as to avoid that the leveling probe 1 crushes the chip.

[0039] Of course, each of the preset positions can correspond to the position of each of the jacks 5 of the chuck 7 one by one. When it is determined that the chuck 7 and the probe card 6 are not parallel to each other, the height of the jack 5 corresponding to the position of the leveling probe 1 connected with the first input end of the first conduction of the circuit conduction detection chip 2 can be adjusted, for example, the height of the jack 5 corresponding to the position of the leveling probe 1 connected with the first input end of the first conduction of the circuit conduction detection chip 2 is adjusted to be lower, the height of the jack 5 corresponding to the position of the leveling probe 1 connected with the first input end of the last conduction of the circuit conduction detection chip 2 is adjusted to be higher, until the chuck 7 and the probe card 6 are parallel to each other. When it is determined that the chuck 7 and the probe card 6 are not parallel to each other, an inclination alarm can be given, so that the worker adjusts the chuck 7 and the probe card 6 to be parallel to each other. Figure 1 Only an example in which four leveling probes 1 are arranged on four edges of the probe card 6 is given in the application, but in fact, the four leveling probes 1 and the three leveling probes 1 can ensure the accuracy of the result of whether the detected probe card 6 and the chuck 7 are parallel to each other, and the cost is relatively low. Figure 1 Although only three jacks 5 of the chuck 7 are shown in the application, in fact, the chuck 7 does not necessarily have only three jacks 5, and the actual structure of the chuck 7 and the detection demand are used as the criterion.

[0040] Specifically, when the heights of the respective jacks 5 change simultaneously, the chuck 7 sequentially contacts the respective leveling probes 1, and the host computer 4 can first record the first height of the jack 5 corresponding to the first input end of the first circuit conduction detection chip 2 that is first turned on, until all the first input ends of the circuit conduction detection chip 2 are turned on, and record the second height of the jack 5 corresponding to the first input end of the last circuit conduction detection chip 2 that is turned on, calculate the height difference between the first height and the second height, if the height difference is less than a preset height difference, then it can be determined that the chuck 7 and the probe card 6 remain relatively horizontal, and if the height difference is not less than the preset height difference, then the chuck 7 and the probe card 6 are not parallel to each other, and then the host computer 4 can adjust the respective jacks 5 accordingly, such as adjusting the height of the jack 5 according to the conduction order of each first input end of the circuit conduction detection chip 2 during the lifting of the jack 5, such as lowering the height of the jack 5 corresponding to the position of the leveling probe 1 connected to the first input end of the circuit conduction detection chip 2 that is first turned on, and raising the height of the jack 5 corresponding to the position of the leveling probe 1 connected to the first input end of the circuit conduction detection chip 2 that is last turned on, until the chuck 7 and the probe card 6 remain parallel to each other. Of course, how to determine that the chuck 7 and the probe card 6 are not parallel to each other and then process it is not limited in the present application.

[0041] In the determination of the first height and the second height, the initial height of the jack 5, the start time of the height adjustment of the jack 5, the conduction time of the first input end of the circuit conduction detection chip 2, and the height change speed during the height adjustment of the jack 5 can be used for calculation, and the height change speed during the height adjustment of the jack 5 can be determined based on the control pulse of the host computer 4 controlling the jack 5, which is not limited in the present application. Specifically, the initial height of each jack 5 is the same, the first height change amount of the jack 5 when the first input end of the circuit conduction detection chip 2 is conducted is the product of the difference between the conduction time when the first input end of the circuit conduction detection chip 2 is conducted and the start time and the height change speed, the sum of the initial height and the first height change amount is the first height, the second height change amount of the jack 5 when the last input end of the circuit conduction detection chip 2 is conducted is the product of the difference between the conduction time when the last input end of the circuit conduction detection chip 2 is conducted and the start time and the height change speed, and the sum of the initial height and the second height change amount is the second height. The height change amount of each jack 5 can also be detected by a sensor to determine the first height and the second height. For example, the first height of each jack 5 when the first leveling probe 1 contacts the chuck 7, i.e., when the first input end of the circuit conduction detection chip 2 is conducted, is identified by an infrared sensor, and the second height of each jack 5 when the last leveling probe 1 contacts the chuck 7, i.e., when the last input end of the circuit conduction detection chip 2 is conducted, is identified. Each jack 5 can correspond to a sensor, or a sensor can detect the height of each jack 5 at the same time, of course, which is not limited in the present application.

[0042] The preset height difference can be but is not limited to 100um, and can be set according to the hardware structure of the chuck 7 and the probe card 6.

[0043] It should be noted that the circuit conduction detection chip 2 can be but is not limited to an I / O (Input / Output) chip, each leveling probe 1 is connected to the first input end of each I / O channel of the I / O chip, the second input end of each I / O channel connected to the leveling probe 1 is connected to the first end of the power supply 3, and the communication end is connected to the first communication end of the host computer 4. When the leveling probe 1 contacts the chuck 7, the I / O channel connected to the leveling probe 1 in contact with the chuck 7 is conducted, and the I / O chip determines whether the leveling probe 1 contacts the chuck 7 by reading the conduction information of the I / O channel, and sends the information of the conducted I / O channel to the host computer 4. Of course, this is not limited in the present application.

[0044] It also needs to be explained that the various communication ends of the host computer 4 can all be multiplexed into the same communication end, that is, the first communication end, the second communication end and the third communication end can be the same end, and the host computer 4 determines the other end for data interaction and the specific meaning of the data by classifying the transmitted and received data differently. The communication end of the circuit conduction detection chip 2 can also multiplex its own second input end, which is not limited in the present application.

[0045] It can be seen that in the present application, the conduction of the corresponding first input end of the circuit conduction detection chip 2 is triggered when the leveling probe 1 contacts the chuck, and then the host computer 4 determines whether the chuck and the probe card are parallel to each other, thereby improving the accuracy of control and judgment of the leveling of the chuck and the probe card.

[0046] On the basis of the above-mentioned embodiments:

[0047] Please refer to Figure 2 , Figure 2 The specific structural diagram of the leveling detection circuit for the chuck and the probe card provided by the present application is shown in the accompanying drawings.

[0048] As a preferred embodiment, the power supply 3 is a wafer test low-voltage source table 31, which is used to supply low voltage to the circuit in which the first input end of the circuit conduction detection chip 2 is located, or to supply low voltage to the circuit composed of the probe card 6 and the wafer when wafer low-voltage testing is performed.

[0049] The power supply 3 in the present embodiment multiplexes the wafer test low-voltage source table 31, that is, when the chuck 7 contacts the leveling probe 1, the wafer test low-voltage source table 31 supplies power to the loop composed of the leveling probe 1 in contact with the chuck 7, the circuit conduction detection chip 2, the wafer test low-voltage source table 31 and the chuck 7, and the wafer test low-voltage source table 31 is a power supply for supplying low voltage to the circuit composed of the probe card 6 and the wafer when wafer low-voltage testing is performed.

[0050] Wafer low-voltage testing refers to the wafer test low-voltage source table 31 outputting low-voltage power to the test probe in the probe card 6, so that the tester determines the state of the wafer based on the test response of the wafer under low-voltage power, and therefore, the wafer test low-voltage source table 31 is a power supply that already exists in the wafer test circuit, and in the present embodiment, it is multiplexed so that the wafer test low-voltage source table 31 can supply low voltage to the loop composed of the leveling probe 1 in contact with the chuck 7, the circuit conduction detection chip 2, the wafer test low-voltage source table 31 and the chuck 7 when leveling detection is performed on the chuck 7 and the probe card 6, ensuring that the host computer 4 can recognize the first input end of the circuit conduction detection chip 2 at the same time, avoiding damage to the modules in the circuit by high voltage, and also saving space and reducing cost.

[0051] As a preferred embodiment, the control switch board 8 is further included;

[0052] The first power supply end of the control switch board 8 is connected with each second input end of the circuit conduction detection chip 2, the second power supply end is connected with the chuck 7, the first power supply end is connected with the first output end of the wafer test low-voltage source table 31, and the second power supply end is connected with the second output end of the wafer test low-voltage source table 31, so as to close the circuit between the circuit conduction detection chip 2, the wafer test low-voltage source table 31 and the chuck 7.

[0053] Considering that the wafer test and the leveling detection are not performed at the same time, and the circuit of the wafer test and the circuit of the leveling detection are independent of each other, and the wafer test low-voltage source table 31 needs to supply power when the circuits are turned on, the control switch board 8 is arranged in the present application, the control switch board 8 is connected between the chuck 7 and the circuit conduction detection chip 2, when the leveling detection is performed, the upper computer 4 controls the control switch board 8, or manually controls the control switch board 8, so as to close the circuit between the circuit conduction detection chip 2, the wafer test low-voltage source table 31 and the chuck 7, when the chuck 7 contacts the leveling probe 1, the circuit formed by the leveling probe 1 contacting the chuck 7, the circuit conduction detection chip 2, the wafer test low-voltage source table 31 and the chuck 7 is turned on, and the wafer test low-voltage source table 31 supplies power to the circuit; when the leveling detection is not needed, the control switch board 8 cuts off the circuit between the circuit conduction detection chip 2, the wafer test low-voltage source table 31 and the chuck 7, so as to avoid that the wafer test result is abnormal due to that the wafer test low-voltage source table 31 supplies power to the leveling detection circuit during the wafer test.

[0054] As a preferred embodiment, the high-voltage isolation circuit 9 is further included;

[0055] Each first input end of the high-voltage isolation circuit 9 is connected with each leveling probe 1, and each second input end is connected with each first input end of the circuit conduction detection chip 2, so as to be turned off when the wafer low-voltage test and the wafer high-voltage test are performed, and closed when the leveling detection of the chuck and the probe card is performed.

[0056] The third power supply end of the control switch board 8 is connected with the first output end of the wafer test high-voltage source table, and the fourth power supply end is connected with the second output end of the wafer test high-voltage source table, and is further used for closing in the first mode to close the circuit formed by the probe card 6, the wafer and the wafer test low-voltage source table 31 when the wafer low-voltage test is performed, closing in the second mode to close the circuit formed by the probe card 6, the wafer and the wafer test high-voltage source table when the wafer high-voltage test is performed, and closing in the third mode to close the circuit between the circuit conduction detection chip 2, the wafer test low-voltage source table 31 and the chuck 7 when the leveling detection of the chuck 7 and the probe card 6 is performed.

[0057] In this embodiment, considering that the wafer test process not only includes wafer low-voltage test, but also includes wafer high-voltage test, therefore, the wafer test circuit not only includes the wafer test low-voltage source table 31, but also includes a wafer test high-voltage source table, the wafer test high-voltage source table is a power supply for supplying high-voltage power to the circuit formed by the probe card 6 and the wafer during wafer high-voltage test, the wafer high-voltage test refers to that the wafer test high-voltage source table outputs high-voltage power to the test probe in the probe card 6, so that the test machine determines the state of the wafer based on the test reaction of the wafer under high-voltage power, therefore, the voltage output by the wafer test high-voltage source table is high-voltage power. Since the power supply 3 in the present application multiplexes the wafer test low-voltage source table 31, the leveling detection circuit in the present application is connected with the wafer test circuit, in order to avoid that the high-voltage power output by the wafer test high-voltage source table is loaded into the leveling detection circuit and causes damage to the device, the present application further provides a high-voltage isolation circuit 9, the high-voltage isolation circuit 9 is arranged between the leveling probe 1 and the circuit conduction detection chip 2. When the wafer test is performed, whether it is wafer high-voltage test or wafer low-voltage test, the high-voltage isolation circuit 9 is turned off, and the wafer test high-voltage source table and the wafer test low-voltage source table 31 cannot access the leveling detection circuit, so as to protect the leveling detection circuit.

[0058] In addition, the control switch board 8 is connected between the wafer test high-voltage source table, the wafer test low-voltage source table 31 and the circuit conduction detection chip 2, when the wafer low-voltage test is performed, the control switch board 8 closes the circuit formed by the probe card 6, the wafer and the wafer test low-voltage source table 31; when the wafer high-voltage test is performed, the control switch board 8 closes the circuit formed by the probe card 6, the wafer and the wafer test high-voltage source table; when the leveling detection is performed, the control switch board 8 closes the circuit between the wafer test low-voltage source table 31 and the circuit conduction detection chip 2; therefore, the control switch board 8 can be improved on the basis of the wafer test switch board for switching the wafer test high-voltage source table and the wafer test low-voltage source table 31 in the wafer test circuit, so as to reduce the cost and save the space.

[0059] It should be noted that the first end and the second end of the wafer test high-voltage source table are the positive electrode and the negative electrode of the wafer test high-voltage source table respectively, and the first end and the second end of the wafer test low-voltage source table 31 are the positive electrode and the negative electrode of the wafer test low-voltage source table 31 respectively.

[0060] It should be further noted that only when the leveling detection of the probe card 6 and the chuck 7 is performed, the host computer 4 closes the high-voltage isolation circuit 9, otherwise the high-voltage isolation circuit 9 always remains in the off state.

[0061] As a preferred embodiment, the high-voltage isolation circuit 9 comprises a plurality of high-voltage isolation switches, the first end of each high-voltage isolation switch is respectively a first input end of the high-voltage isolation circuit 9, the second end of each high-voltage isolation switch is respectively a second input end of the high-voltage isolation circuit 9, and the control end of each high-voltage isolation switch is a control end of the high-voltage isolation circuit 9.

[0062] In this embodiment, the high-voltage isolation circuit 9 can be implemented by a plurality of high-voltage isolation switches, each high-voltage isolation switch is connected between each leveling probe 1 and each first input end of the circuit conduction detection chip 2, and each high-voltage isolation switch is closed at the same time and turned off at the same time to protect the leveling circuit.

[0063] As a preferred embodiment, the high-voltage isolation switch is an NMOS.

[0064] The high-voltage isolation switch in this embodiment can be, but is not limited to, an NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor), the gate of the NMOS is the control end of the high-voltage isolation switch, and the gate and the drain of the NMOS are respectively the first end and the second end of the high-voltage isolation switch. It can be adjusted according to the connection mode of the positive and negative poles of the wafer test low-voltage source table 31.

[0065] The NMOS can ensure high-voltage isolation while having a simple structure, low cost, and simple connection mode.

[0066] As a preferred embodiment, the high-voltage isolation circuit 9 comprises a plurality of contacts of a relay and a coil of the relay.

[0067] The first end of each contact is respectively a first input end of the high-voltage isolation circuit 9, and the second end of each contact is respectively a second input end of the high-voltage isolation circuit 9.

[0068] The coil of the relay is used to be powered when the leveling detection of the chuck 7 and the probe card 6 is performed, so that the coil of the relay attracts each contact of the relay.

[0069] The high-voltage isolation circuit 9 in this embodiment is implemented by the contacts of the relay and the coil of the relay. Specifically, each contact of the relay is connected between each leveling probe 1 and each first input end of the circuit conduction detection chip 2. When the leveling detection is performed, the coil of the relay is powered to attract each contact of the relay, so that the circuit between each leveling probe 1 and each first input end of the circuit conduction detection chip 2 is closed. When the leveling detection is completed, the coil of the relay is de-energized to release each contact of the relay, so that the circuit between each leveling probe 1 and each first input end of the circuit conduction detection chip 2 is turned off.

[0070] The coil and the contact of the relay are connected through high and low voltage circuits with high physical isolation, effectively improving the safety, reliability and flexibility of the system.

[0071] It should be noted that the coil of the relay can be connected with the third communication end of the upper computer 4, so that the upper computer 4 energizes or de-energizes the coil of the relay, of course, the present application does not limit this.

[0072] As a preferred embodiment, the high-voltage isolation circuit 9 further comprises a high-voltage isolation control chip;

[0073] The output end of the high-voltage isolation control chip is connected with the coil of the relay, and is used for controlling the coil of the relay to be energized when the leveling detection of the chuck 7 and the probe card 6 is performed, so that the coil of the relay attracts each contact of the relay.

[0074] In the embodiment, the coil of the relay is additionally provided with a high-voltage isolation control chip for controlling the coil, and the high-voltage isolation control chip controls the coil of the relay to be energized, that is, the high-voltage isolation control chip can supply power to the coil of the relay when the leveling detection of the chuck 7 and the probe card 6 is performed, thereby improving the control efficiency of the coil of the relay.

[0075] The high-voltage isolation control chip can be connected with the third communication end of the upper computer 4 to receive the leveling control instruction of the upper computer 4 and control the coil of the relay to be energized, and the present application does not limit this, and the high-voltage isolation chip can also be manually controlled to control the coil of the relay to be energized or de-energized.

[0076] As a preferred embodiment, the upper computer 4 is an MCU (Microcontroller Unit, microcontroller unit) or a single-chip microcomputer.

[0077] In the embodiment, the upper computer 4 can be an MCU or a single-chip microcomputer, which not only can control the jacking 5 and receive the information of the first input end of the on-off detection chip 2, but also has low cost, high real-time performance and high integration.

[0078] The wafer aging test system in the present application comprises the leveling detection circuit for the chuck and the probe card as described above.

[0079] For the wafer aging test system provided by the present application, please refer to the above-mentioned embodiments, and the present application will not be repeated here.

[0080] It is also important to note that the use of relational terms such as first and second, and the like, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0081] The above description of disclosed embodiments provides enabling concepts for practicing or using the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A leveling and detection circuit for a chuck and probe card, characterized in that, Includes multiple leveling probes, a circuit continuity detection chip, a power supply, and a host computer; Any one of the plurality of leveling probes is mounted on a probe card; each of the leveling probes is connected to a corresponding first input terminal of the circuit continuity detection chip; the second input terminal of the circuit continuity detection chip is connected to a first terminal of the power supply; the second terminal of the power supply is connected to a chuck; and the circuit continuity detection chip is connected to a communication terminal of the host computer. When the height of each first input terminal of the circuit continuity detection chip changes simultaneously at each lifting height of the chuck until the corresponding leveling probe contacts the chuck, the circuit continuity detection chip is activated. When the height difference between the first lifting height corresponding to the first activated first input terminal and the second lifting height corresponding to the last activated first input terminal is less than a preset height difference, the host computer determines that the chuck and the probe card are parallel to each other.

2. The leveling and detection circuit for chuck and probe card as described in claim 1, characterized in that, The power supply is a wafer test low-voltage source meter, which is used to provide low-voltage power to the circuit where the first input terminal of the circuit continuity detection chip is located, or to provide low-voltage power to the circuit composed of the probe card and the wafer when performing wafer low-voltage testing.

3. The leveling and detection circuit for chuck and probe card as described in claim 2, characterized in that, It also includes a control switch board; The first power supply terminal of the control switch board is connected to each of the second input terminals of the circuit continuity detection chip, the second power supply terminal is connected to the chuck, the first power supply terminal is connected to the first output terminal of the wafer test low voltage source meter, and the second power supply terminal is connected to the second output terminal of the wafer test low voltage source meter, for closing the circuit between the circuit continuity detection chip, the wafer test low voltage source meter, and the chuck.

4. The leveling and detection circuit for chuck and probe card as described in claim 3, characterized in that, It also includes high-voltage isolation circuits; Each first input terminal of the high-voltage isolation circuit is connected to each of the leveling probes, and each second input terminal is connected to each of the first input terminals of the circuit continuity detection chip, for use in turning off during wafer low-voltage testing and wafer high-voltage testing, and in turning on during the leveling detection of the chuck and the probe card. The third power supply terminal of the control switch board is connected to the first output terminal of the wafer test high voltage source meter, and the fourth power supply terminal is connected to the second output terminal of the wafer test high voltage source meter. It is also used to close in a first mode during wafer low voltage testing to close the circuit composed of the probe card, the wafer, and the wafer test low voltage source meter; to close in a second mode during wafer high voltage testing to close the circuit composed of the probe card, the wafer, and the wafer test high voltage source meter; and to close in a third mode during the leveling test of the chuck and the probe card to close the circuit between the circuit continuity detection chip, the wafer test low voltage source meter, and the chuck.

5. The leveling and detection circuit for chuck and probe card as described in claim 4, characterized in that, The high-voltage isolation circuit includes multiple high-voltage disconnect switches. The first terminal of each high-voltage disconnect switch is a first input terminal of the high-voltage isolation circuit, the second terminal of each high-voltage disconnect switch is a second input terminal of the high-voltage isolation circuit, and the control terminal of each high-voltage disconnect switch is a control terminal of the high-voltage isolation circuit.

6. The leveling and detection circuit for chuck and probe card as described in claim 5, characterized in that, The high-voltage disconnect switch is an NMOS.

7. The leveling and detection circuit for chuck and probe card as described in claim 4, characterized in that, The high-voltage isolation circuit includes multiple contacts of a relay and the coil of the relay; The first end of each of the contacts is a first input terminal of the high-voltage isolation circuit, and the second end of each of the contacts is a second input terminal of the high-voltage isolation circuit. The coil of the relay is energized during the leveling test of the chuck and the probe card, thereby causing the coil of the relay to attract the contacts of the relay.

8. The leveling and detection circuit for chuck and probe card as described in claim 7, characterized in that, The high-voltage isolation circuit also includes a high-voltage isolation control chip; The output terminal of the high-voltage isolation control chip is connected to the coil of the relay, and is used to control the coil of the relay to be energized when the chuck and the probe card are being leveled and tested, so that the coil of the relay will attract the contacts of the relay.

9. The leveling and detection circuit for chuck and probe card as described in any one of claims 1-8, characterized in that, It also includes multiple indicator lights, each of which corresponds one-to-one with each of the leveling probes; The indicator light is connected between the corresponding leveling probe and the first input terminal of the corresponding circuit continuity detection chip, and is used to light up when the first input terminal of the corresponding circuit continuity detection chip is turned on.

10. A wafer aging test system, characterized in that, Includes the leveling and detection circuit for chuck and probe card as described in any one of claims 1-9.

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