Bridged chip die, memory device and electronic system

Abstract

A bridge chip die, a memory device and an electronic system are provided. The provided bridging chip crystal grain is used for connecting at least one DRAM chip crystal grain; wherein the bridging chip crystal grain is used for being integrated with the at least one DRAM chip crystal grain through 3D packaging; the bridging chip crystal grain comprises one or more UCIe interfaces, a plurality of DRAM (Dynamic Random Access Memory) controllers, a Cache controller and an SRAM (Static Random Access Memory); each of the plurality of DRAM controllers is used for accessing a corresponding DRAM block; each of the plurality of DRAM controllers comprises a 3D DRAM interface; when the main plane of the bridging chip crystal grain is attached to the main plane of the first DRAM chip crystal grain in the at least one DRAM chip crystal grain, the 3D DRAM interface of each DRAM controller is correspondingly connected with the DRAM interface of each DRAM block of the first DRAM chip crystal grain; and the Cache controller and the SRAM are used as the Cache of the at least one DRAM chip crystal grain.

Description

Technical Field

[0001] This application relates to the field of integrated circuit chips, and more specifically, to external storage solutions based on 3D-DRAM. Background Technology

[0002] Generally, when a chip requires high-performance, high-capacity external storage, a DDR controller is used to connect to the memory chip. The DDR controller interacts with the memory chip according to the DDR protocol. The current DDR protocol has been released up to DDR5, with frequencies reaching up to 6400MHz or even higher. Taking a DDR5 DIMM as an example, it is a 32-bit dual-channel specification. The corresponding total bandwidth is 32b x 6.4G x 2 = 4 x 6.4 x 2 = 51.2GB per second. To support even higher bandwidth, the latest GDDR technology can be selected, which can achieve even higher frequencies and bandwidths.

[0003] A high-performance SOC chip often integrates one or more DDR controllers to meet higher bandwidth requirements.

[0004] Figure 1 This demonstrates a logic chip containing eight dual-channel DDR5 controllers. Since DDR memory also typically exists in chip form, the term "logic chip" is used here to distinguish it from DDR memory chips. Figure 1 The logic chip includes eight DDR controllers (showing bit controller 1 to controller 8). Each DDR controller is connected to a corresponding DDR4 memory chip.

[0005] Increasing the number of DDR controllers in a logic chip increases its usable storage capacity and bandwidth. However, in traditional 2D logic chips, the number of DDR controllers is limited by the chip's area and pin count. Furthermore, the connection method between the DDR controller and the DRAM chip is restricted, meaning the DDR controller can only be connected from the side of the logic chip, limiting the number of pins the logic chip can provide for the DDR controller. Increasing the logic chip's area and pin count significantly increases its cost, leading to a decline in its market competitiveness.

[0006] 3D-DRAM is a memory product form proposed to solve the above problems. It uses 3D packaging technology to bond two or more chips in a direction perpendicular to the main plane of the chip, forming a chip that simultaneously includes logic chip chips and DRAM chip chips. This allows logic chip chips and DRAM chip chips to be connected from a higher dimension. Furthermore, the short spacing between the two chips eliminates the need for PHY (physical layer interface circuit) or I / O circuits with strong driving capabilities, thus reducing implementation costs. Even if core voltage conversion is required, only optional voltage conversion circuitry needs to be added.

[0007] Figure 2A This is a schematic diagram showing the combination of DRAM chip chips and logic chip chips.

[0008] For example, several 256-bit, 400MHz interfaces are reserved on the DRAM chip die. Figure 2A Each DRAM block corresponds to such an interface. The DRAM chip die and the logic chip die are directly bonded via surface contact (e.g., connected via TSV). Because they are surface contacts, the number of pins that can be connected is far greater than the number of pins in traditional 2D structure connection methods. For example, implementing 64 such interfaces (each interface 256 bits) on an area of ​​100mm^2 can achieve a bandwidth of 256b x 400MHz x 64 = 32B x 0.4G x 64 = 12.8 x 64 GBps = 819.2 GBps. This is equivalent to the bandwidth provided by 16 of the aforementioned 32b x 6.4G x 2 DDR5 controllers.

[0009] Figure 2B A schematic diagram of the main plane of a logic chip die is shown.

[0010] Figure 2B Each light-colored square represents a region corresponding to one DRAM block after bonding. Each light-colored square also includes an interface location represented by dark-colored squares, used for connecting to the corresponding 256-bit interface of the DRAM block. This can be understood as... Figure 2B The light-colored squares do not necessarily represent the circuit layout within the logic chip that needs to be divided into square areas, but the interface locations represented by the dark-colored squares have pins for interface circuits used to communicate with the DRAM block, so the wiring of the circuit within the logic chip is affected by the interface circuits.

[0011] exist Figure 2A and Figure 2B In the demonstrated 3D DRAM solution, the 3D packaged DRAM format greatly limits the design flexibility of the logic chip:

[0012] 1. Logic chip chips require a large area ( Figure 2B The dark areas are used to connect to the low-speed 3D-DRAM interface, which results in a low memory bandwidth density.

[0013] 2. At the same time, the fixed position of the interface restricts the layout and routing of the logic chip, thereby reducing the area utilization of the logic chip and limiting the routing method of the logic chip.

[0014] 3. 3D packaging technology is required to package the logic chip and DRAM chip together, which results in additional cost increases;

[0015] 4. 3D packaging technology requires that the logic chip die and the DRAM chip die have the same area; that is, the area of ​​the logic chip die must be an integer multiple (usually 2) of the area of ​​the DRAM block. N The relationship is (times) to (the number of times). This limits the area specifications of logic chip chips.

[0016] 5. Because the logic chip die and the DRAM chip die have a fixed area ratio, it means that when the area of ​​the logic chip die is fixed, the capacity of the DRAM that can be used is also relatively fixed, which limits the flexibility of the overall system.

[0017] Each DRAM block in 6.3D-DRAM requires a controller, repair circuit, power supply circuit, etc. in the logic chip, which also consumes a considerable amount of logic chip die area.

[0018] To address the aforementioned issues, a 3D DRAM with a buffer chip die was proposed.

[0019] Figure 3A This is a schematic diagram of a 3D DRAM with a buffer chip die. The buffer chip die is used to connect the logic chip to one or more DRAM chip dies in a 3D package. The buffer chip die integrates the DRAM controller, repair circuitry, etc., so this part of the circuitry is no longer provided by the logic chip die, simplifying the logic chip die design, reducing the area occupied by the interface circuitry accessing the DRAM within the logic chip die, and also reducing the contact area between the logic chip die and the buffer chip die. The buffer chip die is also bonded to the logic chip via core voltage.

[0020] In this way, the buffer chip die can isolate the DRAM control logic, be responsible for DRAM maintenance and repair, and only expose a relatively simple and high-speed interface to the logic chip die.

[0021] Figure 3B A schematic diagram of the main plane of the buffer chip die is shown.

[0022] Figure 3B Each light red square represents the region corresponding to one DRAM block after bonding. Each light red square also includes an interface location represented by a dark purple square, used to connect to the 256-bit interface of the corresponding DRAM block (these interfaces do not need to be connected to the logic chip die). Figure 3B The green area in the diagram represents the interface location on the buffer chip die used to connect to the logic chip.

[0023] Figure 3C A schematic diagram of the main plane of a logic chip die is shown.

[0024] Figure 3C The logic chip die in it is Figure 3A and Figure 3B The logic chip die in the process. Figure 3C In the diagram, the green area represents the logic chip die used for interconnection. Figure 3B The interface location of the buffer chip die. Therefore, in Figures 3A-3C In 3D DRAM with buffer chip dies, the area occupied by the interface on the logic chip die for accessing the DRAM memory is significantly reduced, allowing a larger proportion of the logic chip die's area to be used for implementing the logic chip's circuitry. Logic chips include, for example, CPUs, GPUs, and SoCs. Even when packaging more or fewer DRAM chip dies in 3D DRAM, there is no need to change the logic chip die or increase or decrease the area of ​​the interface connecting the logic chip die and the buffer chip die. This allows for a more economical and convenient way to expand 3D DRAM for the logic chip die.

[0025] There are other forms of chip-level high-speed, high-capacity DRAM storage solutions.

[0026] Figure 4 A schematic diagram of HBM (High Bandwidth Memory) is shown.

[0027] HBM is another type of high-performance DRAM memory based on 3D packaging. HBM is defined in the international standard JESD235 (https: / / www.jedec.org / standards-documents / docs / jesd235a). Figure 3A The demonstrated storage solution is similar, with HBM integrating multiple DRAM chip dies in a 3D package. These DRAM chip dies are vertically connected to microbumps via TSVs. HBM may also include an interface chip die (referred to as Base Logic in the HBM specification) that is vertically connected to the DRAM chip dies and located at the bottom layer.

[0028] The interface chip die can integrate a DRAM controller and can also provide functions such as ECC and DRAM repair.

[0029] The interface chip die may not integrate a DRAM controller; instead, the DRAM controller is provided by the logic chip die that accesses the HBM.

[0030] HBMs include physical layer circuitry (PHYs) for connecting to the corresponding physical layer circuitry (PHYs) of the logic chip. Because of the PHYs, the connection between the HBM and the logic chip can be routed via interposers, allowing the HBM and logic chip to be arranged at different horizontal positions without 3D stacking. This provides greater flexibility in designing the logic chip without requiring 3D packaging. HBMs and logic chips can also be connected to each other via traces on the package substrate.

[0031] More general-purpose die-to-die interconnects (such as Die Link, UCIe, etc.) can also be used to connect logic chip dies and DRAM chip dies.

[0032] from Figures 1 to 4 The storage solutions represent an evolutionary process of problem-solving. Figures 3A-3C The remaining technical problems in storage solutions are:

[0033] 1. While using a buffer chip die solves the problem of occupying logic chip die area as shown in Figure 2, it requires a die with the same area as the DRAM chip die to implement the cache chip die. There may be some wasted area on this cache chip die.

[0034] 2. It also needs to be combined with logic chips through hybrid bonding, which requires additional costs.

[0035] 3. For logic chips, there are still limitations on the fixed position of the interface circuit on the chip die, and the area of ​​the logic chip die and the area between the DRAM chip die need to be the same, which will cause some waste.

[0036] for Figure 4 Compared to HBM storage solutions, Figures 3A-3CThe storage solutions used in traditional methods suffer from relatively high access latency and narrow bandwidth (due to the relatively small area and number of interface circuits). However, the HBM protocol itself is highly complex and costly to implement. For example, HBM needs to support a multi-channel architecture, with each channel operating independently and accessing its corresponding DRAM chip die, requiring a large number of interface signals. The physical layer circuitry (PHY) of HBM is also expensive, needing to support extremely high transmission rates (e.g., 6.4Gbps for HBM3) and the signal integrity requirements necessary for transmitting signals across intercalation boards / polarity plates. The HBM protocol also specifies complex initialization and training processes, as well as various operation commands, requiring not only DRAM read / write capabilities but also DRAM testing and management capabilities. Therefore, the DRAM controller on the logic die used to access HBM still requires a relatively large area and is implemented at a high IP cost.

[0037] To address the technical challenges of HBM memory solutions, Chinese patent CN117222234B proposes inserting a joint die between the HBM memory and the SoC module. The joint die includes both HBM interface circuitry and UCIe interface circuitry, acting as a bridge between the SoC module and the HBM memory. The SoC module accesses the HBM memory via the joint die through the UCIe interface, eliminating the need for the SoC module itself to integrate the expensive HBM interface circuitry. However, from an overall perspective, integrating the HBM interface circuitry on both the HBM memory and the joint die does not reduce the overall cost. Utility Model Content

[0038] To address the shortcomings of existing technologies, this application aims to provide a bridge chip that connects 3D DRAM and logic chips such as GPUs / CPUs / SoCs. By replacing the HBM interface with the bridge chip, the logic chip no longer needs to integrate HBM interface circuitry and a DRAM controller, nor does it need to handle DRAM management tasks or integrate them through 3D packaging, thereby reducing the cost of the logic chip while maintaining high memory performance. The bridge chip provides the logic chip with a randomly accessible memory address space, allowing the logic chip to use 3D DRAM in the same way as SRAM, further simplifying the complexity of the logic chip. It also reduces the latency of the logic chip accessing 3D DRAM by supporting cache mode and easily expands the bandwidth for accessing 3D DRAM.

[0039] According to a first aspect of this application, a bridge chip die is provided for connecting at least one DRAM chip die; wherein each of the at least one DRAM chip die includes a plurality of DRAM blocks, and the bridge chip die is integrated with the at least one DRAM chip die via 3D packaging; the bridge chip die includes one or more UCIe interfaces, a plurality of DRAM controllers, a cache controller, and SRAM; each of the plurality of DRAM controllers is used to access a corresponding DRAM block, and the DRAM blocks corresponding to different DRAM controllers are different from each other; each of the plurality of DRAM controllers includes a 3D DRAM interface, the 3D DRAM interface occupying a designated position on the main plane of the bridge chip die for connecting the corresponding DRAM block; when the main plane of the bridge chip die is aligned with the main plane of a first DRAM chip die among the at least one DRAM chip die, the 3D DRAM interface of each DRAM controller is correspondingly connected to the DRAM interface of each DRAM block of the first DRAM chip die; the cache controller and the SRAM serve as the cache of the at least one DRAM chip die, and the SRAM serves as a cache row of the cache controller.

[0040] A bridge chip die according to a first aspect of this application is provided, further comprising a first bus; each of the one or more UCIe interfaces is connected to the cache controller; the cache controller is connected to the plurality of DRAM controllers via the first bus; each of the one or more UCIe interfaces provides a received memory access request to the cache controller; the cache controller accesses any one of the plurality of DRAM controllers via the first bus.

[0041] A bridge chip die according to a first aspect of this application is provided, including a first bus, a plurality of UCIe interfaces, and a plurality of cache controllers; each of the plurality of cache controllers is connected to one of the plurality of UCIe interfaces; each of the plurality of cache controllers has a cache line; the memory spaces accessible to the plurality of UCIe interfaces at least partially overlap; each cache controller and its cache line serve as a cache of the memory space accessible to the UCIe interface to which it is connected; the plurality of cache controllers are all connected to the plurality of DRAM controllers via the first bus; the bridge chip die further includes circuitry for processing consistency; the circuitry for processing consistency maintains consistency between the caches of the plurality of UCIe interfaces.

[0042] A bridge chip die according to the first aspect of this application is provided, which further includes a second bus and a plurality of cache controllers; the one or more UCIe interfaces are connected to the second bus; the plurality of cache controllers are connected to the second bus; and the plurality of cache controllers correspond one-to-one with the DRAM controller.

[0043] A bridging chip die according to the first aspect of this application is provided, including a first UCIe interface and a second UCIe interface; the memory spaces accessible by memory space access requests received from the first UCIe interface and the second UCIe interface are the same, different or partially overlapping.

[0044] A bridge chip die according to a first aspect of this application is provided, including a plurality of UCIe interfaces; each of the plurality of UCIe interfaces is used to connect to a logic chip or other bridge chip dies.

[0045] A bridge chip die according to a first aspect of this application is provided, wherein the 3D DRAM interface is located in the edge region of the main plane of the bridge chip die; the one or more UCIe interfaces are located in the edge region of the main plane of the bridge chip die that is not occupied by the 3D DRAM interface; and the cache controller and the SRAM are located in the region of the main plane of the bridge chip die that is not occupied by the 3D DRAM interface and the one or more UCIe interfaces.

[0046] A bridge chip die according to a first aspect of this application is provided, wherein the 3D DRAM interface is located in the edge region of the main plane of the bridge chip die; the one or more UCIe interfaces are located in the edge region of the main plane of the bridge chip die not occupied by the 3D DRAM interface; the second bus is located in the central region of the main plane of the bridge chip die; and the cache controller and the SRAM are located between the region of the main plane of the bridge chip die occupied by the second bus and the region occupied by the 3D DRAM interface.

[0047] According to a second aspect of this application, a storage device is provided, including a bridge chip die and at least one DRAM chip die; the bridge chip die and the at least one DRAM chip die are integrated together by 3D packaging; the bridge chip die is the bridge chip die according to the first aspect of this application.

[0048] According to a third aspect of this application, an electronic system is provided, including a first storage device and a second storage device; the first storage device and the second storage device are respectively storage devices according to a second aspect of this application; the first storage device and the second storage device are connected to the UCIe port of the bridge chip of the second storage device through the UCIe port of the bridge chip of the first storage device. Attached Figure Description

[0049] When read in conjunction with the accompanying drawings, and by referring to the following detailed description of illustrative embodiments, this application, its preferred modes of use, and further objects and advantages will be best understood, wherein the drawings include:

[0050] Figure 1 This demonstrates a logic chip containing eight dual-channel DDR5 controllers.

[0051] Figure 2A This is a schematic diagram showing the combination of DRAM chip chips and logic chip chips.

[0052] Figure 2B A schematic diagram of the main plane of a logic chip die is shown.

[0053] Figure 3A This is a schematic diagram of a 3D DRAM with a buffer chip die.

[0054] Figure 3B A schematic diagram of the main plane of the buffer chip die is shown.

[0055] Figure 3C A schematic diagram of the main plane of a logic chip die is shown.

[0056] Figure 4 A schematic diagram of HBM (High Bandwidth Memory) is shown.

[0057] Figure 5A A schematic diagram illustrating the bridging chip die, bridging logic chip die, and DRAM chip die of an embodiment of this application is shown.

[0058] Figure 5B A structural block diagram of the bridging chip die according to an embodiment of this application is shown.

[0059] Figure 6 A schematic diagram illustrating a bridging chip die bridging a logic chip die and a DRAM chip die according to another embodiment of this application is shown.

[0060] Figure 7A A schematic diagram showing the layout of the main plane of a DRAM chip die according to an embodiment of this application is provided.

[0061] Figure 7B Showing with Figure 7A A schematic diagram of the layout of the main plane of the DRAM chip die corresponding to the bridge chip die.

[0062] Figure 7C Another embodiment of the same Figure 7A A schematic diagram of the layout of the main plane of the DRAM chip die corresponding to the bridge chip die.

[0063] Figure 8A A structural block diagram of a bridging chip die according to another embodiment of this application is shown.

[0064] Figure 8B A structural block diagram of a bridging chip die according to another embodiment of this application is shown.

[0065] Figure 8C A block diagram of an application system based on a bridging chip die according to yet another embodiment of this application is shown.

[0066] Figure 9A A structural block diagram of a bridging chip die according to another embodiment of this application is shown.

[0067] Figure 9B A structural block diagram of a bridging chip die according to another embodiment of this application is shown.

[0068] Figure 9C Showing Figure 9A A schematic diagram of the layout of the DRAM chip die main plane used in the / 9B embodiment.

[0069] Figure 9D Showing with Figure 9C A schematic diagram of the layout of the main plane of the DRAM chip die corresponding to the bridge chip die.

[0070] Figure 9E A flowchart illustrating the read request processing of a bridge chip die according to yet another embodiment of this application is shown.

[0071] Figure 9F A schematic diagram showing the layout of the main plane of a DRAM chip die according to another embodiment of this application is provided.

[0072] Figure 9G Showing with Figure 9F A schematic diagram of the layout of the main plane of the DRAM chip die corresponding to the bridge chip die.

[0073] Figure 10A A 3D-packaged storage device according to an embodiment of this application is shown.

[0074] Figure 10B A chip demonstrating the full functionality according to an embodiment of this application is shown.

[0075] Figure 11A block diagram of an electronic system comprising a bridging chip die according to another embodiment of this application is shown.

[0076] Figure 12 A block diagram of an electronic system composed of a bridging chip die, according to yet another embodiment of this application, is shown.

[0077] Figure 13 A block diagram of an electronic system constructed from a bridging chip die, according to another embodiment of this application, is shown. Detailed Implementation

[0078] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0079] Figure 5A A schematic diagram illustrating the bridging chip die connecting the logic chip die and the DRAM chip die according to an embodiment of this application is shown.

[0080] In this embodiment, the bridge chip die and the DRAM chip die are integrated together through 3D packaging, and a die interface such as a UCIe interface is provided externally. External chips or logic chip dies (e.g., GPU, CPU, and / or SoC) access the bridge chip die through the UCIe interface. The bridge chip die presents itself as a memory device or SRAM device to the logic chip die, without requiring the logic chip die to integrate a DRAM controller.

[0081] The bridging chip includes a DRAM controller that utilizes the DRAM chip as the storage medium. The DRAM controller of the bridging chip connects to the DRAM chip via a TSV, eliminating the need to implement an HBM PHY or support the full range of operational commands specified by the HBM protocol. This reduces the complexity and cost of the bridging chip. Optionally, the bridging chip also provides translation between the UCIe address space and the DRAM addresses used by the DRAM chip. Multiple DRAM chips can be used to provide various storage capacities.

[0082] The logic chip and bridge chip are connected via a UCIe interface, allowing the logic chip's area to be any size, unrestricted by the bridge chip's area. The logic chip can be packaged together with the bridge chip and DRAM chip within a single chip, but this is not mandatory. Therefore, the logic chip's packaging method is not limited by 3D packaging.

[0083] Figure 5B A structural block diagram of the bridging chip die according to an embodiment of this application is shown.

[0084] See Figure 5B The bridge chip includes a UCIe interface, a cache controller, a bus and DRAM controller, and an optional management interface. The management interface, such as a serial port, is used to configure the bridge chip to operate in cache mode or SRAM mode.

[0085] A bridging chip may include one or more UCIe interfaces. More UCIe interfaces represent higher data transfer bandwidth. Therefore, logic chips can easily achieve higher memory access performance by connecting to the bridging chip via more UCIe interfaces. Optionally, multiple logic chips can be connected to different logic chips via different UCIe interfaces. Each of the multiple logic chips can access the same or different memory spaces provided by the bridging chip.

[0086] The cache controller, which bridges the DRAM chip, acts as a cache for the DRAM chip to optimize DRAM access performance. The cache controller also includes SRAM as a cache line or a cache for DRAM. The cache controller identifies whether a memory access request from the UCIe interface has a hit. If a hit occurs, the accessed SRAM is used to respond to the memory access request; otherwise, the DRAM chip is accessed through the DRAM controller to respond to the memory access request. The implementation principle of the cache controller is existing technology.

[0087] In this embodiment, the cache controller provides either cache mode or SRAM mode. The operating mode of the cache controller can be set or changed through the management interface.

[0088] In Cache mode, the Cache controller acts as a cache for the DRAM chip die. The storage space provided by the bridging chip die to the logic chip die can be the sum of the storage space provided by all DRAM chip dies. For memory access requests from the logic chip die, the memory access performance experienced by the logic chip die differs when the cache hits and misses.

[0089] In SRAM mode, the DRAM die does not need to operate. The cache controller simply provides its SRAM to the logic die as accessible storage space. The size of the storage space provided by the bridge die to the logic die can be equal to the size of the SRAM. The cache controller directly maps received memory access requests to SRAM access requests based on the access address. The cache controller does not need to handle cache hits. For memory access requests from the logic die, the memory access performance experienced by the logic die is almost identical across the entire address space provided by the bridge die, and is superior to the performance provided by cache mode. In SRAM mode, the DRAM die can be turned off to reduce power consumption.

[0090] Optionally, the cache controller also provides a hybrid mode. In hybrid mode, the cache controller uses a portion of the SRAM as cache lines for the DRAM die, while providing a portion of the SRAM directly as accessible memory. This bridges the die to provide a hybrid memory space, where a portion of the address space (the memory space directly provided by the SRAM) has stable high read / write performance, while the remaining address space (provided by the DRAM die and the SRAM used as cache lines) has large storage capacity and high read / write performance upon cache hit.

[0091] Alternatively, the cache controller can provide another hybrid mode. In this mode, there are no cache lines; all SRAM provides high-performance, accessible storage, while the DRAM die provides large-capacity storage. Both storage components coexist and can be accessed in parallel.

[0092] The cache controller is connected to the DRAM controller via a bus. The bridge die includes one or more DRAM controllers. The number of DRAM controllers is, for example, equal to the number of DRAM blocks in the DRAM die. Figure 5B The diagram illustrates four DRAM controllers and four corresponding DRAM blocks. Each DRAM controller corresponds one-to-one with a DRAM block. Optionally, when multiple DRAM chips are connected via a bridging chip, the DRAM chips are generally identical and have the same number of DRAM blocks. The number of DRAM controllers is the same as the number of DRAM blocks in, for example, a single DRAM chip. This allows DRAM blocks located at the same horizontal position across multiple DRAM chips to share the same DRAM controller, reducing the overall number of DRAM controllers. Optionally, separate DRAM controllers are provided for different DRAM blocks of different DRAM chips to maximize DRAM access bandwidth.

[0093] When the cache controller operates in cache mode, the entire address space provided by the bridge chip die is mapped to the memory space provided by each DRAM block. Based on the memory access request received from the UCIe interface, the cache controller translates the memory address to be accessed into an address for the DRAM block, and then accesses the corresponding DRAM block via the bus with the corresponding DRAM controller. Each DRAM controller occupies a different address space on the bus, and the cache controller distinguishes between the different DRAM controllers to be used based on their addresses.

[0094] Requests from the logic chip are sent to the cache controller. The cache controller determines whether the current request is in the cache. If it is, it returns the data directly. Otherwise, it reads the data from the DRAM, saves it to the cache, and returns it to the logic chip.

[0095] In one implementation, Figure 5B The bridging chip's various UCIe ports share a cache controller and all cache lines provided by the cache controller's SRAM space. This is suitable for applications where the logic chip chips connected to each UCIe port share data. The cache controller does not differentiate between memory access requests from each UCIe port; instead, it uses a uniform method to identify cache hits in the SRAM and then accesses the DRAM chip chip if necessary. However, when the data accessed by each UCIe interface is significantly different, the shared cache controller approach leads to frequent cache line replacements, impacting storage performance. By reserving dedicated SRAM space (cache lines) for each UCIe port, the number of cache line replacements can be reduced.

[0096] In an alternative implementation, the management interface is, for example, an SPI or I2C interface. Alternatively, the bridge chip die may not include a management interface, but instead be configured by accessing registers in the configuration space of the UCIe interface.

[0097] Optionally, the bridging die may also include circuitry for scanning, detecting, and / or repairing manufacturing defects in the DRAM die. Information regarding DRAM die defects obtained through scanning and detection can be reported to the logic die. The bridging die may also load repair information for the DRAM die and perform repair operations on it. Optionally, the bridging die may also include verification circuitry, such as one or more ECC circuits, to add verification data to data written to the DRAM / SRAM and to verify data read from the DRAM / SRAM to detect and identify erroneous bits in the stored data.

[0098] Figure 6 A schematic diagram illustrating a bridging chip die bridging a logic chip die and a DRAM chip die according to another embodiment of this application is shown.

[0099] same Figure 5A Compared to the previous embodiment, Figure 6 The bridge chip die includes two UCIe interfaces, and correspondingly, the logic chip die also includes two UCIe interfaces. The two UCIe interfaces of the logic chip die are connected to the two UCIe interfaces of the bridge chip die. If a single UCIe interface can provide a maximum bandwidth of 32Gbps, combining the two UCIe interfaces can achieve a memory access bandwidth of 64Gbps. It can be understood that there can be many channels between the bridge chip die and the DRAM chip die (shown as...). Figure 6 The bridge chip connects the DRAM chip die and the bridge chip die (multiple bidirectional arrows, for example, dozens), thus the data transmission bandwidth between the bridge chip die and the DRAM chip die can be much greater than the bandwidth provided by a single UCIe interface. Therefore, in this embodiment, the bridge chip die can provide a greater number of UCIe interfaces without wasting bandwidth.

[0100] Figure 6 In this example, the logic chip die can access the same or different memory spaces through two UCIe interfaces. This allows different circuits within the logic chip die to use their own memory spaces without interfering with each other, or to share memory spaces. This is achieved by configuring the cache controller (see also...). Figure 5B Configure the storage space range provided by each UCIe interface.

[0101] Figure 7A A schematic diagram showing the layout of the main plane of a DRAM chip die according to an embodiment of this application is provided.

[0102] A DRAM chip die consists of multiple DRAM blocks, and each DRAM block has a corresponding DRAM interface. Figure 7A In this embodiment, the interface of the DRAM block is disposed along the edge of the DRAM chip die, while the interface of the DRAM block is avoided inside the DRAM chip die. Optionally, multiple Figure 7A DRAM chip dies can be 3D stacked in a direction perpendicular to the main plane.

[0103] Figure 7B Showing with Figure 7A A schematic diagram of the layout of the main plane of the DRAM chip die corresponding to the bridge chip die.

[0104] Figure 7B The bridging chip die is used to connect with Figure 7A The DRAM chip chips are bonded together, with the main planes of the two chips facing each other during bonding. Figure 7BThe dashed box in the middle shows Figure 7A The corresponding location of the DRAM block.

[0105] The DRAM interface (and optional DRAM controller) is set at the edge of the bridging chip die. When the bridging chip die and the DRAM chip die are attached, the DRAM interfaces of the respective dies are opposite each other and can be connected through TSV.

[0106] The edge of the bridging chip die that is not occupied by the DRAM interface is provided with a UCIe interface to facilitate the connection of leads to the UCIe interface of other chips or dies. Figure 7B The image shows two UCIe interfaces (UCIe interface 0 and UCIe interface 1).

[0107] The central area of ​​the bridge chip die (the area not occupied by the DRAM interface and UCIe interface) can be used to house the cache controller (and its SRAM), bus, and other circuitry. This provides sufficient area within the bridge chip die to accommodate SRAM and enable a large capacity of SRAM.

[0108] Preferably, the cache controller / SRAM is located in the middle area of ​​the bridge chip, while the bus is positioned relatively close to the DRAM interfaces, allowing the cache controller to access each DRAM interface and thus the DRAM blocks via the bus. UCIe interface 0 / 1 is located near the cache controller / SRAM, facilitating the transmission of memory access requests received from the UCIe interfaces to the cache controller. Each UCIe interface can share the cache controller, or the cache controller's resources can be allocated to serve different UCIe interfaces.

[0109] Figure 7C Another embodiment of the same Figure 7A A schematic diagram of the layout of the main plane of the DRAM chip die corresponding to the bridge chip die.

[0110] same Figure 7B Compared to the bridging chip die, Figure 7C In this configuration, the bridge chip die includes a greater number (4) of UCIe interfaces (shown as UCIe0, UCIe1, UCIe2, and UCIe3). All four UCIe interfaces are located at the edge of the bridge chip die (in locations not occupied by DRAM interfaces) and are close to the bus.

[0111] Figure 7C The document also demonstrates two logic chips (logic chip 0 and logic chip 1) connected to a bridge chip chip via a UCIe interface. Each of the two logic chip chips includes, for example, one UCIe interface, which is connected to a corresponding UCIe interface of the bridge chip chip.

[0112] Figure 8A A structural block diagram of a bridging chip die according to another embodiment of this application is shown.

[0113] same Figure 5B Compared to the bridging chip die, Figure 8A In one embodiment, multiple cache controllers are included (shown as cache controller 0 with SRAM0 and cache controller 1 with SRAM1). Cache controller 0 serves memory access requests from UCIe interface 0, while cache controller 1 serves memory access requests from UCIe interface 1.

[0114] In one implementation, the logic chip accesses different memory spaces through UCIe interface 0 and UCIe interface 1, respectively. Accordingly, Cache controller 0 uses SRAM 0 as a cache line and accesses the DRAM blocks providing the memory space using DRAM controller 0 and DRAM controller 1. DRAM controller 0 accesses DRAM block 0, DRAM controller 1 accesses DRAM block 1, and so on, with a one-to-one correspondence between DRAM controllers and DRAM blocks. In this implementation, the cache resources of the bridging chip die are divided according to the UCIe interface, with each UCIe port having its own dedicated cache resources. Therefore, access requests and data transfers on one UCIe port do not affect the performance of other UCIe ports. However, the memory space available to each UCIe port is limited, and it cannot use all of the memory space.

[0115] In another implementation, each UCIe port still corresponds to a separate cache controller, but each cache controller can use all DRAM controllers and manage all DRAM blocks. Circuitry for handling consistency is also provided between the cache controllers, such as circuitry implementing the MESI protocol based on a consistency directory. Through the consistency directory, for memory access requests received by the cache controllers, it is also checked whether the data to be accessed is being managed by other cache controllers, and data is synchronized between the SRAMs of each cache controller if necessary. This implementation introduces additional overhead for handling consistency, but allows each UCIe interface to access the full memory space provided by all DRAM blocks. Figure 8A In this system, each controller can connect to all DRAM controllers via a bus, thereby accessing the DRAM block corresponding to any DRAM controller.

[0116] Figure 8B A structural block diagram of a bridging chip die according to another embodiment of this application is shown.

[0117] exist Figure 8BIn this embodiment, the two UCIe interfaces of the bridging chip die are connected to two CPUs (denoted as CPU0 and CPU1), respectively. CPU0 includes its own cache (denoted as L1 Cache0), and CPU1 includes its own cache (L1 Cache1). The bridging chip die in this embodiment can serve as the LLC (last level cache) for CPU0 and CPU1, and together with the DRAM chip die, constitute a large-capacity memory for CPU0 and CPU1. The bridging chip die in this embodiment can also operate in SRAM mode, providing SRAM storage space for CPU0 and CPU1 without using a DRAM chip die.

[0118] The bridging chip die in this embodiment does not handle the consistency issues between the L1 Cache0 and L1 Cache1 of the CPU it is connected to, nor does it monitor operations or data transfers occurring between L1 Cache0 and L1 Cache1, thereby reducing the complexity of the bridging chip die itself. Regarding consistency handling, the bridging chip die in this embodiment at most maintains the consistency of the cache lines of Cache Controller 0 and Cache Controller 1. In an optional embodiment, the bridging chip die also maintains the consistency between Cache Controller 0 and Cache Controller 1, while completely delegating consistency-related operations to the logic chip it is connected to.

[0119] exist Figure 8A and Figure 8B In this embodiment, a cache controller is provided at the UCIe entry point. The advantage is that it provides better access latency control, but the disadvantage is that different UCIe interfaces may require their own cache controllers to perform consistency operations. Figure 9A In the embodiments described, the need for consistency operations is further eliminated.

[0120] Figure 8C A block diagram of an application system based on a bridging chip die according to yet another embodiment of this application is shown.

[0121] exist Figure 8C In this embodiment, the two UCIe interfaces of the bridging chip die are connected to two CPU chips (denoted as CPU chip 0 and CPU chip 1), respectively. Each CPU chip includes two CPU cores (denoted as CPU core 0 and CPU core 1). Each CPU core has its own L1 cache, and the two CPU cores within the CPU chip share an L2 / L3 cache. The CPU chip also includes, for example, a PCIe CXL interface for interacting with other devices.

[0122] The L1 Cache, L2 Cache, and L3 Cache inside the CPU chip belong to the same consistency domain.

[0123] Figure 8C The bridging chip die in this embodiment can provide cache functionality for both CPU chip 1 and CPU chip 2 as an LLC (Last Level Cache). However, the LLC provided by the bridging chip die belongs to a different consistency domain than the internal cache system of the CPU chip, and the bridging chip die does not provide consistency services between CPU chip 1 and CPU chip 2. Therefore, the bridging chip die is the LLC of both CPU chip 1 and CPU chip 2. However, if CPU chip 1 and CPU chip 2 access the overlapping portion of the storage space provided by the bridging chip die, the bridging chip die will not affect the cache system (including L1 Cache and L2 / L3 Cache) of the other CPU chip based on the behavior of one CPU chip. Optionally, the bridging chip die maintains the consistency of its provided storage space for both CPU chips. Changes made by one CPU chip to the storage space provided by the bridging chip die are visible to accesses to the same storage space from the other CPU chip. This design simplifies the bridging chip die.

[0124] In one application, the bridge chip die operates in SRAM mode, providing shared SRAM space for CPU chip 1 and CPU chip 2. In another application, the bridge chip die operates in cache mode, with one of CPU chip 1 and CPU chip 2 working while the other is not; in this case, the bridge chip die acts as an LLC for the CPU chip. In yet another application, the bridge chip die operates in cache mode, with both CPU chip 1 and CPU chip 2 working. Since the bridge chip die belongs to a different consistency domain than CPU chip 1 / CPU chip 2, it is not a complete LLC for the two CPU chips, but rather a large-capacity DRAM with a hitable interface cache. Therefore, the bridge chip die in this embodiment is more suitable for local high-performance computing, for expanding local storage capacity, bandwidth, and optimizing access latency (e.g., suitable for AI inference scenarios), and relatively unsuitable for scenarios where multiple computing units need to update shared storage space individually (e.g., AI training scenarios).

[0125] Figure 9A A structural block diagram of a bridging chip die according to another embodiment of this application is shown.

[0126] same Figure 8A Compared to the / 8B embodiment, Figure 9AIn this configuration, the UCIe interface of the bridging chip is connected to the cache controller via a bus, rather than directly. This allows memory access requests from each UCIe interface to be transmitted via the bus to any one or more of the multiple cache controllers, thereby enabling access to the DRAM blocks associated with any one or more of these cache controllers. Figure 9A The diagram illustrates four cache controllers (Cache Controller 0 through Cache Controller 3). These cache controllers operate independently and do not share SRAM resources. For example, each cache controller corresponds one-to-one with a DRAM controller. For a memory access request from the UCIe interface, the corresponding cache controller is determined based on the memory address being accessed, and the request is then transmitted to the appropriate cache controller via the bus for processing.

[0127] In another example, the cache controller and DRAM controller have a one-to-many relationship, but each cache controller has its own dedicated DRAM controller, rather than sharing one. Further buses may be included between the cache controller and its corresponding DRAM controller to transfer memory access requests and data between the cache controller and the DRAM controller.

[0128] exist Figure 9A In this embodiment, the DRAM storage spaces corresponding to each cache controller do not overlap, thus eliminating consistency issues among the cache controllers and eliminating the need for consistency processing circuitry, thereby simplifying the design complexity of the logic chip die. However, since access requests are forwarded between the UCIe interface and the cache controller via the bus, the memory access latency experienced by the logic chip is the same as... Figure 8A It will increase slightly compared to / 8B.

[0129] Figure 9B A structural block diagram of a bridging chip die according to another embodiment of this application is shown.

[0130] same Figure 9A Compared to the previous embodiment, Figure 9B The image shows two bridge chip dies. Bridge chip die 0 and DRAM chip die 0 form a 3D packaged memory device, while bridge chip die 1 and DRAM chip die 1 form another 3D packaged memory device. Bridge chip die 0 and bridge chip die 1 are connected via their respective UCIe interfaces.

[0131] By cascading multiple bridge chips, a wider range of memory space is provided that can be accessed by logic chips. A logic chip connected to a bridge chip (e.g., logic chip 0) can access the memory space shared by DRAM chip 0 and DRAM chip 1. Although logic chip 0 is only connected to bridge chip 0, memory access requests issued by logic chip 0 through UCIe interface 0 are forwarded by the bus of bridge chip 0 to UCIe interface 1 based on the access address, and then transmitted to bridge chip 1. Bridge chip 1 responds to the access request by accessing the DRAM chip 1 connected to it based on the access address.

[0132] In this way, any number of bridge chip dies can be connected via the UCIe interface, with each bridge chip die integrated with its corresponding DRAM chip die through 3D packaging. This allows for the provision of storage devices with various capacity specifications. The DRAM chip dies connected to each cascaded bridge chip die can have the same or different DRAM capacities.

[0133] Each UCIe interface connected to the bus has a different bus address range. The bus determines whether to forward the access request to other UCIe interfaces and / or the DRAM controller based on the address accessed by the memory access request.

[0134] Figure 9C Showing Figure 9A A schematic diagram of the layout of the DRAM chip die main plane used in the / 9B embodiment.

[0135] Figure 9D Showing with Figure 9C A schematic diagram of the layout of the main plane of the DRAM chip die corresponding to the bridge chip die.

[0136] Figure 9D The bridging chip die is used to connect with Figure 9C The DRAM chip chips are bonded together, with the main planes of the two chips facing each other during bonding. Figure 9D The dashed box in the middle shows Figure 9C The corresponding location of the DRAM block.

[0137] The middle area of ​​the bridge chip die (the area not occupied by the DRAM interface and UCIe interface) can be used to set up circuits such as the bus, cache controller (and its SRAM).

[0138] The bus is located in the middle area of ​​the bridge chip, while the cache controller / SRAM is positioned relatively close to the DRAM interface. This allows access requests to be forwarded to each cache controller via the bus to access the respective DRAM interface and, consequently, the DRAM block. UCIe interface 0 / 1 is located near the bus so that memory access requests received from the UCIe interface can be transmitted via the bus to the cache controller capable of servicing the request. Since each cache controller is connected to the bus, all UCIe interfaces can share all cache controllers.

[0139] Figure 9E A flowchart illustrating the read request processing of a bridge chip die according to yet another embodiment of this application is shown.

[0140] As an example, the logic chip sends a read request to access the memory space through the UCIe interface 0 of the bridge chip die. The address to be accessed by the read request is provided by DRAM block 0. Figure 9E The image shows the read request processing flow for three different scenarios, separated by dashed lines.

[0141] In scenario A, UCIe interface 0 sends a read request to the bus ( Figure 9E (A1). The bus identifies which DRAM controller should handle the current access request based on which DRAM block the target address to be accessed by the read request belongs to, and sends the read request to that DRAM controller (A2). For example, the read request is handled by DRAM controller 0. The read request sent to DRAM controller 0 is received by cache controller 0. The cache controller first checks whether there is a cache hit based on the requested address. In case A, there is a cache miss, and cache controller 0 generates a read request to fill the cache line and sends it to DRAM controller 0 (A3). The size of the data read by the read request to fill the cache line is the entire cache line, which may be different from the size of the data read by the read request received from UCIe interface 0. After receiving the read request, DRAM controller 0 reads the data from the complete cache line read from DRAM block 0 connected to itself and returns it to cache controller 0 (A4). Cache controller 0 fills its own cache line (SRAM) with the received data and returns the data to be read by the read request received from UCIe interface 0 to the bus (A5), and then returns it to UCIe interface 0 (A6) as a response to the read request. UCIe interface 0 returns the data to the logic chip.

[0142] In scenario B, UCIe interface 0 sends a read request to the bus. Figure 9E(B1). The bus identifies which DRAM controller should handle the current access request based on which DRAM block the target address to be accessed by the read request belongs to, and sends the read request to that DRAM controller (B2). For example, the read request is handled by DRAM controller 0. The read request sent to DRAM controller 0 is received by cache controller 0. The cache controller first checks whether there is a cache hit based on the requested address. In case B, if there is a cache hit, the cache controller retrieves the data to be read from its own hit cache line (SRAM) and returns it to the bus (B3), and then returns it to UCIe interface 0 (B4) as a response to the read request. UCIe interface 0 returns the data to the logic chip.

[0143] In case C, UCIe interface 0 sends a read request to the bus ( Figure 9E (C1). The bus identifies which DRAM controller should handle the current access request based on which DRAM block the target address to be accessed by the read request belongs to, and sends the read request to that DRAM controller (C2). For example, DRAM controller 0 handles the read request. The read request sent to DRAM controller 0 is received by cache controller 0. The cache controller first checks for a cache hit based on the requested address. In case C, there is a cache miss, and the cache line corresponding to the address accessed by the read request contains dirty data. In this case, data cannot be directly read from DRAM to fill the cache line; instead, the entire cache line must first be written back to the DRAM block. Figure 9E In the process, Cache Controller 0 sends a write request to DRAM Controller 0 to write the cache line back to DRAM block 0. Next, Cache Controller 0 generates a read request to fill the cache line and sends it to DRAM Controller 0 (C3). Upon receiving the read request, DRAM Controller 0 reads the complete cache line from DRAM block 0 connected to it and returns it to Cache Controller 0 (C4). Cache Controller 0 fills its own cache line (SRAM) with the received data and returns the data to be read from the read request received from UCIe interface 0 to the bus (C5), which in turn returns it to UCIe interface 0 (C6) as a response to the read request. UCIe interface 0 then returns this data to the logic chip.

[0144] Although the above uses Cache Controller 0 and DRAM Controller 0 as examples to describe the process of handling read requests by the bridge chip die, it can be understood that the working principles of other Cache Controllers and DRAM Controllers are the same as those of Cache Controller 0 and DRAM Controller 0.

[0145] In another embodiment of this application, the bridge chip die processes write requests. For example, the logic chip issues a write request to access memory space through the UCIe interface 0 of the bridge chip die, and the address to be accessed by the read request is determined by... Figure 9B DRAM block 1 is provided.

[0146] UCIe interface 0 sends a write request to the bus. The bus determines which DRAM controller's address range the write request belongs to based on the target address accessed by the write request. For example, DRAM controller 1 should handle this write request. The write request sent to DRAM controller 1 is received by cache controller 1. The cache controller checks for a cache hit based on the address accessed by the write request. If a hit occurs, the cache controller merges the data to be written with the data in the hit cache line, and then returns the result of the write request processing completed via the bus and UCIe interface 0. If the cache controller 1 detects a cache miss, it retrieves the cache line corresponding to the target address of the write request, writes the data to be written into the cache line, and then returns the result of the write request processing completed via the bus and UCIe interface 0. If the cache line corresponding to the target address of the write request is occupied by data at other addresses, the existing data in the cache is written back to DRAM block 0 via DRAM controller 1 before writing the data to be written into the cache line.

[0147] Optionally, the bridging chip die according to embodiments of this application further includes accelerators, such as AI accelerators, matrix calculation units, encryption / decryption units, and other circuit components. Each component is used to process the data flowing through the bridging chip die accordingly. Combining one or more accelerators can achieve, for example, clustering calculations and support for key-value storage.

[0148] Alternatively, the bridging chip die in this application embodiment supports not only DRAM chip dies packaged in 3D, but also conventional DDR chips, independent SRAM chips and other types of memory chips.

[0149] Optionally, the bridging chip die in this application embodiment may also include a PCIe interface and a PCIe-CXL interface for connecting to a logic chip with a corresponding interface.

[0150] The bridging chip die in this application embodiment can be provided to the user independently and used together with DRAM chip dies from different sources and specifications to construct a storage device and connect to logic chips for use.

[0151] This application also includes 3D-packaged storage devices. The 3D-packaged storage device includes the bridge chip die and DRAM chip die of this application embodiment, which are integrated together by 3D bonding. The storage device may include multiple DRAM chip dies. The 3D-bonded storage device can be packaged into a chip-shaped product, or it can be delivered to the user without packaging, allowing the user to further package its logic chip die or other circuits, interposer boards, and essentially obtain a fully functional chip.

[0152] Figure 9F A schematic diagram showing the layout of the main plane of a DRAM chip die according to another embodiment of this application is provided.

[0153] Figure 9G Showing with Figure 9F A schematic diagram of the layout of the main plane of the DRAM chip die corresponding to the bridge chip die.

[0154] Figure 9G The bridging chip die is used to connect with Figure 9F The DRAM chip chips are bonded together, with the main planes of the two chips facing each other during bonding. Figure 9G The dashed box in the middle shows Figure 9F The corresponding location of the DRAM block.

[0155] Figure 9F The DRAM chip die consists of four rows of DRAM blocks. The DRAM interfaces of the top two rows of DRAM blocks are adjacent, and the DRAM interfaces of the bottom two rows of DRAM blocks are adjacent. The DRAM interface area is used to set up TSVs for communication with other DRAM blocks in the vertical direction. Although the DRAM interface occupies most of one edge of the DRAM block, there is still space for routing between adjacent DRAM interfaces. Optionally, the TSV does not occupy the entire area of ​​the DRAM interface; the main plane area within the DRAM interface area can also be used for routing.

[0156] Figure 9G The DRAM interface of the bridge chip die is used to interface with the DRAM interface of the DRAM chip die. Wiring can also be used within the DRAM interface area of ​​the bridge chip die, and / or between adjacent DRAM interfaces. The middle area of ​​the bridge chip die (the area not occupied by the DRAM interface and UCIe interface) can be used to house circuitry such as the bus, cache controller (and its SRAM). The bus is located in the middle area of ​​the bridge chip, while the cache controller / SRAM is located relatively close to the DRAM interface. UCIe interface 0 / 1 is located near the bus. There are areas not occupied by DRAM interfaces at the top and bottom of the bridge chip die; more SRAM can be placed in these areas. The cache controller uses the SRAM located at the top and bottom by wiring within or between the DRAM interface areas.

[0157] Figure 10A A 3D-packaged storage device according to an embodiment of this application is shown.

[0158] Figure 10A In this 3D packaged storage device, a bridge chip die according to an embodiment of the present application and eight DRAM chip dies are included. The bridge chip die and the eight DRAM chip dies are 3D bonded. After bonding, the device is provided to the user or for further testing and packaging. The 3D packaged storage device may include other numbers of DRAM chip dies.

[0159] Figure 10A The 3D packaged storage device includes two D2D (Die to Die) interfaces for connecting to other dies. The UCIe interface is a type of D2D interface.

[0160] Figure 10B A chip demonstrating the full functionality according to an embodiment of this application is shown.

[0161] Figure 10B The chips include Figure 10A The 3D packaged storage device and logic chip are connected via an interposer or substrate. The substrate or interposer contains wiring that bridges the D2D interface of the chip and the D2D interface of the logic chip.

[0162] Figure 11 A block diagram of an electronic system comprising a bridging chip die according to another embodiment of this application is shown.

[0163] exist Figure 11 In this example, the electronic system includes five cascaded bridge chip dies (shown as bridge chip dies 0-4). Each bridge chip die includes a DRAM chip die to form a storage device. Logic chip die 0 includes four UCIe interfaces. Logic chip 1 is connected to bridge chip die 0 via UCIe interface 0 and UCIe interface 1, and can access the storage space provided by all cascaded bridge chip dies. Bridge chip die 0 is connected to bridge chip die 1 via its UCIe interface 2. Bridge chip die 0 is connected to bridge chip die 2 via its UCIe interface 3. Bridge chip die 1 is connected to bridge chip die 3 via a UCIe interface. Bridge chip die 2 is connected to bridge chip die 4 via a UCIe interface.

[0164] For example, the memory spaces provided by the five bridge chip dies are denoted as S0 to S4. When a memory access request issued by logic chip 1 accesses address s0 of space S0, the bus of bridge chip dies 0 forwards the access request to the DRAM controller of bridge chip dies 0 for processing. The bus of bridge chip dies 0 forwards access requests for addresses belonging to address spaces S1 or S3 to UCIe interface 2, and forwards access requests for addresses belonging to address spaces S2 or S4 to UCIe interface 3.

[0165] Figure 11 In the example, the bus of bridge chip 1 forwards access requests from logic chip 1 that access addresses belonging to address space S3 to bridge chip 3, and forwards access requests that access addresses belonging to address space S1 to its own DRAM controller for processing. Optionally, there is a logic chip connected to bridge chip 1, and the bus of bridge chip 1 forwards access requests from that logic chip that access addresses belonging to address spaces S0, S2, or S4 to bridge chip 0.

[0166] Figure 11 In the example, the bus of bridge chip 2 forwards access requests for addresses belonging to address space S4 to bridge chip 4, and forwards access requests for addresses belonging to address space S2 to its own DRAM controller for processing. Optionally, if there are logic chips connected to other bridge chip dies besides bridge chip 0, the bus of bridge chip 2 will forward received access requests for addresses belonging to address spaces S0, S1, or S3 to bridge chip 0.

[0167] Figure 11 In the example, the bus of bridge chip die 3 forwards access requests for addresses belonging to address space S3 to its own DRAM controller for processing. Optionally, if there are logic chips connected to other bridge chip dies besides bridge chip die 0, the bus of bridge chip die 3 forwards received access requests for addresses belonging to address spaces S0, S1, S2, and S4 to bridge chip die 0.

[0168] Figure 11 In the example, the bus of bridge chip die 4 forwards access requests for addresses belonging to address space S4 to its own DRAM controller for processing. Optionally, if there are logic chips connected to other bridge chip dies besides bridge chip die 0, the bus of bridge chip die 4 forwards received access requests for addresses belonging to address spaces S0, S1, S2, and S3 to bridge chip die 2.

[0169] It is understandable that for multiple bridge chip dies cascaded in other topologies, the access requests received by each UCIe interface on the bus of each bridge chip die are configured according to the memory space provided by each bridge chip die and the topology. Regardless of the topology used, logic chip 1 can always access the memory space provided by all bridge chip dies.

[0170] Figure 12 A block diagram of an electronic system composed of a bridging chip die, according to yet another embodiment of this application, is shown.

[0171] exist Figure 12 The electronic system includes four logic chips (shown as logic chip 1-logo chip 4) and two cascaded bridge chip dies (shown as bridge chip die 0-bridge chip die 4). Each bridge chip die includes a DRAM chip die to form a storage device. Logic chip die 0 and logic chip die 1 each include five UCIe interfaces. Logic chip 1 is connected to bridge chip die 0 via UCIe interface 0 and UCIe interface 1 of logic chip die 0, and can access the storage space provided by all cascaded bridge chip dies. Logic chip 2 is connected to bridge chip die 0 via UCIe interface 2 and UCIe interface 3. Logic chip 3 is connected to bridge chip die 1 via UCIe interface 0 and UCIe interface 1 of logic chip die 1. Logic chip 4 is connected to bridge chip die 1 via UCIe interface 2 and UCIe interface 3 of logic chip die 1.

[0172] exist Figure 12 In this embodiment, the bridging chip die not only provides bridging for access requests to the DRAM chip die's storage space from logic chips, but also provides UCIe connectivity between multiple logic chips. Multiple logic chips can collaborate using the UCIe connectivity provided by the bridging chip.

[0173] For example, see Figure 12In addition to accessing the DRAM connected to each bridge chip die via bridge chip die 0 / 1 as described in the previous embodiments, logic chip 1 also accesses logic chip interface 2 via UCIe interface 0 / 1. For example, logic chip 1 occupies address space SL1 on the bus of bridge chip die 0, and logic chip 2 occupies address space SL2 on the bus of bridge chip die 0. Access requests to address space SL2 issued by logic chip 1 via UCIe interface 0 or UCIe interface 1 are forwarded by the bus to UCIe interface 2, and then forwarded to logic chip 2 for processing. As an example of an application, logic chip 1 is a CPU and logic chip 2 is a GPU. Logic chip 1 (CPU) can preprocess the data in the DRAM of bridge chip die 0 and then send relevant information about the data (such as storage address, size, calculations required by the GPU, etc.) to logic chip 2 (GPU) through UCIe interface 0 and UCIe interface 2. Logic chip 2 (GPU) then performs high-performance calculations on the data in the DRAM of bridge chip die 0 according to the instructions of the received relevant information.

[0174] As another example, logic chip 1 and logic chip 2 share data in DRAM. Each logic chip also has a local copy of the shared data. In order to achieve data consistency, logic chip 1 and logic chip 2 pass locks or data access rights information through the UCIe connection provided by bridge chip die 0. Thus, even if bridge chip die 0 does not provide consistency support, logic chip 1 and logic chip 2 can still achieve consistency through their own processing.

[0175] exist Figure 12 In this configuration, bridge chip 0 and bridge chip 1 are interconnected via their respective UCIe interfaces 4. Logic chip 1 / 2 connected to bridge chip 0 can access the DRAM chip connected to bridge chip 1. Similarly, logic chip 3 / 4 can access the DRAM chip connected to bridge chip 0. Furthermore, logic chip 1 / 2 and logic chip 3 / 4 can communicate with each other via UCIe interface 4. Thus, the four logic chips (logic chip 1-logic chip 4) are interconnected and can work collaboratively. The bridge chip bus, upon receiving an access request, does not need to identify whether the access target is DRAM memory or a logic chip; it can determine the target (a UCIe interface or a DRAM controller) based solely on the target address of the access request.

[0176] Optionally, Figure 12In this chip, logic chip 1, logic chip 2, bridge chip die 0 and the DRAM die connected to them form a multi-die packaged chip, which can be delivered to the user. Figure 12 The multi-chip package, consisting of logic chip 3, logic chip 4, bridge chip 1, and the connected DRAM chips, has the same specifications as the aforementioned multi-chip package. Users can use a single such chip or cascade multiple such chips to work together, depending on the application's needs, to improve the processing bandwidth and performance of the application system.

[0177] Figure 13 A block diagram of an electronic system constructed from a bridging chip die, according to another embodiment of this application, is shown.

[0178] exist Figure 13 In this system, the electronic components include two logic chips (shown as logic chip 1 and logic chip 2) and two cascaded bridge chip dies (shown as bridge chip die 0 and bridge chip die 1). Each bridge chip die includes a DRAM chip to form a storage device. Logic chip die 0 and logic chip die 1 each include four UCIe interfaces. The UCIe interfaces of the bridge chip dies are connected to a bus, which forwards access requests between the UCIe interfaces and the cache controller, and also forwards access requests between multiple UCIe interfaces. UCIe interfaces 1 and 2 of bridge chip dies 0 and 1 are used to connect to the logic chips, while UCIe interface 0 and UCIe interface 3 are used to connect to the UCIe interfaces of other bridge chip dies. Logic chip 1 is connected to bridge chip die 0 through UCIe interfaces 1 and 2 of logic chip die 0 and can access the storage space provided by all cascaded bridge chip dies. Logic chip 2 is connected to bridge chip die 1 through UCIe interface 1 and UCIe interface 2.

[0179] As an example, in addition to accessing the storage space provided by the DRAM chip 0 connected to the bridge chip 0 as described in the aforementioned embodiments, logic chip 1 can also access the storage space provided by the DRAM chip 1 connected to the bridge chip 1. See Figure 13To access the storage space provided by DRAM chip die 1, logic chip 1 sends an access request from UCIe interface 3. The bus of bridge chip die 0 forwards the access request to its UCIe interface 3 according to the target address of the access request, and then the access request is transmitted to UCIe interface 0 of bridge chip die 1. Upon receiving the access request, UCIe0 of bridge chip die 1 provides it to the bus and, based on the target address, knows that it should be handled by its own DRAM controller. Subsequently, the bus of bridge chip die 1 forwards the access request to the connected DRAM controller (Cache controller) corresponding to the target address for processing.

[0180] As an example again, logic chip 1 and logic chip 2 can also transmit access requests and give responses to each other through the UCIe interface and bus of bridge chip die 0 and bridge chip die 1, without the need for DRAM controller access.

[0181] By introducing the bridge chip die of the present application embodiment, the interface complexity required for logic chips to use large-capacity DRAM memory can be reduced, without the need to use expensive DDR controllers, while still being able to provide the large capacity and high data bandwidth offered by DRAM.

[0182] Although the examples referenced in this application are described for illustrative purposes only and not for limiting the scope of this application, changes, additions and / or deletions to the implementation may be made without departing from the scope of this application.

[0183] Those skilled in the art who benefit from the teachings presented in the above description and associated drawings will recognize many modifications and other embodiments of the present application described herein. Therefore, it should be understood that the present application is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in its general and descriptive sense and not for limiting purposes.

Claims

1. A bridging chip die, characterized in that, For connecting at least one DRAM chip die; wherein each of the at least one DRAM chip die includes a plurality of DRAM blocks, and the bridging chip die is used to be integrated with the at least one DRAM chip die via 3D packaging; The bridge chip die includes one or more UCIe interfaces, multiple DRAM controllers, a cache controller, and SRAM; Each of the plurality of DRAM controllers is used to access a corresponding DRAM block, and the DRAM blocks corresponding to different DRAM controllers are different from each other; Each of the plurality of DRAM controllers includes a 3D DRAM interface, which occupies a designated position on the main plane of the bridge chip die and is used to connect to the corresponding DRAM block; when the main plane of the bridge chip die is attached to the main plane of the first DRAM chip die in the at least one DRAM chip die, the 3D DRAM interface of each DRAM controller is connected to the DRAM interface of each DRAM block of the first DRAM chip die. The cache controller and the SRAM serve as the cache for the at least one DRAM chip die, and the SRAM serves as the cache row for the cache controller.

2. The bridging chip die according to claim 1, characterized in that, It also includes the first bus; Each of the one or more UCIe interfaces is connected to the Cache controller; The cache controller is connected to the plurality of DRAM controllers via the first bus; Each of the one or more UCIe interfaces will provide the received storage space access request to the Cache controller; The cache controller accesses any one of the plurality of DRAM controllers via the first bus.

3. The bridging chip die according to claim 1, characterized in that, This includes a first bus, multiple UCIe interfaces, and multiple cache controllers; Each of the plurality of cache controllers is connected to one of the plurality of UCIe interfaces; Each of the plurality of cache controllers has a cache line; The storage spaces accessible by the multiple UCIe interfaces overlap at least partially with each other; Each cache controller and its cache lines serve as the cache of the storage space accessible by the UCIe interface to which they are connected; The plurality of cache controllers are all connected to the plurality of DRAM controllers via the first bus; The bridging chip die also includes a consistency processing circuit; the consistency processing circuit maintains consistency among the caches of the multiple UCIe interfaces.

4. The bridging chip die according to claim 1, characterized in that, It also includes a second bus and multiple cache controllers; The one or more UCIe interfaces are connected to the second bus; The plurality of cache controllers are connected to the second bus; Each of the multiple cache controllers corresponds to one of the DRAM controllers.

5. The bridging chip die according to any one of claims 1-4, characterized in that, Including the first UCIe interface and the second UCIe interface; The storage spaces accessible by the storage space access requests received from the first UCIe interface and the second UCIe interface may be the same, different, or partially overlapping.

6. The bridging chip die according to claim 5, characterized in that, Includes multiple UCIe interfaces; Each of the plurality of UCIe interfaces is used to connect to a logic chip or other bridge chip die.

7. The bridging chip die according to claim 1, characterized in that, The 3D DRAM interface is located in the edge region of the main plane of the bridge chip die; The one or more UCIe interfaces are located in the edge region of the main plane of the bridge chip die that is not occupied by the 3D DRAM interface; The cache controller and the SRAM are located in the area of ​​the main plane of the bridge chip die that is not occupied by the 3D DRAM interface and the one or more UCIe interfaces.

8. The bridging chip die according to claim 4, characterized in that, in, The 3D DRAM interface is located in the edge region of the main plane of the bridge chip die; The one or more UCIe interfaces are located in the edge region of the main plane of the bridge chip die that is not occupied by the 3D DRAM interface; The second bus is located in the central region of the main plane of the bridging chip die; The cache controller and the SRAM are located between the area occupied by the second bus and the area occupied by the 3D DRAM interface on the main plane of the bridge chip die.

9. A storage device, characterized in that, Includes a bridging chip die and at least one DRAM chip die; The bridging chip die and the at least one DRAM chip die are integrated together through 3D packaging; The bridging chip die is the bridging chip die according to claim 4.

10. An electronic system, characterized in that, Includes a first storage device and a second storage device; The first storage device and the second storage device are respectively the storage devices according to claim 9; The first storage device and the second storage device are connected to each other via the UCIe port of the bridge chip of the first storage device and the UCIe port of the bridge chip of the second storage device.

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