Optimized high-speed differential via hole structure, electronic equipment and system

Abstract

The utility model discloses an optimized structure of high-speed differential via holes, the high-speed differential via holes are arranged in each wiring layer, each wiring layer is provided with a corresponding anti-pad, and corresponding wires are laid in the high-speed differential via holes; marking the part of the wire in each suspension area outside the corresponding anti-bonding pad close to the wiring layer as a suspension wire, marking the part of the wire in the high-speed differential via hole as a via hole wire, thickening the suspension wire, and controlling the suspension wire to be thicker than the via hole wire; a suspension line in the routing is thicker than the via hole line; and the size of the anti-bonding pad in each non-adjacent wiring layer is smaller than the size of a preset anti-bonding pad. According to the utility model, through combined use of the thickened suspension line, reduction of non-adjacent wiring layer anti-bonding pads and increase of adjacent wiring layer anti-bonding pads, the impedance of each part is effectively adjusted, and the impedance requirement of high-speed signal transmission is met; and the optimized mode is high in universality, simple and efficient.

Description

Technical Field

[0001] This utility model relates to the field of high-speed digital PCB design technology, specifically to an optimized high-speed differential via structure, electronic device, and system. Background Technology

[0002] PCB stands for Printed Circuit Board. It is a crucial component of the electronics industry. Conductive patterns, such as copper foil, are printed or etched onto an insulating substrate to support and connect various electronic components, enabling electrical connections between circuits. High-speed digital PCBs are printed circuit boards specifically designed to handle high-speed signal transmission and are widely used in high-end electronic products such as computers, communication equipment, and medical instruments.

[0003] To ensure reliable transmission of high-speed signals above 25Gbps, such as 25Gbps, 32Gbps, 56Gbps, and 112Gbps, the physical transmission path on the PCB must have very small impedance fluctuations. High-speed differential vias, as the largest impedance discontinuities on the PCB, offer significant benefits for high-speed signal transmission by further optimizing their structure. However, traditional differential vias lack a clear definition for high-speed signals. Due to design inertia, if differential vias used for 25Gbps and higher speeds are still used as 10Gbps differential vias without differentiation or further optimization, this will significantly impact the performance of signals above 25Gbps.

[0004] Currently, when optimizing high-speed differential vias, for example, for a specific model of multilayer PCB device equipped with high-speed differential vias, there are two main approaches: First, one can change the PCB manufacturing process, upgrading it to a higher-level process to meet transmission requirements. However, this often significantly increases costs and may affect the overall layout, even requiring redesign of each layer and the actual routing, resulting in a massive workload. Second, based on parameters such as the PCB node constants, via sizes, and preset anti-pad sizes, a rigorous calculation of the new anti-pad sizes is performed using an existing model to determine the optimized anti-pad dimensions. However, this calculation process is also very cumbersome and lacks versatility, requiring redesign for each different actual device. Preset anti-pad sizes refer to the default isolation distance pre-set for specific types of vias or component pins during the design of a multilayer PCB.

[0005] In other words, the measures currently being taken involve at least the following two problems:

[0006] 1) High cost and potentially large workload;

[0007] 2) The process is complicated and lacks universality. Utility Model Content

[0008] To address the two issues mentioned above, the purpose of this invention is to propose an optimized structure, electronic device, and system for high-speed differential vias. By combining the use of thickened floating lines, reduced anti-pads on non-adjacent trace layers, and enlarged anti-pads on adjacent trace layers, the impedance of each part is effectively adjusted to meet the impedance requirements for high-speed signal transmission. At the same time, no process change is required, and the optimized method is highly versatile, simple, and efficient.

[0009] This was achieved through the following technical solutions:

[0010] First, an optimized structure for high-speed differential vias is proposed.

[0011] An optimized high-speed differential via structure is applied in a multilayer PCB, which includes multiple parallel adjacent routing layers and multiple non-adjacent routing layers. High-speed differential vias are disposed in each routing layer, and each layer has a corresponding anti-pad. Corresponding traces are laid within the high-speed differential vias. The portion of the trace outside the corresponding anti-pad in each adjacent routing layer is designated as a suspended trace, and the portion of the trace within the high-speed differential via is designated as a via trace. The suspended trace is thicker than the via trace. The size of the anti-pad in each non-adjacent routing layer is smaller than the size of a preset anti-pad.

[0012] Preferably, the size of the anti-pad in each adjacent trace layer is larger than the size of the preset anti-pad.

[0013] Preferably, the anti-pads in each adjacent trace layer are of the same size.

[0014] Preferably, the antipads in each non-adjacent trace layer are of the same size.

[0015] Preferably, the plurality of adjacent routing layers includes at least two adjacent first adjacent routing layers and two adjacent second adjacent routing layers, and there are a plurality of non-adjacent routing layers between the two adjacent first adjacent routing layers and the two adjacent second adjacent routing layers.

[0016] Preferably, the number of layers of multiple non-adjacent traces is greater than the number of layers of multiple adjacent traces.

[0017] Secondly, an electronic device is proposed, which has a built-in multilayer PCB, and the multilayer PCB adopts the high-speed differential via structure as described above.

[0018] In addition, a system is proposed that has a built-in controller connected to an electronic device as described above.

[0019] The advantages of this utility model compared with the prior art are:

[0020] The technical solution of this utility model effectively adjusts the impedance of each part by combining the use of thickening the floating line, reducing the anti-pad of the non-adjacent trace layer and increasing the anti-pad of the adjacent trace layer, so as to meet the impedance requirements of high-speed signal transmission; at the same time, no process change is required, and the optimized method is highly versatile, simple and efficient. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of an optimized high-speed differential via structure in a multilayer PCB.

[0022] Figure 2 A schematic diagram of a structure for widening traces in the suspended area outside the solder pad;

[0023] Figure 3 A schematic diagram of a structure for reducing anti-pads in a non-adjacent trace layer;

[0024] Figure 4 A schematic diagram of a structure with enlarged anti-pads near the trace layer;

[0025] Figure 5 This is a schematic diagram comparing the impedance results of a high-speed differential via after optimization using different methods. Detailed Implementation

[0026] The following will refer to the appendix in the embodiments of this utility model. Figures 1 to 5 The technical solutions in the embodiments of this utility model will be described in detail below.

[0027] like Figure 1 The diagram shows an optimized high-speed differential via structure in a multilayer PCB. The multilayer PCB includes multiple parallel adjacent routing layers and multiple non-adjacent routing layers. One or more high-speed differential vias are placed in each routing layer, and each layer has a corresponding anti-pad. Corresponding traces are laid within the high-speed differential vias. Taking two adjacent high-speed differential vias in the middle as an example, 10 in the diagram represents an enlarged anti-pad in the adjacent routing layer, 20 represents a thickened trace in the suspended area above the anti-pad, 30 represents the planar layer of each non-adjacent routing layer, 40 represents a reduced anti-pad in the planar layer of each non-adjacent routing layer, and 50 represents the planar board of each adjacent routing layer.

[0028] like Figure 2 The diagram shown illustrates a structure for widening traces in the suspended area outside the solder pad; as shown... Figure 3 The diagram shown illustrates a structure for reducing anti-pad size on a non-adjacent trace layer; as shown... Figure 4 The diagram shown illustrates a structure where the anti-pad is enlarged near the trace layer; combined with... Figures 1 to 4 For optimization of any high-speed differential via, there are three optimization methods: Optimization 1, Optimization 2, and Optimization 3. Figure 3 and 4 The vertical arrows are centered on the center point of a high-speed differential via, used to characterize the plane in which they are located. In the case of multiple high-speed differential vias, the centers of the multiple high-speed differential vias are on a straight line.

[0029] For the three optimization methods, the portion of the trace outside the anti-pad of each adjacent trace layer is denoted as a floating trace, and the portion of the trace in the high-speed differential via is denoted as a via trace. Optimization 1 involves thickening the floating trace, making it thicker than the via trace, thereby compensating for the high impedance of the trace in the floating region and reducing the impedance of the trace in the floating region. Optimization 2 involves reducing the size of the anti-pad in each non-adjacent trace layer to be smaller than the preset anti-pad size, to compensate for the relatively high impedance in these layers and effectively reduce the impedance of each non-adjacent trace layer. Multiple adjacent trace layers include at least two adjacent first adjacent trace layers and two adjacent second adjacent traces. Between the two adjacent first adjacent trace layers and the two adjacent second adjacent traces are multiple non-adjacent trace layers. Reducing the impedance in the middle is equivalent to reducing the distance of the trace at both ends of the via, which is more convenient for high-speed signal transmission. Optimization 3 involves enlarging the anti-pads of each adjacent routing layer to a size larger than the preset anti-pad size. This also ensures that the size of the anti-pads in each non-adjacent routing layer is smaller than the size of the anti-pads in each adjacent routing layer, thereby effectively compensating for the low impedance of each adjacent routing layer and allowing its impedance to be effectively increased.

[0030] In this embodiment, the three optimization methods can be used in five combinations in practical applications, including: a) using optimization 1 alone; b) using optimization 2 alone; c) using optimization 1 and optimization 2 in combination; d) using optimization 1 and optimization 3 in combination; e) using optimization 1, optimization 2 and optimization 3 in combination.

[0031] like Figure 5 The diagram shows a comparison of impedance results for a high-speed differential via after optimization using different methods. It illustrates the impedance comparison curves after applying the five combinations of optimization methods to the same high-speed differential via. Blue represents the original impedance curve of the high-speed differential via without any optimization, while red represents the corresponding improved impedance curve. It is evident that each method can optimize impedance, thus better meeting the transmission requirements of high-speed signals. Furthermore, the best effect is achieved when all three optimization methods are used together.

[0032] It is important to emphasize that Optimization 3 cannot be used alone. If Optimization 3 is to be used, it must be combined with Optimization 1 at least. This is because if the floating traces outside the anti-pads are not thickened, but only the anti-pads of the adjacent trace layers are enlarged, more traces will be left floating, and the impedance of the floating traces will suddenly increase. The impedance sudden change of the floating traces will become the determining factor, and the overall impedance continuity will not improve, but will become worse.

[0033] In this embodiment, the size of the anti-pad in each adjacent routing layer is the same, and the size of the anti-pad in each non-adjacent routing layer is the same. By controlling the size change to be the same, it is easier to improve the continuity of impedance.

[0034] In this embodiment, the number of layers of multiple non-adjacent traces is greater than the number of layers of multiple adjacent traces.

[0035] Secondly, an electronic device is proposed, which has a built-in multilayer PCB, and the multilayer PCB adopts the high-speed differential via structure as described above.

[0036] In addition, a system is proposed that has a built-in controller connected to an electronic device as described above.

[0037] In summary, this utility model effectively adjusts the impedance of each part by combining the use of thickened floating lines, reduced anti-pads on non-adjacent trace layers, and enlarged anti-pads on adjacent trace layers, so as to meet the impedance requirements of high-speed signal transmission. At the same time, it does not require changing the process, and the optimized method is highly versatile, simple and efficient, and has significant progress.

[0038] The above embodiments are only for illustrating the technical concept of this application and should not be used to limit the scope of protection of this application. Any modifications made to the technical solution based on the technical concept proposed in this application shall fall within the scope of protection of this application.

Claims

1. An optimized high-speed differential via structure, applied in multilayer PCBs, characterized in that, The multilayer PCB includes multiple parallel adjacent trace layers and multiple non-adjacent trace layers. High-speed differential vias are set in each trace layer and each layer has a corresponding anti-soldering pad. Corresponding traces are laid in the high-speed differential vias. The portion of the trace outside the anti-pad in each adjacent trace layer is called a suspended trace, and the portion of the trace in the high-speed differential via is called a via. The suspended trace is thicker than the via. The size of the anti-pad in each non-adjacent trace layer is smaller than the size of the preset anti-pad.

2. The optimized high-speed differential via structure according to claim 1, characterized in that, The size of the anti-pad in each adjacent routing layer is larger than the preset anti-pad size.

3. The optimized high-speed differential via structure according to claim 2, characterized in that, The anti-pad size is the same in each adjacent routing layer.

4. The optimized high-speed differential via structure according to claim 1, characterized in that, The anti-pad size is the same in each non-adjacent trace layer.

5. The optimized high-speed differential via structure according to claim 1, characterized in that, Multiple adjacent routing layers include at least two adjacent first adjacent routing layers and two adjacent second adjacent routing layers, with multiple non-adjacent routing layers between the two adjacent first adjacent routing layers and the two adjacent second adjacent routing layers.

6. The optimized high-speed differential via structure according to claim 1, characterized in that, The number of layers of multiple non-adjacent traces is greater than the number of layers of multiple adjacent traces.

7. An electronic device, characterized in that, The electronic device has a built-in multilayer PCB, which adopts the optimized high-speed differential via structure as described in any one of claims 1 to 6.

8. A system, characterized in that, The system has a built-in controller, which is connected to an electronic device as described in claim 7.

Images