Display panel

Abstract

The utility model relates to a display panel. The display panel comprises a display area and a non-display area adjacent to the display area, and further comprises a pixel definition layer and a printing layer. A plurality of first openings located in the display area and second openings at least formed in the pixel definition layer and located in the non-display area are formed in the pixel definition layer; the printing layer comprises a plurality of pixel printing parts arranged in the plurality of first openings; wherein the depth of the second opening in the thickness direction of the display panel is greater than the thickness of the pixel definition layer; according to the display panel, the ink storage amount of the second opening in the manufacturing process of the display panel can be effectively increased, and the film forming uniformity of the pixel printing part is improved; besides, the depth of the second opening in the thickness direction of the display panel is increased, so that the width of the second opening in the direction away from the display area can be reduced or not increased on the basis of ensuring the ink storage amount, and the bezel narrowing of the display panel is facilitated.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess advantages such as self-illumination, fast response, wide viewing angle, high brightness, vibrant colors, and thinness, and are considered the next-generation display technology. There are two main methods for OLED thin-film deposition: vacuum evaporation and solution processing. In inkjet printing, the solvent dries faster in the edge regions than in the display areas. To ensure uniform film formation between pixels and uniform brightness of the corresponding devices, auxiliary pixels are typically placed in the edge regions. These auxiliary pixels also have ink printed within them, but they do not emit light when the device is illuminated.

[0003] To meet the above design requirements, multiple auxiliary pixels are usually needed in the edge area to accommodate more ink and make the film formation uniform. However, this will also make the border area occupied by the edge area larger, which is not conducive to the design requirements of narrow borders. Utility Model Content

[0004] This application provides a display panel that can increase the ink capacity in the second opening, thereby improving the film uniformity of the pixel printing section and facilitating the narrowing of the display panel's bezel.

[0005] This application embodiment provides a display panel, the display panel including a display area and a non-display area adjacent to the display area, the display panel further including:

[0006] A pixel definition layer, wherein a plurality of first openings are formed in the display area, and at least a second opening is formed in the pixel definition layer and located in the non-display area;

[0007] The printing layer includes a plurality of pixel printing portions disposed within a plurality of the first openings;

[0008] Wherein, the depth of the second opening along the thickness direction of the display panel is greater than the thickness of the pixel definition layer.

[0009] In one embodiment of this application, the display panel further includes:

[0010] A substrate, wherein the pixel definition layer is disposed on one side of the substrate;

[0011] An array layer is disposed between the substrate and the pixel definition layer;

[0012] The distance between the bottom surface of the second opening and the substrate is less than the thickness of the array layer.

[0013] In one embodiment of this application, the array layer includes:

[0014] A first conductive layer is disposed between the substrate and the pixel definition layer;

[0015] A first planarization layer is disposed between the first conductive layer and the pixel definition layer;

[0016] A second planarization layer is disposed between the first planarization layer and the first conductive layer;

[0017] Wherein, the distance between the bottom surface of the second opening and the substrate is less than the distance between the side of the first flat layer away from the substrate and the substrate.

[0018] In one embodiment of this application, the second opening passes through the pixel definition layer and the first planarization layer;

[0019] Alternatively, a third opening is formed in the second planarization layer, the first planarization layer covers the sidewalls and bottom surface of the third opening, and the third opening is located between the second opening and the substrate.

[0020] In one embodiment of this application, the array layer includes:

[0021] A second conductive layer is disposed between the substrate and the first conductive layer;

[0022] A third planarization layer is disposed between the second conductive layer and the first conductive layer;

[0023] An insulating layer is disposed between the third planarization layer and the second conductive layer;

[0024] Wherein, at least one of the third planarization layer and the insulating layer is formed with a fourth opening, the fourth opening being located between the second opening and the substrate.

[0025] In one embodiment of this application, the first conductive layer includes a first signal line disposed in the non-display area. The first signal line includes a first line segment and a second line segment connected to each other. The first line segment is disposed corresponding to the fourth opening, and the distance between the first line segment and the substrate is less than the distance between the second line segment and the substrate.

[0026] In one embodiment of this application, a third opening is formed in the second planarization layer, and a fourth opening is formed in the third planarization layer. The third opening and the fourth opening are connected, and both the third opening and the fourth opening are located between the second opening and the substrate.

[0027] The first flat layer covers the sidewall of the third opening, the sidewall of the fourth opening, and the bottom surface of the fourth opening.

[0028] In one embodiment of this application, a third opening is formed in the second planarization layer, and a fourth opening is formed in the insulating layer. The third opening is located between the second opening and the fourth opening, and the fourth opening is located between the third opening and the substrate.

[0029] The first flattening layer covers the sidewalls and bottom surface of the third opening, and the third flattening layer covers the sidewalls and bottom surface of the fourth opening.

[0030] In one embodiment of this application, the printing layer further includes a virtual printing section disposed in the non-display area, the virtual printing section being located within the second opening.

[0031] In one embodiment of this application, the display panel further includes:

[0032] The anode layer includes a plurality of first anodes disposed in the display area and a second anode disposed in the non-display area. The plurality of first anodes are disposed corresponding to a plurality of pixel printing parts. The pixel printing parts are located on the side of the corresponding first anode that is close to the light-emitting surface of the display panel, and the virtual printing parts are located on the side of the second anode that is close to the light-emitting surface of the display panel.

[0033] This application provides a display panel in which the depth of a second opening located in the non-display area is increased. Specifically, the depth of the second opening along the thickness direction of the display panel is set to be greater than the thickness of the pixel definition layer. This effectively increases the ink storage capacity of the second opening during the manufacturing process of the display panel and improves the film uniformity of the pixel printing section. Furthermore, since the depth of the second opening along the thickness direction of the display panel is increased, the width of the second opening along the direction away from the display area can be reduced or not increased while ensuring the ink storage capacity, which is beneficial for achieving a narrow bezel of the display panel.

[0034] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0037] Figure 1 This is a schematic diagram of a planar distribution of a display panel provided in an embodiment of this application;

[0038] Figure 2 This is a schematic diagram of the structure of the display panel within the display area provided in the embodiments of this application;

[0039] Figure 3 Provided for the embodiments of this application Figure 2 A schematic diagram of the first type of cross-sectional structure obtained along line AA;

[0040] Figure 4 This is a schematic diagram of the structure of the display panel in the non-display area provided in an embodiment of this application;

[0041] Figure 5 Provided for the embodiments of this application Figure 4 A schematic diagram of the first type of structure obtained by cutting along line BB;

[0042] Figure 6 Provided for the embodiments of this application Figure 2 A schematic diagram of the second type of cross-sectional structure obtained along line AA;

[0043] Figure 7 Provided for the embodiments of this application Figure 4 A schematic diagram of the second structure obtained by cutting along line BB;

[0044] Figure 8 Provided for the embodiments of this application Figure 4 A schematic diagram of the third structure obtained by cutting along line BB;

[0045] Figure 9 Provided for the embodiments of this application Figure 4 A schematic diagram of the fourth structure obtained by cutting along line BB;

[0046] Figure 10 Provided for the embodiments of this application Figure 4 A schematic diagram of the fifth structure obtained by cutting along line BB;

[0047] Figure 11 Provided for the embodiments of this application Figure 4 A schematic diagram of the sixth structure obtained by cutting along line BB;

[0048] Figure 12 Provided for the embodiments of this application Figure 4 A schematic diagram of the seventh structure obtained by cutting along line BB;

[0049] Figure 13 Provided for the embodiments of this application Figure 4 The eighth structural diagram is obtained by cutting along line BB.

[0050] Explanation of reference numerals in the attached figures:

[0051] 101. Display area; 102. Non-display area; 10. Substrate;

[0052] 20. Pixel definition layer; 21. First barrier; 22. Second barrier; 201. First opening; 202. Second opening;

[0053] 30. Printing layer; 31. Pixel printing section; 310. First ink; 32. Virtual printing section; 320. Second ink;

[0054] 40. Array layer; 401. Third opening; 402. Fourth opening; 41. First planarization layer; 42. Second planarization layer; 43. Third planarization layer; 44. Insulating layer; 45. First conductive layer; 451. First signal line; 4511. First line segment; 4512. Second line segment; 46. Second conductive layer; 461. Second signal line; 47. Functional layer;

[0055] 50. Anode layer; 51. First anode; 52. Second anode. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0057] Please combine Figure 1 , Figure 2 , Figure 3 , Figure 4 as well as Figure 5 This application provides a display panel, which includes a display area 101 and a non-display area 102 adjacent to the display area 101. The display panel also includes a pixel definition layer 20 and a printing layer 30.

[0058] The pixel definition layer 20 has a plurality of first openings 201 located in the display area 101, and at least a second opening 202 formed in the pixel definition layer 20 and located in the non-display area 102; the printing layer 30 includes a plurality of pixel printing portions 31 disposed in the plurality of first openings 201.

[0059] The depth H1 of the second opening 202 along the thickness direction of the display panel is greater than the thickness H2 of the pixel definition layer 20.

[0060] In the implementation process, this embodiment of the application increases the depth H1 of the second opening 202 located in the non-display area 102. Specifically, the depth H1 of the second opening 202 along the thickness direction of the display panel is set to be greater than the thickness H2 of the pixel definition layer 20. This can effectively increase the ink storage capacity of the second opening 202 in the manufacturing process of the display panel and improve the film uniformity of the pixel printing section 31. In addition, since the depth H1 of the second opening 202 along the thickness direction of the display panel is increased, the width of the second opening 202 along the direction away from the display area 101 can be reduced or not increased while ensuring the ink storage capacity, which is beneficial to achieving a narrow bezel of the display panel.

[0061] Specifically, please continue to combine Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 as well as Figure 6 The display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101; in some embodiments, the non-display area 102 is disposed around the display area 101, that is, the non-display area 102 may include the border area of ​​the display panel.

[0062] In some embodiments, the display panel includes a substrate 10, an array layer 40 disposed on the substrate 10, an anode layer 50 disposed on the side of the array layer 40 away from the substrate 10, a pixel definition layer 20 disposed on the side of the array layer 40 away from the substrate 10, and a printing layer 30 disposed on the side of the anode layer 50 away from the substrate 10.

[0063] It should be noted that the array layer 40 may include a plurality of thin-film transistors, signal lines, and a plurality of insulating film layers covering the thin-film transistors disposed on the substrate 10.

[0064] In some embodiments, substrate 10 may be a rigid substrate, such as a glass substrate; or substrate 10 may be a flexible substrate, such as a substrate formed of polyimide. When substrate 10 is a flexible substrate, substrate 10 may be formed of multiple sub-substrates of the same material, such as polyimide, and adjacent sub-substrates may be bonded together by adhesive sub-layers.

[0065] In some embodiments, the array layer 40 includes a functional layer 47 disposed on the substrate 10; the functional layer 47 may specifically include a semiconductor layer, a gate layer, and an insulating film layer disposed on the substrate 10 between the semiconductor layer and the gate layer.

[0066] It is understandable that the semiconductor layer contains the active part of the thin-film transistor, and the gate layer contains the gate of the thin-film transistor.

[0067] In some embodiments, the array layer 40 includes a second conductive layer 46 disposed on the side of the functional layer 47 away from the substrate 10, and the functional layer 47 further includes an insulating film layer located between the gate layer and the second conductive layer 46, or includes an insulating film layer located between the semiconductor layer and the second conductive layer 46.

[0068] In some embodiments, the second conductive layer 46 may include the source and drain of a thin-film transistor, and a second signal line 461 located in the non-display area 102; wherein the source, drain, active portion and gate constitute a thin-film transistor.

[0069] In some embodiments, the display panel may include a pixel driving circuit disposed in the display area 101 and a gate driving circuit located in the non-display area 102, and the gate driving circuit may provide various scanning signals or control signals to the pixel driving circuit; wherein, the second signal line 461 may be used to transmit scanning signals or control signals.

[0070] In some embodiments, the array layer 40 further includes an insulating layer 44 disposed on the side of the second conductive layer 46 away from the functional layer 47, a third planarization layer 43 disposed on the side of the insulating layer 44 away from the second conductive layer 46, a first conductive layer 45 disposed on the side of the third planarization layer 43 away from the insulating layer 44, a second planarization layer 42 disposed on the side of the first conductive layer 45 away from the third planarization layer 43, and a first planarization layer 41 located on the side of the second planarization layer 42 away from the first conductive layer 45; and the anode layer 50 and the pixel definition layer 20 can both be disposed on the first planarization layer 41.

[0071] The first conductive layer 45 may include multiple transfer lines, such as a first signal line 451 located in the non-display area 102. The first signal line 451 may be used to transfer and transmit scanning signals or control signals. In addition, one end of the transfer line may be used to connect to the source or drain of the thin film transistor, and the other end of the transfer line may be used to connect to the anode layer 50.

[0072] It should be noted that the first signal line 451 and the second signal line 461 can be arranged to overlap along the thickness direction of the display panel, or the first signal line 451 and the second signal line 461 can be arranged to not overlap along the thickness direction of the display panel.

[0073] In some embodiments, the anode layer 50 includes a plurality of first anodes 51 disposed in the display area 101, and the other end of the adapter cable can be connected to the first anodes 51 to realize signal transmission between the first anodes 51 and the thin-film transistor.

[0074] In some embodiments, the pixel definition layer 20 includes a plurality of first openings 201 disposed in the display area 101 and a second opening 202 disposed in the non-display area 102; wherein, the plurality of first openings 201 are disposed in a one-to-one correspondence with a plurality of first anodes 51, and each first opening 201 exposes the surface of the corresponding first anode 51 on the side away from the substrate 10.

[0075] In some embodiments, the printing layer 30 is disposed on the side of the anode layer 50 away from the substrate 10, and the printing layer 30 includes a plurality of pixel printing portions 31 disposed in the display area 101; the plurality of pixel printing portions 31 are disposed one-to-one with a plurality of first anodes 51, wherein each pixel printing portion 31 is disposed in a corresponding first opening 201 on one side and is located on the side of a corresponding first anode 51 away from the substrate 10, that is, the pixel printing portion 31 is located on the side of the first anode 51 close to the light-emitting surface of the display panel.

[0076] It should be noted that the printing layer 30 in the display panel provided in this application embodiment includes multiple pixel printing sections 31, and the pixel printing sections 31 can be prepared by inkjet printing process. In inkjet printing process, after the ink of the pixel printing section 31 is formed, it needs to be cured to form a film so that the solvent of the ink evaporates. However, the solvent evaporation rate at the edge of the display panel is faster, which can easily lead to uneven film thickness of the pixel printing section 31. In order to make the solvent atmosphere above the display panel uniform and ensure the thickness uniformity of the pixel printing section 31, this application embodiment provides a second opening 202 in the non-display area 102 to contain ink in the process, so as to increase the solvent atmosphere at the edge of the display panel, balance the solvent evaporation rate in different areas of the display panel, and thus effectively improve the film uniformity of the pixel printing section 31 in the display panel, and improve the luminous efficiency and yield of the display panel.

[0077] The second opening 202 is located within the non-display area 102. The depth H1 of the second opening 202 along the thickness direction of the display panel is greater than the thickness H2 of the pixel definition layer 20. This can effectively increase the ink storage capacity of the second opening 202 during the manufacturing process of the display panel and improve the film uniformity of the pixel printing section 31. In addition, since the depth H1 of the second opening 202 along the thickness direction of the display panel has increased, the width of the second opening 202 along the direction away from the display area 101 can be reduced or not increased while ensuring the ink storage capacity. This is beneficial for achieving a narrow bezel of the display panel.

[0078] In some embodiments, the pixel printing unit 31 may include at least one of a hole injection layer, a hole transport layer, and a light-emitting layer disposed within the first opening 201; wherein the hole injection layer is located between the hole transport layer and the anode, the hole transport layer is located on the side of the hole injection layer away from the anode, and the light-emitting layer is located on the side of the hole transport layer away from the hole injection layer; and the hole injection layer, the hole transport layer, and the light-emitting layer may all be prepared using an inkjet printing process; when the pixel printing unit 31 contains a light-emitting layer, the pixel printing unit 31 has a light-emitting function.

[0079] It is understood that the display panel may also include an electron transport layer and an electron injection layer disposed sequentially on the side of the printed layer 30 away from the array substrate 10, and the electron transport layer and the electron injection layer may be prepared by vapor deposition process.

[0080] In some embodiments, the distance L1 between the bottom surface of the second opening 202 and the substrate 10 is less than the thickness L2 of the array layer 40.

[0081] In some embodiments, the distance L1 between the bottom surface of the second opening 202 and the substrate 10 is smaller than the distance L3 between the side of the first planarization layer 41 away from the substrate 10 and the substrate 10.

[0082] In other words, within the region corresponding to the second opening 202, the second opening 202 can pass through the pixel definition layer 20 and other film layers located in the pixel definition layer 20 and the substrate 10; or other openings located between the second opening 202 and the substrate 10 are formed in the film layer located between the pixel definition layer 20 and the substrate 10, thereby allowing the film layer in the region corresponding to the second opening 202 to be further recessed, so that the bottom surface of the second opening 202 is closer to the substrate 10, so as to effectively increase the ink storage capacity in the second opening 202.

[0083] For example, the second opening 202 passes through the pixel definition layer 20 and the first flattening layer 41; or, a third opening 401 is formed in the second flattening layer 42, such as... Figure 7 As shown, the first planarization layer 41 covers the sidewall and bottom surface of the third opening 401, which is located between the second opening 202 and the substrate 10.

[0084] For example, at least one of the third planarization layer 43 and the insulating layer 44 has a fourth opening 402, such as Figure 8 As shown, the fourth opening 402 is located between the second opening 202 and the substrate 10.

[0085] It is understandable that the third opening 401 and the fourth opening 402 can both make the bottom surface of the second opening 202 closer to the substrate 10, which can increase the ink storage capacity of the second opening 202.

[0086] The embodiments of this application can increase the amount of second ink 320 formed in the second opening 202 during the process; at the same time, since the first opening 201 is not expanded, the amount of second ink 320 in the second opening 202 can be greater than the amount of first ink 310 in the first opening 201.

[0087] It should be noted that the first ink 310 and the second ink 320 do not exist in the final display panel product. The first ink 310 and the second ink 320 shown in the figures provided in this application embodiment are only used to illustrate the change in the amount of ink stored in the second opening 202.

[0088] In addition, a plurality of first openings 201 are arranged in an array within the display area 101 along the first direction X and the second direction Y, wherein the first direction X and the second direction Y intersect; preferably, the first direction X and the second direction Y are perpendicular to each other.

[0089] The pixel definition layer 20 may include a first barrier 21 extending along a first direction X and a second barrier 22 extending along a second direction Y, and the second barrier 22 is located on the side of the first barrier 21 away from the substrate 10, and the first barrier 21 and the second barrier 22 intersect to form a plurality of first openings 201.

[0090] In some embodiments, a plurality of pixel printing portions 31 between two adjacent second baffles 22 along the first direction X are connected, and the light-emitting layers in a plurality of first openings 201 between two adjacent second baffles 22 along the first direction X also have the same light-emitting color. In the process, the ink formed in the region between two adjacent second baffles 22 along the first direction X is continuous.

[0091] Correspondingly, the second opening 202 in the non-display area 102 can also be arranged in an array along the first direction X and the second direction Y; similarly, the arrangement of the first barrier 21 and the second barrier 22 in the non-display area 102 can be the same as that in the display area 101, and thus, in the non-display area 102, during the process, the ink formed in the area between two adjacent second barrier 22 along the first direction X is continuous.

[0092] In some embodiments, during the manufacturing process, the ink in the plurality of first openings 201 arranged along the second direction Y in the display area 101 and the ink in the plurality of second openings 202 arranged along the second direction Y in the non-display area 102 are continuous; wherein, the anode layer 50 further includes a second anode 52 disposed corresponding to the second opening 202, and the second anode 52 is made of the same material as the first anode 51, thereby facilitating the flow of ink in the first opening 201 near the non-display area 102 to the second opening 202 in the non-display area 102 during the manufacturing process, thereby improving the uniformity of ink distribution in the first opening 201 near the non-display area 102, and further improving the film formation uniformity of the pixel printing section 31.

[0093] In other embodiments of this application, the second opening 202 may also be a continuous opening surrounding the display area 101, and the second anode 52 may also be a single electrode surrounding the display area 101, so as to further increase the ink storage in the non-display area 102 during the display panel manufacturing process.

[0094] In addition, in some embodiments, the pixel definition layer 20 may also include only one barrier, and the thickness of the barrier extending along the second direction Y is greater than the thickness of the barrier extending along the first direction X.

[0095] In some embodiments, the printing layer 30 further includes a virtual printing section 32 disposed on a plurality of second openings 202, and the virtual printing section 32 is located on the side of the second anode 52 near the light-emitting surface of the display panel; wherein the pixel printing section 31 may be formed by curing the first ink 310, and the virtual printing section 32 may be formed by curing the second ink 320.

[0096] It is understandable that the virtual printing section 32 may not have a light-emitting function, or in other words, the film layer inside the second opening 202 may not have a light-emitting function, and the second anode 52 and the first anode 51 may be provided with an insulated space.

[0097] In some embodiments, the surface of the virtual printing section 32 on the side away from the substrate 10 does not extend beyond the surface of the pixel definition layer 20 on the side away from the substrate 10.

[0098] In other embodiments of this application, the second ink 320 may contain only solvent, which can further increase the solvent evaporation atmosphere in the non-display area 102 and improve the film formation uniformity of the pixel printing section 31; thus, the virtual printing section 32 may not be formed in the second opening 202 in the end.

[0099] In one specific embodiment of this application, please refer to Figure 4 as well as Figure 5 The second opening 202 passes through the pixel definition layer 20 and the first flattening layer 41.

[0100] Wherein, the depth H1 of the second opening 202 along the thickness direction of the display panel can be equal to the sum of the thickness H2 of the pixel definition layer 20 and the thickness of the first planarization layer 41, and the bottom surface of the second opening 202 can be regarded as the side of the second planarization layer 42 away from the substrate 10.

[0101] Furthermore, the second anode 52 can be continuously located on the side of the first planarization layer 41 away from the substrate 10, and on the sidewall and bottom surface of the second opening 202.

[0102] In another specific embodiment of this application, please refer to Figure 4 as well as Figure 7 A third opening 401 is formed in the second planarization layer 42, and the third opening 401 passes through the second planarization layer 42 and ends at the first conductive layer 45; the third opening 401 is located between the second opening 202 and the substrate 10.

[0103] The first planarization layer 41 covers the sidewalls and bottom surface of the third opening 401. It can be regarded as the first planarization layer 41 forming a first depression in the area of ​​the third opening 401 during the process of filling the third opening 401. This first depression is part of the second opening 202, which makes the depth H1 of the second opening 202 greater than the thickness H2 of the pixel definition layer 20.

[0104] It is understandable that the bottom surface of the second opening 202 is the side of the first planar layer 41 that is away from the substrate 10.

[0105] In another specific embodiment of this application, please refer to Figure 4 as well as Figure 8 A fourth opening 402 is formed in the third planarization layer 43, and the fourth opening 402 passes through the third planarization layer 43 and ends at the insulating layer 44. The depth of the fourth opening 402 can be equal to the thickness of the third planarization layer 43. The fourth opening 402 is located between the second opening 202 and the substrate 10.

[0106] The second planarization layer 42 covers the sidewalls and bottom surface of the fourth opening 402. As a result, the second planarization layer 42 will form a second depression in the area of ​​the fourth opening 402 during the process of filling the fourth opening 402. When the first planarization layer 41 covers the second depression, a third depression will be formed at the second depression. The third depression is part of the second opening 202, which makes the depth H1 of the second opening 202 greater than the thickness H2 of the pixel definition layer 20.

[0107] It is understandable that the bottom surface of the second opening 202 is the side of the first planar layer 41 that is away from the substrate 10.

[0108] It should be noted that, since a fourth opening 402 is formed in the third planarization layer 43, the first signal line 451 will extend along the shape of the fourth opening 402 when it passes through the fourth opening 402; specifically, the first signal line 451 includes a first line segment 4511 corresponding to the fourth opening 402 and a second line segment 4512 connected to the first line segment 4511, and the distance L4 between the first line segment 4511 and the substrate 10 is smaller than the distance L5 between the second line segment 4512 and the substrate 10.

[0109] The first line segment 4511 is a part of the sidewall and bottom surface of the first signal line 451 located in the fourth opening 402, while the second line segment 4512 is another part of the first signal line 451 located outside the fourth opening 402, that is, the second line segment 4512 is located on the side of the third planarization layer 43 away from the substrate 10.

[0110] In some embodiments, the thickness of the first signal line 451 can be greater than or equal to 6000 angstroms and less than or equal to 7000 angstroms. That is, the thickness of the first signal line 451 is relatively large, and it will not easily break due to the need to climb slopes.

[0111] In some embodiments, the slope angle formed by the sidewall of the fourth opening 402 is about 70°, for example, it can be between 65° and 75°, which can help reduce the probability of the first signal line 451 breaking due to the need to climb the slope.

[0112] In another specific embodiment of this application, please refer to Figure 4 as well as Figure 9 A fourth opening 402 is formed in the insulating layer 44, and the fourth opening 402 passes through the insulating layer 44 and ends at the second conductive layer 46. The depth of the fourth opening 402 can be equal to the thickness of the insulating layer 44. The fourth opening 402 is located between the second opening 202 and the substrate 10.

[0113] The third planarization layer 43 covers the sidewalls and bottom surface of the fourth opening 402. As a result, the third planarization layer 43 will form a fourth depression in the area of ​​the fourth opening 402 during the process of filling the fourth opening 402. When the second planarization layer 42 covers the fourth depression, it will form a fifth depression at the fourth depression. When the first planarization layer 41 covers the fifth depression, it will form a sixth depression at the fifth depression. The sixth depression is part of the second opening 202, which makes the depth H1 of the second opening 202 greater than the thickness H2 of the pixel definition layer 20.

[0114] It is understandable that the bottom surface of the second opening 202 is the side of the first planar layer 41 that is away from the substrate 10.

[0115] In this embodiment, the first signal line 451 is continuously arranged to conform to the shape of the fourth recess at the fourth recess.

[0116] In another specific embodiment of this application, please refer to Figure 4 as well as Figure 10 A fourth opening 402 is formed in the third planarization layer 43, and the fourth opening 402 passes through the third planarization layer 43 and ends at the insulating layer 44. Therefore, the depth of the fourth opening 402 can be equal to the thickness of the third planarization layer 43.

[0117] A third opening 401 is formed in the second planarization layer 42, and the third opening 401 passes through the second planarization layer 42 and is connected to a fourth opening 402. The third opening 401 and the fourth opening 402 are both located between the second opening 202 and the substrate 10.

[0118] During the process of the first planarization layer 41 covering and filling the third opening 401 and the fourth opening 402, a seventh depression is formed in the area of ​​the third opening 401 and the fourth opening 402, and the seventh depression is part of the second opening 202, thereby making the depth H1 of the second opening 202 greater than the thickness H2 of the pixel definition layer 20.

[0119] It is understandable that the bottom surface of the second opening 202 is the side of the first planar layer 41 that is away from the substrate 10.

[0120] In this embodiment, the first signal line 451 is continuously arranged to conform to the shape of the fourth opening 402 at the fourth opening 402.

[0121] In another specific embodiment of this application, please refer to Figure 4 as well as Figure 11 A fourth opening 402 is formed in the third planarization layer 43, and the fourth opening 402 passes through the third planarization layer 43 and ends at the insulating layer 44. Therefore, the depth of the fourth opening 402 can be equal to the thickness of the third planarization layer 43.

[0122] During the process of the second planarization layer 42 covering and filling the fourth opening 402, an eighth recess is formed in the area of ​​the fourth opening 402, and the eighth recess is part of the second opening 202. At the same time, the second opening 202 also passes through the pixel definition layer 20 and the first planarization layer 41, thereby making the depth H1 of the second opening 202 greater than the thickness H2 of the pixel definition layer 20.

[0123] It is understandable that the bottom surface of the second opening 202 is the side of the second flat layer 42 that is away from the substrate 10.

[0124] In this embodiment, the first signal line 451 is continuously arranged to conform to the shape of the fourth opening 402 at the fourth opening 402.

[0125] In another specific embodiment of this application, please refer to Figure 4 as well as Figure 12 A fourth opening 402 is formed in the insulating layer 44, and the fourth opening 402 passes through the insulating layer 44 and ends at the second conductive layer 46. Therefore, the depth of the fourth opening 402 can be equal to the thickness of the insulating layer 44.

[0126] During the process of the third planarization layer 43 covering and filling the fourth opening 402, a ninth depression is formed in the area of ​​the fourth opening 402. During the process of the second planarization layer 42 covering the ninth depression, a tenth depression is formed in the area of ​​the ninth depression, and the tenth depression is part of the second opening 202. At the same time, the second opening 202 also passes through the pixel definition layer 20 and the first planarization layer 41; thus, the depth H1 of the second opening 202 is greater than the thickness H2 of the pixel definition layer 20.

[0127] It is understandable that the bottom surface of the second opening 202 is the side of the second flat layer 42 that is away from the substrate 10.

[0128] In this embodiment, the first signal line 451 is continuously arranged to conform to the shape of the fourth opening 402 at the ninth recess.

[0129] In another specific embodiment of this application, please refer to Figure 4 as well as Figure 13 A fourth opening 402 is formed in the insulating layer 44, and the fourth opening 402 passes through the insulating layer 44 and ends at the second conductive layer 46. Therefore, the depth of the fourth opening 402 can be equal to the thickness of the insulating layer 44.

[0130] A third opening 401 is formed in the second planarization layer 42, and the third opening 401 is located between the second opening 202 and the fourth opening 402. The fourth opening 402 is located between the third opening 401 and the substrate 10.

[0131] The third flat layer 43 covers the sidewalls and bottom surface of the fourth opening 402, and during the covering process, an eleventh depression is formed in the area of ​​the fourth opening 402.

[0132] The first planarization layer 41 covers the sidewalls and bottom surface of the third opening 401, and during the covering process, a twelfth recess is formed in the area of ​​the third opening 401, wherein the eleventh recess is part of the third opening 401, and the bottom surface of the third opening 401 is the side of the third planarization layer 43 away from the substrate 10 and the side of the first conductive layer 45 away from the substrate 10.

[0133] The twelfth recess is part of the second opening 202, which makes the depth H1 of the second opening 202 greater than the thickness H2 of the pixel definition layer 20.

[0134] It is understandable that the bottom surface of the second opening 202 is the side of the first planar layer 41 that is away from the substrate 10.

[0135] In this embodiment, the first signal line 451 is continuously arranged to conform to the shape of the eleventh recess at the fourth opening 402.

[0136] In other embodiments of this application, at least one of the following film layers can be made open, such that the depth H1 of the second opening 202 is greater than the thickness H2 of the pixel definition layer 20, thereby effectively increasing the ink storage capacity of the second opening 202.

[0137] In summary, by increasing the depth of the second opening 202 located in the non-display area 102, specifically by setting the depth H1 of the second opening 202 along the thickness direction of the display panel to be greater than the thickness H2 of the pixel definition layer 20, the ink storage capacity of the second opening 202 in the display panel manufacturing process can be effectively increased, thereby improving the film uniformity of the pixel printing section 31. In addition, since the depth H1 of the second opening 202 along the thickness direction of the display panel has been increased, the width of the second opening 202 along the direction away from the display area 101 can be reduced or not increased while ensuring the ink storage capacity, which is beneficial to achieving a narrow bezel of the display panel.

[0138] In addition, this application embodiment also provides a display device, which includes a display panel as described in the above embodiments.

[0139] It is understood that since the display device has the same display panel as in the above embodiments, the display device has the same beneficial effects as the display panel, which will not be elaborated here.

[0140] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0141] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0142] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0143] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area adjacent to the display area, and the display panel further includes: A pixel definition layer, wherein a plurality of first openings are formed in the display area, and at least a second opening is formed in the pixel definition layer and located in the non-display area; The printing layer includes a plurality of pixel printing portions disposed within a plurality of the first openings; Wherein, the depth of the second opening along the thickness direction of the display panel is greater than the thickness of the pixel definition layer.

2. The display panel according to claim 1, characterized in that, The display panel also includes: A substrate, wherein the pixel definition layer is disposed on one side of the substrate; An array layer is disposed between the substrate and the pixel definition layer; The distance between the bottom surface of the second opening and the substrate is less than the thickness of the array layer.

3. The display panel according to claim 2, characterized in that, The array layer includes: A first conductive layer is disposed between the substrate and the pixel definition layer; A first planarization layer is disposed between the first conductive layer and the pixel definition layer; A second planarization layer is disposed between the first planarization layer and the first conductive layer; Wherein, the distance between the bottom surface of the second opening and the substrate is less than the distance between the side of the first flat layer away from the substrate and the substrate.

4. The display panel according to claim 3, characterized in that, The second opening passes through the pixel definition layer and the first planarization layer; Alternatively, a third opening is formed in the second planarization layer, the first planarization layer covers the sidewalls and bottom surface of the third opening, and the third opening is located between the second opening and the substrate.

5. The display panel according to claim 3, characterized in that, The array layer includes: A second conductive layer is disposed between the substrate and the first conductive layer; A third planarization layer is disposed between the second conductive layer and the first conductive layer; An insulating layer is disposed between the third planarization layer and the second conductive layer; Wherein, at least one of the third planarization layer and the insulating layer is formed with a fourth opening, the fourth opening being located between the second opening and the substrate.

6. The display panel according to claim 5, characterized in that, The first conductive layer includes a first signal line disposed in the non-display area. The first signal line includes a first line segment and a second line segment connected to each other. The first line segment is disposed corresponding to the fourth opening, and the distance between the first line segment and the substrate is less than the distance between the second line segment and the substrate.

7. The display panel according to claim 5, characterized in that, A third opening is formed in the second planarization layer, and a fourth opening is formed in the third planarization layer. The third opening and the fourth opening are connected, and both the third opening and the fourth opening are located between the second opening and the substrate. The first flat layer covers the sidewall of the third opening, the sidewall of the fourth opening, and the bottom surface of the fourth opening.

8. The display panel according to claim 5, characterized in that, A third opening is formed in the second planarization layer, and a fourth opening is formed in the insulating layer. The third opening is located between the second opening and the fourth opening, and the fourth opening is located between the third opening and the substrate. The first flattening layer covers the sidewalls and bottom surface of the third opening, and the third flattening layer covers the sidewalls and bottom surface of the fourth opening.

9. The display panel according to any one of claims 1 to 8, characterized in that, The printing layer also includes a virtual printing section disposed in the non-display area, the virtual printing section being located within the second opening.

10. The display panel according to claim 9, characterized in that, The display panel also includes: The anode layer includes a plurality of first anodes disposed in the display area and a second anode disposed in the non-display area. The plurality of first anodes are disposed corresponding to a plurality of pixel printing parts. The pixel printing parts are located on the side of the corresponding first anode that is close to the light-emitting surface of the display panel, and the virtual printing parts are located on the side of the second anode that is close to the light-emitting surface of the display panel.

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