Dynamic aging test circuit for modular power semiconductor device

Abstract

The utility model discloses a dynamic aging test circuit for a modularized power semiconductor device, and relates to the field of power semiconductor device test hardware systems, the dynamic aging test circuit for the modularized power semiconductor device comprises a plurality of test channels, and any test channel comprises a power supply module and a driving module; the power supply module and the driving module are electrically connected with the test bottom plate through connectors, the power supply module is electrically connected with the driving module, and the power supply module is used for supplying power to the driving module; the driving module accesses an input signal and is electrically connected with a to-be-tested power device. The driving module is used for outputting a voltage excitation waveform to the to-be-tested power device according to the input signal. Through the modular design, the dynamic aging test circuit for the power semiconductor device has the advantages of flexibility, convenience, convenience in maintenance, low cost and high applicability.

Description

Technical Field

[0001] This utility model relates to the field of power semiconductor device testing hardware systems, and in particular to a modular power semiconductor device dynamic aging test circuit. Background Technology

[0002] Currently, specific tooling circuitry (main test board) is used to perform gate dynamic bias aging tests on power semiconductor devices. Existing dynamic aging test circuits employ an integrated gate driver test hardware system, which integrates different types and models of driver ICs into the main test board. Different models of driver ICs have different driving capabilities and characteristics. When the waveform generated by the voltage excitation terminal of the driver IC driving the gate of the power device does not meet the test standards or technical specifications, it is necessary to replace it with a different type and model of driver IC for the specific characteristics of the power device. However, because existing dynamic aging test circuits use an integrated gate driver design, with different types and models of driver ICs integrated on the main test board, it is not possible to quickly replace single or multiple driver ICs, affecting test efficiency.

[0003] Testing a power device often requires designing and debugging a separate drive circuit. However, traditional test circuits using integrated gate drivers require debugging the entire main test board, which is time-consuming, ineffective, and difficult, or even impossible, to debug individual power devices and gate test waveforms (to meet standard waveforms). Furthermore, if individual gate drivers in an integrated gate driver test circuit fail or age prematurely, the entire circuit must be shut down for repair, affecting experimental results, delaying progress, and incurring high maintenance costs. Utility Model Content

[0004] In response to the aforementioned problems and technical requirements, the applicant has proposed a modular power semiconductor device dynamic aging test circuit.

[0005] The technical solution of this utility model is as follows:

[0006] A modular power semiconductor device dynamic aging test circuit includes multiple test channels, and for any test channel, it includes a power supply module and a drive module.

[0007] The power module and the drive module are electrically connected to the test base plate via connectors, and the power module is electrically connected to the drive module. The power module is used to supply power to the drive module.

[0008] The driving module receives the input signal and is electrically connected to the power device under test. The driving module is used to output a voltage excitation waveform to the power device under test according to the input signal.

[0009] A further technical solution is that the power module includes a power input circuit, a power control circuit, a positive power output circuit, and a negative power output circuit, wherein...

[0010] The power supply input circuit includes a power connector CN1 and a rectifier chip D1. The power connector CN1 is connected to the rectifier chip D1. The positive output terminal of the rectifier chip D1 is connected to the power control circuit, and the negative output terminal of the rectifier chip D1 is grounded.

[0011] A further technical solution is that the power control circuit includes a fuse F1, a capacitor C1, a switch SW1, and a power conversion chip U3, wherein...

[0012] One end of the fuse F1 is connected to the positive output terminal of the rectifier chip D1, and the other end of the fuse F1 is grounded through capacitor C1 and connected to the input terminal of the power conversion chip U3 through switch SW1. The ground terminal of the power conversion chip U3 is grounded, the positive output terminal of the power conversion chip U3 is connected to the positive power output circuit, and the negative output terminal of the power conversion chip U3 is connected to the negative power output circuit.

[0013] A further technical solution is that the power control circuit also includes capacitors C8, C10 and C11. The positive output terminal of the power conversion chip U3 is connected to analog ground through capacitor C11. Both capacitors C8 and C10 are connected in parallel with capacitor C11.

[0014] A further technical solution is that the power control circuit also includes capacitors C9, C12 and C13. The negative output terminal of the power conversion chip U3 is connected to analog ground through capacitor C13. Both capacitors C9 and C12 are connected in parallel with capacitor C13.

[0015] A further technical solution is that the positive power output circuit includes resistors R1 and R2, capacitors C2, C3, C4, C5, C6, and C7, and a voltage regulator U1, wherein...

[0016] The positive output terminal of the power conversion chip U3 is connected to the input terminal of the voltage regulator U1. One end of the capacitor C2 is connected to the input terminal of the voltage regulator U1, and the other end of the capacitor C2 is connected to analog ground. The capacitors C3, C4 and C5 are all connected in parallel with the capacitor C2.

[0017] One end of resistor R1 is connected to the input terminal of voltage regulator U1, the other end of resistor R1 is connected to one end of resistor R2 and the adjustment terminal of voltage regulator U1, and the other end of resistor R2 is connected to analog ground.

[0018] One end of capacitor C6 is connected to the output terminal of voltage regulator U1, and the other end of capacitor C6 is connected to analog ground. Capacitor C7 is connected in parallel with capacitor C6, and the output terminal of voltage regulator U1 outputs voltage VDD.

[0019] A further technical solution is characterized in that the negative power supply output circuit includes resistor R3, resistor R4, capacitor C15, capacitor C16, and voltage regulator U2, wherein,

[0020] The negative output terminal of the power conversion chip U3 is connected to the input terminal of the voltage regulator U2, one end of the capacitor C16 is connected to the input terminal of the voltage regulator U2, and one end of the capacitor C15 is connected to the output terminal of the voltage regulator U2.

[0021] One end of resistor R3 is connected to the input terminal of voltage regulator U2, and the other end of resistor R3 is connected to one end of resistor R4 and the adjustment terminal of voltage regulator U2. The other end of resistor R4, the other end of capacitor C16, and the other end of capacitor C15 are connected to analog ground. The output terminal of voltage regulator U2 outputs voltage VEE.

[0022] A further technical solution is that the driving module includes an input interface U4, resistors R5, R6, R7, and R8, an optocoupler U5, an output interface U6, and a driver Q1, wherein...

[0023] The input interface U4 is used to receive input signals. One end of the resistor R5 is connected to the fifth pin of the input interface U4, and the other end of the resistor R5 is connected to the fourth and third pins of the input interface. One end of the resistor R6 is connected to one end of the resistor R5, and the other end of the resistor R6 is connected to the first pin of the optocoupler U5.

[0024] The second pin of the optocoupler U5 is grounded through resistor R7, the fifth pin of the optocoupler U5 is connected to the input terminal of driver Q1, and the output terminal of driver Q1 is connected to output interface U6 through resistor R8.

[0025] The beneficial technical effects of this utility model are:

[0026] (1) The gate drive function is modularly designed as an independent drive module. The drive module is connected to the test base plate to realize the function, so that the type and model of the gate driver in a single drive module can be replaced independently, realizing quick replacement of the gate driver and improving debugging efficiency.

[0027] (2) The independent driver module can debug the driver function separately, which can reduce the debugging difficulty, improve the debugging efficiency, and realize the update and iteration of the driver function at the lowest cost to meet the testing requirements.

[0028] (3) The power supply function that powers the drive module is also designed as an independent power supply module. When the drive module or power supply module is damaged or fails due to aging, it is not necessary to stop the entire test circuit for maintenance. Only the faulty drive module or power supply module needs to be repaired independently, which shortens the experimental test cycle and reduces maintenance costs. Attached Figure Description

[0029] Figure 1 This is a schematic block diagram of one embodiment of the modular power semiconductor device dynamic aging test circuit provided by this utility model.

[0030] Figure 2 This is a circuit diagram of one embodiment of the power supply input circuit provided by this utility model.

[0031] Figure 3 This is a circuit diagram of one embodiment of the power control circuit provided by this utility model.

[0032] Figure 4 This is a circuit diagram of one embodiment of the positive power output circuit provided by this utility model.

[0033] Figure 5 This is a circuit diagram of one embodiment of the negative power supply output circuit provided by this utility model.

[0034] Figure 6 This is a circuit schematic diagram of one embodiment of the driving module provided by this utility model. Detailed Implementation

[0035] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0036] This invention provides a modular dynamic aging test circuit for power semiconductor devices, mainly used for gate aging tests of various types of SiC MOSFET devices, such as... Figure 1 As shown, in one embodiment of the present invention, the modular power semiconductor device dynamic aging test circuit includes multiple test channels, and for any test channel, it includes a power supply module and a drive module.

[0037] The power module and the drive module are electrically connected to the test base plate via connectors, and the power module is electrically connected to the drive module. The power module is used to supply power to the drive module.

[0038] The driving module receives the input signal and is electrically connected to the power device under test. The driving module is used to output a voltage excitation waveform to the power device under test according to the input signal.

[0039] In this embodiment, the test base plate, drive module, and power module are all implemented in the form of PCB (Printed Circuit Board). Specifically, the components in the drive module are set on a PCB to form an independent drive board, and the components in the power module are set on a PCB to form an independent power board. The layout design is carried out on a PCB, and connectors for connecting the power board and the drive board are preset in each test channel, as well as wiring for connecting the power board and the drive board to form the test base plate. The connectors can be standard metal pin headers. Figure 1 The diagram shows three test channels, each capable of testing one power device under test (DUT). Within any test channel, the driver board and power supply board are electrically connected to the test base plate via standard metal headers. The power supply board is electrically connected to the driver board via wiring on the test base plate to supply power to the driver board. The driver board receives an input signal, which can be provided by a signal generator and can be a PWM signal. The DUT is connected to the driver board, and the driver board outputs a voltage excitation waveform to the gate of the DUT (SiC MOSFET device) based on the input signal to perform continuous dynamic aging tests. The specific method of using the voltage excitation waveform for dynamic aging tests is consistent with existing technologies. In practice, the number of test channels can be set according to actual needs, and the form of the signal generator can be consistent with existing technologies.

[0040] The drive module is equipped with a gate driver. As is known from the background art, different types and models of gate drivers have different driving capabilities and characteristics. Since the drive module in this application is an independent modular design, when the voltage excitation waveform output by the current drive module does not meet the experimental standards, the type and model of the gate driver in the drive module can be quickly and conveniently replaced to improve testing efficiency. In addition, multiple backup drive modules with different models of gate drivers can be preset. When the voltage excitation waveform output by the currently used drive module does not meet the experimental standards, a drive module with better performance can be directly replaced by plugging and unplugging the connector. In case of failure of the drive module or power module, the faulty drive module or power module can be targeted for repair, reducing maintenance costs. At the same time, the independent drive module can also reduce the difficulty of debugging the voltage excitation waveform, so as to quickly meet the testing requirements.

[0041] Furthermore, the power module includes a power input circuit, a power control circuit, a positive power output circuit, and a negative power output circuit, wherein,

[0042] like Figure 2As shown, the power supply input circuit includes a power connector CN1 and a rectifier chip D1. The power connector CN1 is connected to the rectifier chip D1. The positive output terminal of the power connector CN1 is grounded, and the negative output terminal of the power connector CN1 is connected to voltage VCC. The two input terminals (AC) of the rectifier chip D1 are connected to the positive and negative output terminals of the power connector CN1, respectively. The positive output terminal of the rectifier chip D1 is connected to the power control circuit, and the negative output terminal of the rectifier chip D1 is grounded. Alternating current (AC) is input to the rectifier chip D1 through the power connector CN1, and the rectifier chip D1 rectifies the AC current and outputs a 24V DC voltage.

[0043] like Figure 3 As shown, the power control circuit includes a fuse F1, a capacitor C1, a switch SW1, a power conversion chip U3, capacitors C8, C10, C11, C9, C12, and C13, wherein...

[0044] One end of fuse F1 is connected to the positive output terminal of rectifier chip D1. The other end of fuse F1 is grounded through capacitor C1 and connected to the input terminal (VIN) of power conversion chip U3 through switch SW1. The ground terminal (GND) of power conversion chip U3 is grounded. The positive output terminal (+VO) of power conversion chip U3 is connected to the positive power output circuit, and the negative output terminal (-VO) of power conversion chip U3 is connected to the negative power output circuit. The positive output terminal of power conversion chip U3 is connected to analog ground through capacitor C11, and capacitors C8 and C10 are connected in parallel with capacitor C11. The negative output terminal of power conversion chip U3 is connected to analog ground through capacitor C13, and capacitors C9 and C12 are connected in parallel with capacitor C13.

[0045] In one embodiment of this utility model, the switch SW1 can be a push-button switch, the capacitor C1 can be an electrolytic capacitor, the second and fifth pins of the push-button switch are connected to the positive terminal of the capacitor C1, the negative terminal of the capacitor C1 is grounded, the fourth and first pins of the push-button switch are connected to the input terminal (VIN) of the power conversion chip U3, when the push-button switch is pressed, the fourth and fifth pins of the push-button switch are connected, and the first and second pins are connected, 24V voltage is applied to the input terminal of the power conversion chip U3, the positive output terminal of the power conversion chip U3 outputs +24V voltage, and the negative output terminal of the power conversion chip U3 outputs -24V voltage.

[0046] like Figure 4 As shown, the positive power output circuit includes resistors R1 and R2, capacitors C2, C3, C4, C5, C6, and C7, and a voltage regulator U1.

[0047] The positive output terminal of the power conversion chip U3 is connected to the input terminal (INPUT) of the voltage regulator U1. One end of the capacitor C2 is connected to the input terminal of the voltage regulator U1, and the other end of the capacitor C2 is connected to analog ground. Capacitors C3, C4, and C5 are all connected in parallel with capacitor C2. One end of the resistor R1 is connected to the input terminal of the voltage regulator U1. The other end of the resistor R1 is connected to one end of the resistor R2 and the adjustment terminal (ADJ) of the voltage regulator U1. The other end of the resistor R2 is connected to analog ground. One end of the capacitor C6 is connected to the output terminal (OUTPUT) of the voltage regulator U1, and the other end of the capacitor C6 is connected to analog ground. Capacitor C7 is connected in parallel with capacitor C6. The voltage regulator U1 converts the +24V voltage into the output voltage VDD and outputs it from the output terminal of the voltage regulator U1.

[0048] like Figure 5 As shown, the negative power supply output circuit includes resistor R3, resistor R4, capacitor C15, capacitor C16, and voltage regulator U2. The negative output terminal of the power conversion chip U3 is connected to the input terminal (IN) of the voltage regulator U2, one end of capacitor C16 is connected to the input terminal (IN) of the voltage regulator U2, and one end of capacitor C15 is connected to the output terminal (OUT) of the voltage regulator U2.

[0049] One end of resistor R3 is connected to the input terminal of voltage regulator U2, and the other end of resistor R3 is connected to one end of resistor R4 and the adjustment terminal (ADJ) of voltage regulator U2. The other end of resistor R4, the other end of capacitor C16, and the other end of capacitor C15 are connected to analog ground. Voltage regulator U2 converts the -24V voltage into an output voltage VEE, which is output from the output terminal of voltage regulator U2. The specific values ​​of voltage VDD and voltage VEE can be set according to actual needs to meet the power supply requirements of the drive module. The specific forms of voltage regulator U1 and voltage regulator U2 can be consistent with existing technology.

[0050] In one embodiment of this utility model, both capacitor C15 and capacitor C16 can be electrolytic capacitors. When both capacitor C15 and capacitor C16 are electrolytic capacitors, the negative terminal of capacitor C16 is connected to the negative output terminal of power conversion chip U3, the positive terminal of capacitor C16 is connected to analog ground, the positive terminal of capacitor C15 is connected to analog ground, and the negative terminal of capacitor C15 is connected to the output terminal of voltage regulator U2.

[0051] like Figure 6 As shown, the driving module includes an input interface U4, resistors R5, R6, R7, and R8, an optocoupler U5, an output interface U6, and a driver Q1.

[0052] The input interface U4 is used to receive input signals. One end of the resistor R5 is connected to the fifth pin of the input interface U4. The first to fourth pins of the input interface are interconnected. The other end of the resistor R5 is connected to the fourth and third pins of the input interface. One end of the resistor R6 is connected to one end of the resistor R5. The other end of the resistor R6 is connected to the first pin of the optocoupler U5. The second pin of the optocoupler U5 is grounded through the resistor R7. The fifth pin of the optocoupler U5 is connected to the input terminal (IN) of the driver Q1. The output terminal (OUT#) of the driver Q1 is connected to the output interface U6 through the resistor R8.

[0053] The optocoupler U5 can be of model MOC3021S-TA1, such as... Figure 6 As shown, pin 6 of optocoupler U5 is connected to voltage VDD, and pin 4 of optocoupler U5 is connected to voltage VEE. The power supply terminal (VCC) of driver Q1 is connected to voltage VDD, and the ground terminal (GND) of driver Q1 is connected to voltage VEE. The power device under test (DUT) is connected to the output terminal of driver Q1 through output interface U6 and resistor R8. The drive module is connected to the signal generator through input interface U4 to receive the input signal. In this embodiment, output interface U6 has six pins. The output terminal of driver Q1 is connected to pins 3 and 4 of output interface U6 through resistor R8. Pins 1, 2, 5, and 6 of output interface U6 are all connected to voltage VEE. Driver Q1 is the gate driver described above, which outputs a voltage excitation waveform to the DUT based on the input signal. As can be seen from the above description, the type and model of the gate driver in the drive module can be set according to actual test needs, and the physical form of input interface U4 and output interface U6 can also be set according to actual test needs. Preferably, the form of input interface U4 in all drive modules is uniform for ease of use.

[0054] In the description of this specification, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The reference to the term "an embodiment / method," etc., means that a specific feature or structure described in connection with that embodiment / method is included in at least one embodiment / method of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / method. Features defined as "first" or "second" may explicitly or implicitly include at least one of those features. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0055] Those skilled in the art should understand that the above embodiments are merely for clearly illustrating this disclosure and are not intended to limit the scope of this disclosure. Any other improvements and variations directly derived or conceived by those skilled in the art without departing from the spirit and concept of this utility model should be considered to be included within the protection scope of this utility model.

Claims

1. A modular power semiconductor device dynamic aging test circuit, characterized in that, It includes multiple test channels, and for any given test channel, it includes both the power module and the driver module; The power module and the drive module are electrically connected to the test base plate via connectors, and the power module is electrically connected to the drive module. The power module is used to supply power to the drive module. The driving module receives the input signal and is electrically connected to the power device under test. The driving module is used to output a voltage excitation waveform to the power device under test according to the input signal.

2. The modular power semiconductor device dynamic aging test circuit according to claim 1, characterized in that, The power module includes a power input circuit, a power control circuit, a positive power output circuit, and a negative power output circuit, wherein... The power supply input circuit includes a power connector CN1 and a rectifier chip D1. The power connector CN1 is connected to the rectifier chip D1. The positive output terminal of the rectifier chip D1 is connected to the power control circuit, and the negative output terminal of the rectifier chip D1 is grounded.

3. The modular power semiconductor device dynamic aging test circuit according to claim 2, characterized in that, The power control circuit includes a fuse F1, a capacitor C1, a switch SW1, and a power conversion chip U3. One end of the fuse F1 is connected to the positive output terminal of the rectifier chip D1, and the other end of the fuse F1 is grounded through capacitor C1 and connected to the input terminal of the power conversion chip U3 through switch SW1. The ground terminal of the power conversion chip U3 is grounded, the positive output terminal of the power conversion chip U3 is connected to the positive power output circuit, and the negative output terminal of the power conversion chip U3 is connected to the negative power output circuit.

4. The modular power semiconductor device dynamic aging test circuit according to claim 3, characterized in that, The power control circuit also includes capacitors C8, C10 and C11. The positive output terminal of the power conversion chip U3 is connected to analog ground through capacitor C11. Both capacitors C8 and C10 are connected in parallel with capacitor C11.

5. The modular power semiconductor device dynamic aging test circuit according to claim 3, characterized in that, The power control circuit also includes capacitors C9, C12 and C13. The negative output terminal of the power conversion chip U3 is connected to analog ground through capacitor C13. Both capacitors C9 and C12 are connected in parallel with capacitor C13.

6. The modular power semiconductor device test circuit according to claim 3, characterized in that, The positive power output circuit includes resistor R1, resistor R2, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, and voltage regulator U1, wherein... The positive output terminal of the power conversion chip U3 is connected to the input terminal of the voltage regulator U1. One end of the capacitor C2 is connected to the input terminal of the voltage regulator U1, and the other end of the capacitor C2 is connected to analog ground. The capacitors C3, C4 and C5 are all connected in parallel with the capacitor C2. One end of resistor R1 is connected to the input terminal of voltage regulator U1, the other end of resistor R1 is connected to one end of resistor R2 and the adjustment terminal of voltage regulator U1, and the other end of resistor R2 is connected to analog ground. One end of capacitor C6 is connected to the output terminal of voltage regulator U1, and the other end of capacitor C6 is connected to analog ground. Capacitor C7 is connected in parallel with capacitor C6, and the output terminal of voltage regulator U1 outputs voltage VDD.

7. The modular power semiconductor device dynamic aging test circuit according to claim 6, characterized in that, The negative power supply output circuit includes resistor R3, resistor R4, capacitor C15, capacitor C16, and voltage regulator U2, wherein... The negative output terminal of the power conversion chip U3 is connected to the input terminal of the voltage regulator U2, one end of the capacitor C16 is connected to the input terminal of the voltage regulator U2, and one end of the capacitor C15 is connected to the output terminal of the voltage regulator U2. One end of resistor R3 is connected to the input terminal of voltage regulator U2, and the other end of resistor R3 is connected to one end of resistor R4 and the adjustment terminal of voltage regulator U2. The other end of resistor R4, the other end of capacitor C16, and the other end of capacitor C15 are connected to analog ground. The output terminal of voltage regulator U2 outputs voltage VEE.

8. The modular power semiconductor device dynamic aging test circuit according to claim 7, characterized in that, The driving module includes an input interface U4, resistors R5, R6, R7, and R8, an optocoupler U5, an output interface U6, and a driver Q1. The input interface U4 is used to receive input signals. One end of the resistor R5 is connected to the fifth pin of the input interface U4, and the other end of the resistor R5 is connected to the fourth and third pins of the input interface. One end of the resistor R6 is connected to one end of the resistor R5, and the other end of the resistor R6 is connected to the first pin of the optocoupler U5. The second pin of the optocoupler U5 is grounded through resistor R7, the fifth pin of the optocoupler U5 is connected to the input terminal of driver Q1, and the output terminal of driver Q1 is connected to output interface U6 through resistor R8.

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