Adjustable differential clock generator with digital configuration interface

Abstract

The utility model provides an adjustable differential clock generator with a digital configuration interface, which relates to the technical field of differential clock generators, and comprises a crystal oscillator used for providing a reference clock signal with a fixed frequency; the input end of the phase-locked loop circuit is electrically connected with the output end of the crystal oscillator, and the phase-locked loop circuit comprises a programmable fractional frequency divider; the input end of the output frequency divider is electrically connected with the output end of the phase-locked loop circuit; the input end of the differential output buffer is electrically connected with the output end of the output frequency divider, the differential output buffer integrates multiple differential output modes, and the output end of the differential output buffer is used for outputting differential output signals; the configuration circuit is electrically connected with the decimal frequency divider, the output frequency divider and the differential output buffer respectively; and the serial communication interface is connected with the configuration circuit, the frequency control data received by the serial communication interface is input into the fractional frequency divider through the configuration circuit, and the output mode data received by the serial communication interface is input into the differential output buffer through the configuration circuit.

Description

Technical Field

[0001] This utility model relates to the field of differential clock generator technology, and specifically to an adjustable differential clock generator with a digital configuration interface. Background Technology

[0002] In fields such as electronic communication, computers, and industrial control, clock signals serve as the core driving source for system synchronization and data processing. Their frequency stability, signal integrity, and mode flexibility have a decisive impact on the performance of the entire system. Among them, clock generators based on quartz crystal resonators are widely used in various electronic devices due to their inherent frequency stability, high Q value, and strong anti-interference capabilities.

[0003] Traditional quartz crystal resonators are made by processing artificial crystal into wafers at specific cutting angles, placing conductive electrodes on their surface, and then using the coupling characteristics of mechanical vibration and electrical signals to generate a fixed-frequency reference clock signal. However, the frequency of such resonators is mainly determined by the physical thickness of the wafer. Once packaged, the thickness of the wafer is fixed, making it impossible to adjust the output frequency online. On the one hand, to meet the diverse clock frequency requirements of different circuits, manufacturers need to pre-process wafers of various thicknesses, each corresponding to a specific frequency point. This "one machine, one frequency" production model not only leads to high raw material inventory pressure and complex production processes, but also results in resource waste and increased production costs because the frequency cannot be dynamically adjusted according to actual needs. On the other hand, with the development of high-frequency clock technology, differential output mode has become the mainstream choice for high-frequency clocks due to its advantages such as strong anti-interference and support for long-distance transmission. However, different circuit modules have significant differences in their requirements for the level mode of differential clocks: for example, LVDS (Low Voltage Differential Signaling) is suitable for low-power short-distance transmission, LVPECL (Low Voltage Positive Emitter Coupled Logic) is suitable for high-speed long-distance transmission, and HCSL (Current Mode Logic) is often used in high-speed serial buses. Traditional crystal oscillators only support a single differential output mode and cannot flexibly switch according to the requirements of downstream circuits, which leads to the need to add mode conversion circuits in system design, increasing system complexity and cost. Utility Model Content

[0004] In view of the above problems, this utility model provides an adjustable differential clock generator with a digital configuration interface, comprising:

[0005] A crystal oscillator for providing a reference clock signal at a fixed frequency;

[0006] A phase-locked loop circuit, wherein the input terminal of the phase-locked loop circuit is electrically connected to the output terminal of the crystal oscillator, and the phase-locked loop circuit includes a programmable fractional frequency divider;

[0007] An output frequency divider, wherein the input terminal of the output frequency divider is electrically connected to the output terminal of the phase-locked loop circuit;

[0008] A differential output buffer, the input of which is electrically connected to the output of the output divider, the differential output buffer integrates multiple differential output modes, and the output of which is used to output differential output signals;

[0009] A configuration circuit is provided, which is electrically connected to the fractional frequency divider and the differential output buffer, respectively.

[0010] A serial communication interface is connected to the configuration circuit. Frequency control data received by the serial communication interface is input to the fractional frequency divider through the configuration circuit. Output mode data received by the serial communication interface is input to the differential output buffer through the configuration circuit.

[0011] In one possible implementation, the configuration circuit includes:

[0012] A frequency control register, the output of which is electrically connected to the control terminals of the fractional frequency divider, the output frequency divider, and the output frequency divider, respectively;

[0013] An output mode controller, wherein the output terminal of the output mode controller is electrically connected to the mode selection terminal of the differential output buffer;

[0014] Memory;

[0015] The control interface is electrically connected to the serial communication interface, the memory, the frequency control register, and the output mode controller.

[0016] In one possible implementation, the memory includes non-volatile memory and random access memory, wherein the non-volatile memory is used to store configuration parameters and the random access memory is used for real-time data interaction.

[0017] In one possible implementation, the phase-locked loop circuit includes a phase detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator connected in sequence, with the fractional frequency divider located in the feedback loop of the phase-locked loop circuit.

[0018] In one possible implementation, the differential output buffer supports at least two of the programmable output modes of LVDS, LVPECL, and HCSL.

[0019] In one possible implementation, the serial communication interface is an I²C interface.

[0020] In one possible implementation, the crystal oscillator includes a water crystal wafer that is electrically connected to a base via a conductive connection structure.

[0021] The conductive connection structure includes electrodes and conductive adhesive disposed on the surface of the crystal wafer, used to transmit crystal vibration signals to the circuit interface of the base.

[0022] In one possible implementation, the phase-locked loop circuit, differential output buffer, frequency control register, output mode controller, memory, control interface, and serial communication interface are integrated into an integrated control chip, which is electrically connected to the circuit interface.

[0023] In one possible implementation, the adjustable differential clock generator with a digital configuration interface further includes a top cover that forms a sealed cavity with the base, and the crystal wafer and the integrated control chip are sealed within the sealed cavity.

[0024] The above-described one or more technical solutions in the embodiments of this application have at least one or more of the following technical effects:

[0025] This utility model provides an adjustable differential clock generator with a digital configuration interface. By integrating a phase-locked loop (PLL) circuit, a fractional divider, a differential output buffer, and a configuration circuit, it effectively solves the technical pain points of traditional crystal oscillators, namely "fixed frequency, single mode, and inability to be configured online." Specifically, the fractional divider in the PLL, in conjunction with the configuration circuit, receives frequency control data from the serial communication interface, allowing for real-time adjustment of the division ratio. This enables the same oscillator to cover a wide frequency range, avoiding the high-cost production mode that requires multiple thick crystal wafers. The differential output buffer integrates multiple differential output modes, which are dynamically switched by receiving output mode data through the configuration circuit, simplifying the design complexity of downstream circuits and improving signal integrity. The serial communication interface supports online dynamic configuration, meeting the real-time adjustment requirements of scenarios such as software-defined radio.

[0026] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the module composition structure of the adjustable differential clock generator with a digital configuration interface in an embodiment of this utility model.

[0029] Figure 2 This is a schematic diagram of the crystal wafer structure of the adjustable differential clock generator with a digital configuration interface in an embodiment of this utility model.

[0030] Figure 3 This is a schematic diagram of the circuit interface structure of the adjustable differential clock generator with a digital configuration interface in an embodiment of this utility model.

[0031] Figure 4 This is a schematic diagram of the internal structure of an adjustable differential clock generator with a digital configuration interface according to an embodiment of the present invention.

[0032] Explanation of reference numerals in the attached diagram: 100, Crystal oscillator; 110, Crystal wafer; 120, Electrode; 130, Conductive adhesive; 210, Fractional frequency divider; 220, Phase detector; 230, Charge pump; 240, Low-pass filter; 250, Voltage-controlled oscillator; 300, Output frequency divider; 400, Differential output buffer; 510, Frequency control register; 520, Output mode controller; 530, Memory; 540, Control interface; 600, Serial communication interface; 700, Base; 710, Circuit interface; 800, Integrated control chip; 810, Bonding gold wire; 900, Top cover. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be described in further detail below with reference to the accompanying drawings.

[0034] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this invention as detailed in the appended claims.

[0035] The overall concept of the technical solution provided by this utility model is as follows:

[0036] Please see Figure 1 An adjustable differential clock generator with a digital configuration interface includes:

[0037] Crystal oscillator 100 is used to provide a reference clock signal at a fixed frequency. Understandably, crystal oscillator 100 utilizes the piezoelectric effect of quartz crystal to generate a stable oscillation frequency. When a quartz crystal is subjected to mechanical stress, an electric charge is generated on its surface; conversely, when an electric field is applied to the ends of the crystal, mechanical deformation occurs. After the quartz crystal is cut into a specific shape and thickness, its mechanical vibration frequency is determined by the material properties, cutting angle, and geometric dimensions. When the frequency of the applied electric field matches the inherent mechanical vibration frequency of the crystal, resonance occurs. At this point, the crystal's impedance is at its minimum or maximum, thus outputting a stable periodic electrical signal.

[0038] A phase-locked loop (PLL) circuit is included, with its input electrically connected to the output of a crystal oscillator 100. The PLL circuit includes a programmable fractional-order divider 210. Essentially, a PLL is a feedback control circuit whose core objective is to maintain strict synchronization between the output frequency of a voltage-controlled oscillator (VCO) 250 and a reference frequency through a phase-locked mechanism. A typical structure of a conventional PLL circuit includes a phase detector 220, a loop filter, a VCO 250, and a frequency divider. The phase detector 220 compares the phase difference between the input signal and the feedback signal to generate an error signal. The loop filter filters the error signal to generate a control voltage. The VCO 250 adjusts its oscillation frequency according to the control voltage. The frequency divider divides the output signal of the VCO 250 to generate the feedback frequency. In this invention, the main function of the phase-locked loop circuit is to convert the fixed-frequency reference signal provided by the crystal oscillator 100 into a high-precision output signal with an adjustable frequency. Specifically, traditional integer frequency dividers can only achieve frequency division of integer multiples, while fractional frequency dividers 210 can achieve frequency division of non-integer multiples, thereby providing a finer frequency resolution. By receiving frequency control data, fractional frequency dividers 210 can adjust the division ratio in real time to achieve dynamic adjustment of the output frequency. Through the programmable fractional frequency divider 210, the phase-locked loop circuit can achieve a wide range of frequency outputs to meet the needs of different application scenarios.

[0039] The output frequency divider 300 has its input terminal electrically connected to the output terminal of the phase-locked loop (PLL) circuit. The main function of the output frequency divider 300 is to divide the high-frequency signal output from the PLL circuit to provide the required output frequency. Specifically, the output frequency divider 300 divides the input signal according to a preset division ratio. For example, if the division ratio is 2, the frequency of the output signal is half that of the input signal. The divided signal is then output for use by the subsequent differential output buffer 400. The division ratio of the output frequency divider 300 can be fixed or programmable. A fixed division ratio is suitable for applications with fixed output frequency requirements. A programmable division ratio can be dynamically adjusted by receiving division ratio control data, enabling flexible adjustment of the output frequency. In this invention, to achieve greater flexibility, the output frequency divider 300 can use a programmable division ratio, depending on the design requirements.

[0040] A differential output buffer 400 has its input electrically connected to the output of an output frequency divider 300. The differential output buffer 400 integrates multiple differential output modes, and its output is used to output differential output signals. The differential output buffer 400 is used to process and output clock signals; it receives signals from the output frequency divider 300 and converts them into differential signals for use by downstream circuits. More specifically, the differential output buffer 400 is connected to the output of the output frequency divider 300, receives single-ended clock signals, and converts the single-ended signals into differential signals, i.e., generating a pair of signals with opposite phases. Integrating multiple differential output modes, such as LVDS (Low Voltage Differential Signaling), LVPECL (Low Voltage Positive Emitter Coupled Logic), and HCSL (Current Mode Logic), the differential output buffer 400 supports at least two of the programmable output modes of LVDS, LVPECL, and HCSL. Different formats of differential signals can be output through different types of differential output circuits. For example, an LVDS output circuit converts the input signal to an LVDS format differential signal, an LVPECL output circuit converts the input signal to an LVPECL format differential signal, and an HCSL output circuit converts the input signal to an HCSL format differential signal. The differential output buffer 400 may include a multiplexer with multiple input terminals, each connected to a different type of differential output circuit. The selection control terminal of the multiplexer can select the appropriate differential output circuit based on its input configuration data.

[0041] The configuration circuit is electrically connected to the fractional frequency divider 210 and the differential output buffer 400 respectively. The configuration circuit is the module in this invention that realizes the dynamic configuration of the fractional frequency divider 210 and the differential output buffer 400. By receiving control data from the serial communication interface 600, it configures the fractional frequency divider 210 and the differential output buffer 400 in the phase-locked loop circuit respectively, thereby realizing the dynamic adjustment of the output frequency and output mode.

[0042] A serial communication interface 600 is connected to a configuration circuit. Frequency control data received by the serial communication interface 600 is input to a fractional frequency divider 210 via the configuration circuit. Output mode data received by the serial communication interface 600 is input to a differential output buffer 400 via the configuration circuit. The serial communication interface 600 receives frequency control data and output mode data from an external controller, then parses the received data and transmits it to the fractional frequency divider 210 and the differential output buffer 400 respectively via the configuration circuit. The serial communication interface 600 can include common communication protocol interfaces, such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), and UART (Universal Asynchronous Receiver / Transmitter). The appropriate interface type can be selected according to application requirements, with I2C being the preferred choice.

[0043] By integrating a phase-locked loop (PLL) circuit, a fractional frequency divider 210, a differential output buffer 400, and a configuration circuit, the technical pain points of traditional crystal oscillators 100—namely, fixed frequency, single mode, and inability to be configured online—are effectively solved. Specifically, the fractional frequency divider 210 in the PLL, in conjunction with the configuration circuit, receives frequency control data from the serial communication interface 600, allowing for real-time adjustment of the division ratio. This enables the same oscillator to cover a wide frequency range, avoiding the high-cost production model that requires multiple thick crystal wafers 110. The differential output buffer 400 integrates multiple differential output modes, dynamically switching between them by receiving output mode data through the configuration circuit. This simplifies the complexity of downstream circuit design and improves signal integrity. The serial communication interface 600 supports online dynamic configuration, meeting the real-time adjustment needs of scenarios such as software-defined radio.

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0045] Please see Figure 1 The configuration circuit includes:

[0046] The frequency control register 510 has its output terminals electrically connected to the control terminals of the fractional frequency divider 210 and the output frequency divider 300, respectively. The frequency control register 510 receives and stores frequency control data from the serial communication interface 600. This data includes the required output frequency information, such as the target frequency value, the division ratio, and the frequency adjustment step. Then, the frequency control register 510 transmits the stored frequency control data to the control terminals of the fractional frequency divider 210 or the output frequency divider 300, respectively, to achieve dynamic adjustment of the output frequency.

[0047] The output mode controller 520 is electrically connected to the mode selection terminal of the differential output buffer 400. The output mode controller 520 receives and stores output mode data from the serial communication interface 600. This data contains the required differential output mode information, such as selecting LVDS, LVPECL, HCSL, etc. Then, the output mode controller 520 transmits the stored output mode data to the mode selection terminal of the differential output buffer 400 to control the multiplexer to select the corresponding output mode.

[0048] Memory 530; Memory 530 is used to store the current configuration data of the configuration circuit, including frequency control data and output mode data.

[0049] Control interface 540 is electrically connected to serial communication interface 600, memory 530, frequency control register 510, and output mode controller 520. Control interface 540 acts as a data relay bridge between the configuration circuit and serial communication interface 600, memory 530, frequency control register 510, and output mode controller 520. It manages control signals from serial communication interface 600, such as read / write control signals and address signals, and routes data to the appropriate components based on the control signals; for example, it routes frequency control data to frequency control register 510 and output mode data to output mode controller 520.

[0050] Furthermore, the memory 530 includes a non-volatile memory 530 and a random access memory 530. The non-volatile memory 530 is used to store configuration parameters, and the random access memory 530 is used for real-time data interaction. Specifically, non-volatile memory 530 is used to store configuration parameters, such as frequency control data, output mode data, calibration parameters, and user settings. After a system power failure or restart, the previous configuration data can be restored from the non-volatile memory 530, ensuring the continuity and stability of the system. Common types of non-volatile memory 530 include EEPROM (Electrically Erasable Programmable Read-Only Memory), Flash Memory, and FRAM (Ferroelectric RAM). Random-access memory 530 (RAM) is used to store and quickly access temporary data, such as intermediate calculation results, status information, and real-time configuration changes. It provides high-speed read and write capabilities, supports real-time data processing and rapid configuration updates. Common types of random-access memory 530 include SRAM (Static RAM) and DRAM (Dynamic RAM).

[0051] Please see Figure 1 The phase-locked loop (PLL) circuit includes a phase detector 220, a charge pump 230, a low-pass filter 240, and a voltage-controlled oscillator 250 connected in sequence. A fractional frequency divider 210 is disposed in the feedback loop of the PLL circuit. Specifically, the phase detector 220 compares the phase difference between the input reference signal from the crystal oscillator 100 and the feedback signal from the fractional frequency divider 210 to generate an error signal; the charge pump 230 converts the error signal output by the phase detector 220 into a current signal and outputs a corresponding current pulse based on the direction and amplitude of the error signal; the low-pass filter 240 filters the current pulse output by the charge pump 230 to generate a smooth control voltage; and the voltage-controlled oscillator 250 generates an oscillation signal of a corresponding frequency based on the amplitude of the control voltage, serving as the output signal of the PLL circuit.

[0052] Please see Figures 2 to 4The crystal oscillator 100 includes a crystal wafer 110, which is electrically connected to the base 700 through a conductive connection structure. The crystal wafer 110 is usually made of quartz crystal (SiO2). Quartz crystal has a piezoelectric effect, that is, it generates an electric charge when subjected to mechanical stress, and conversely, it generates mechanical deformation under the action of an electric field. The conductive connection structure is the key part connecting the crystal wafer 110 and the circuit interface 710 of the base 700. Its main function is to convert the mechanical vibration signal of the crystal wafer 110 into an electrical signal and transmit it to the circuit interface 710 of the base 700.

[0053] The conductive connection structure includes an electrode 120 and conductive adhesive 130 disposed on the surface of the crystal wafer 110, for transmitting crystal vibration signals to the circuit interface 710 of the base 700. The electrode 120 disposed on the surface of the crystal wafer 110 is typically a thin metal film (such as silver plating, gold plating, etc.); the conductive adhesive 130 is used to connect the electrode 120 to the circuit interface 710 of the base 700 to transmit electrical signals.

[0054] Furthermore, the phase-locked loop circuit, differential output buffer 400, frequency control register 510, output mode controller 520, memory 530, control interface 540, and serial communication interface 600 are integrated into the integrated control chip 800, which is electrically connected to the circuit interface 710. By integrating the phase-locked loop circuit, differential output buffer 400, frequency control register 510, output mode controller 520, memory 530, control interface 540, and serial communication interface 600 into a single integrated control chip 800, the board space and number of components are significantly reduced, thereby lowering system complexity and cost.

[0055] Preferably, the integrated control chip 800 can be electrically connected to the circuit interface 710 via a gold bonding wire 810. The circuit interface 710 can be a gold-plated pad. The gold bonding wire 810 is a fine gold wire, typically with a diameter between 20 and 50 micrometers. The gold-plated pad is formed by depositing a thin layer of gold on the surface of a copper pad on a circuit board or packaging substrate through processes such as electroplating or chemical plating. Through the gold bonding wire 810 and the gold-plated pad, the integrated control chip 800 can achieve a highly reliable and highly conductive electrical connection with the circuit interface 710.

[0056] Furthermore, the adjustable differential clock generator with a digital configuration interface also includes a top cover 900, which, together with the base 700, forms a sealed cavity. The wafer 110 and the integrated control chip 800 are sealed within this cavity. The top cover 900 and the base 700 are typically made of metal (such as aluminum alloy or stainless steel) or ceramic materials, and are connected by resistance welding. The wafer 110 and the integrated control chip 800 are bonded to the base 700 via die bonding, ensuring their stability and reliability. By sealing the wafer 110 and the integrated control chip 800 within the sealed cavity formed by the top cover 900 and the base 700, not only are the internal components protected from external environmental factors, but their anti-interference capability is also enhanced, improving signal integrity and accuracy.

[0057] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0058] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this utility model without departing from the spirit and scope of the embodiments of this utility model. Therefore, if these modifications and variations to the embodiments of this utility model fall within the scope of the claims of this utility model and their equivalents, then this utility model also intends to include these modifications and variations.

Claims

1. An adjustable differential clock generator with a digital configuration interface, characterized in that, include: A crystal oscillator for providing a reference clock signal at a fixed frequency; A phase-locked loop circuit, wherein the input terminal of the phase-locked loop circuit is electrically connected to the output terminal of the crystal oscillator, and the phase-locked loop circuit includes a programmable fractional frequency divider; An output frequency divider, wherein the input terminal of the output frequency divider is electrically connected to the output terminal of the phase-locked loop circuit; A differential output buffer, the input of which is electrically connected to the output of the output divider, the differential output buffer integrates multiple differential output modes, and the output of which is used to output differential output signals; A configuration circuit is provided, which is electrically connected to the fractional frequency divider, the output frequency divider, and the differential output buffer, respectively. A serial communication interface is connected to the configuration circuit. Frequency control data received by the serial communication interface is input to the fractional frequency divider through the configuration circuit. Output mode data received by the serial communication interface is input to the differential output buffer through the configuration circuit.

2. The adjustable differential clock generator with a digital configuration interface according to claim 1, characterized in that, The configuration circuit includes: A frequency control register, the output of which is electrically connected to the control terminals of the fractional frequency divider and the output frequency divider, respectively; An output mode controller, wherein the output terminal of the output mode controller is electrically connected to the mode selection terminal of the differential output buffer; Memory; The control interface is electrically connected to the serial communication interface, the memory, the frequency control register, and the output mode controller.

3. An adjustable differential clock generator with a digital configuration interface according to claim 2, characterized in that, The memory includes non-volatile memory and random access memory. The non-volatile memory is used to store configuration parameters, and the random access memory is used for real-time data interaction.

4. An adjustable differential clock generator with a digital configuration interface according to claim 1, characterized in that, The phase-locked loop circuit includes a phase detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator connected in sequence, and the fractional frequency divider is located in the feedback loop of the phase-locked loop circuit.

5. An adjustable differential clock generator with a digital configuration interface according to claim 1, characterized in that, The differential output buffer supports at least two of the following programmable output modes: LVDS, LVPECL, and HCSL.

6. An adjustable differential clock generator with a digital configuration interface according to any one of claims 1-5, characterized in that, The serial communication interface is an I²C interface.

7. An adjustable differential clock generator with a digital configuration interface according to any one of claims 1-5, characterized in that, The crystal oscillator includes a crystal wafer, which is electrically connected to the base via a conductive connection structure. The conductive connection structure includes electrodes and conductive adhesive disposed on the surface of the crystal wafer, used to transmit crystal vibration signals to the circuit interface of the base.

8. An adjustable differential clock generator with a digital configuration interface according to claim 7, characterized in that, The phase-locked loop circuit, differential output buffer, frequency control register, output mode controller, memory, control interface, and serial communication interface are integrated into an integrated control chip, which is electrically connected to the circuit interface.

9. An adjustable differential clock generator with a digital configuration interface according to claim 8, characterized in that, It also includes a top cover, which forms a sealed cavity with the base, and the crystal wafer and the integrated control chip are sealed within the sealed cavity.

Images