Printed circuit board with adjacent layer deviation test structure
By setting a concentric ring-shaped copper ring structure on the printed circuit board and using X-ray equipment to detect the projection of the copper ring, the problem of the inability to monitor the offset of adjacent layers in traditional methods is solved, realizing flexible and low-cost testing in any direction, and improving the integrity and testing efficiency of high-speed signal lines.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING SIFANG JIBAO AUTOMATION
- Filing Date
- 2025-04-10
- Publication Date
- 2026-05-19
AI Technical Summary
Traditional layer offset testing methods cannot effectively monitor the offset of adjacent layers, and existing technology equipment is bulky and lacks flexibility, making it impossible to meet the requirements for detecting the offset of adjacent layers in any direction.
A concentric ring-shaped copper ring structure is set on each layer of the printed circuit board. The overlapping of the copper ring projections is detected by X-ray equipment to achieve adjacent layer offset testing in any direction.
It enables non-destructive, low-cost, and flexible testing of adjacent layers in any direction, improving the integrity and testing efficiency of high-speed signal lines and reducing the footprint of the test structure.
Smart Images
Figure CN224265174U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of printed circuit board manufacturing, and in particular to a printed circuit board with an adjacent layer offset test structure. Background Technology
[0002] In the field of multilayer printed circuit board (PCB) design and manufacturing, overall layer offset data is typically monitored to avoid problems such as internal layer short circuits or insufficient insulation spacing caused by excessive layer offset. However, traditional layer offset testing methods cannot measure the deviation between adjacent layers. For high-speed PCBs, the offset between adjacent layers is of even greater concern to ensure the integrity of the reference plane of high-speed links. Traditional methods for monitoring adjacent layer offset can only be determined by slicing. However, slicing is destructive, costly, and inefficient; moreover, the slicing result only shows the offset between adjacent layers in one direction, which cannot meet the monitoring requirements for adjacent layer offset in any direction. This patent provides a PCB with a non-destructive, efficient, low-cost, and arbitrary-directional adjacent layer offset testing structure.
[0003] Existing technical documents describe multilayer PCB structures for detecting interlayer alignment. This involves setting up circular detection modules and using existing X-ray equipment to observe whether the detection modules on each inner layer are aligned, thereby determining whether the multilayer PCB 1 exhibits layer misalignment. However, existing technical documents require placing detection modules on every layer and at each of the four corners of the PCB when testing overall layer misalignment. Therefore, this method can only test a single value of overall layer misalignment, resulting in a large footprint and poor flexibility. Utility Model Content
[0004] To address the shortcomings of existing technologies, this invention provides a flexible, cost-effective printed circuit board with an adjacent layer offset testing structure that can test in any direction.
[0005] The present invention adopts the following technical solution.
[0006] A printed circuit board with an adjacent layer offset test structure includes a printed circuit board body and a test structure;
[0007] The printed circuit board body includes printed circuit board layers, and the multiple printed circuit board layers are arranged sequentially from top to bottom, and are respectively labeled as: layer 1, layer 2, layer 3...N layers;
[0008] On the printed circuit board, test structures are provided at the locations where adjacent layer offsets need to be tested and on each layer of the printed circuit board. The test structures are located at the same positions on each layer of the printed circuit board.
[0009] Preferably, the test structure is a copper ring, and the copper ring is shaped as a circular ring.
[0010] Preferably, the projections of the copper rings on each printed circuit board layer onto its vertical plane are concentric rings.
[0011] Preferably, the inner dimensions of the copper ring increase with the number of printed circuit board layers.
[0012] Preferably, the adjacent layer offset to be monitored is the difference between the inner dimension of the next copper ring and the outer dimension of the previous copper ring, forming the gap between the Nth copper ring and the (N-1)th copper ring.
[0013] Preferably, the values of the gaps can be set to the same or different values.
[0014] Preferably, the copper ring is made of an X-ray-proof material, and the overlapping of the projections of adjacent layers of the test structure is detected by connecting the printed circuit board to an X-ray device.
[0015] Preferably, if the projections of adjacent copper rings do not overlap, it indicates that the adjacent layer is smaller than the design value; if the projections of adjacent rings are tangent, it indicates that the adjacent layer is exactly equal to the design value; if the projections of adjacent rings overlap, it indicates that the adjacent layer is larger than the design value.
[0016] Preferably, when testing the adjacent layer offset in different regions, copper rings can be arranged separately in different regions, with the number of copper rings on each printed circuit board being greater than or equal to one.
[0017] Preferably, to test the offset between adjacent layers at different levels, copper rings can be arranged on different printed circuit board layers, with the centers of the copper rings in each layer aligned.
[0018] Compared with the prior art, the beneficial effects of this utility model include at least the following:
[0019] 1. Compared to testing the overall layer offset, testing the line deviation of adjacent layers of the printed circuit board for high-speed signals is more effective in ensuring the integrity of the reference ground plane of high-speed signal lines, preventing high-speed signal energy from radiating outside the reference ground plane, and improving the quality of high-speed transmission signals.
[0020] 2. It can be flexibly deployed in any location, especially in high-speed signal areas with strict requirements for adjacent layer offset. It allows for individual testing of the required adjacent layer offset in the area, and different values can be set, improving flexibility and overcoming the limitations of traditional methods that can only test the overall deviation of a single fixed value.
[0021] 3. It can test the adjacent layer deviation of one or two layers individually, instead of testing every layer, thereby reducing the floor space occupied by the test structure. At the same time, the test modules can be placed individually or in multiples according to product needs. For overall layer deviation, four modules are usually placed at the four corners. Using non-destructive optical testing methods, it can also perform adjacent layer deviation testing in any direction, reducing costs and improving testing efficiency. Attached Figure Description
[0022] Figure 1This is a schematic diagram of the vertical projection of the adjacent layer offset test structure of this utility model.
[0023] Figure 2 This is an X-ray projection of the adjacent layers of this utility model that are qualified.
[0024] Figure 3 This is an X-ray projection of the adjacent layers of this utility model that are not properly offset.
[0025] Figure 4 This is a schematic diagram of each printed layer of this utility model.
[0026] In the diagram: 1. First layer copper ring; 2. Second layer copper ring; 3. Third layer copper ring; 4. First layer; 5. Second layer; 6. Nth layer; 7. Copper ring; 8. Printed circuit board; N-1. N-1th layer copper ring; N. Nth layer copper ring; a2. Gap between the second layer copper ring and the first layer copper ring; aN. Gap between the Nth layer copper ring and the N-1th layer copper ring. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The embodiments described in this application are merely some embodiments of this utility model, and not all embodiments. Based on the spirit of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0028] like Figure 4 As shown, an embodiment of this utility model discloses a printed circuit board with an adjacent layer offset test structure. The printed circuit board 8 includes multiple printed circuit board layers, which are arranged sequentially from top to bottom and are respectively labeled as: layer 1, layer 2, layer 3... layer N. A copper ring 7 is provided on each printed circuit board. The shape of the copper ring 7 is preferably, but not limited to, a circular ring. On the printed circuit board 8, a test structure is provided at the position where the adjacent layer offset needs to be tested and on each layer of the printed circuit board. The test structure is set at the same position on each layer of the printed circuit board.
[0029] Test structures for adjacent layer offsets, such as Figure 1 As shown, a copper ring 7 is designed for each layer of the printed circuit board where the adjacent layer offset is to be tested. The centers of the copper rings 7 in each layer are aligned, i.e., they are set as concentric rings. The inner dimension of the copper ring 7 increases with the number of layers. The adjacent layer offset to be monitored is the difference between the inner dimension of the next layer copper ring 7 and the outer dimension of the previous layer copper ring 7. For example, the gap a2 between the second layer copper ring and the first layer copper ring to the gap aN between the Nth layer copper ring and the (N-1)th layer copper ring. The specific values can be set as needed. The values can be the same or different. The projection of each layer copper ring 7 on the vertical board surface is a concentric ring.
[0030] Example 1:
[0031] After the printed circuit board is processed, the concentric rings should theoretically be concentric. However, due to the existence of adjacent layer offsets, the concentric rings are no longer completely concentric. At this time, by detecting the projection of the adjacent layer offset test structure using X-RAY equipment, it can be determined whether the adjacent layer offset exceeds the design value.
[0032] When adjacent copper ring projections do not overlap, such as Figure 2 The projections of the copper rings between the first layer (copper ring 1) and the second layer (copper ring 2) do not overlap, indicating that the adjacent layers are smaller than the design value, which meets the requirements.
[0033] When the projections of adjacent annexes are tangent, such as Figure 2 The projection of the copper ring between the (N-1)th layer and the Nth layer is tangent, indicating that the offset of the adjacent layer is exactly equal to the design value, which meets the requirements.
[0034] When adjacent annular projections have overlapped, such as Figure 3 The projections of the copper rings in the second layer (2) and the third layer (3) overlap, indicating that the adjacent layers are larger than the design value and do not meet the requirements.
[0035] Example 2:
[0036] When designing a printed circuit board, if monitoring is required in different areas, copper rings 7 can be arranged separately in different areas. Copper rings 7 are designed at the layers that need to be tested, with one or more on each printed circuit board. The inner size of the copper rings 7 increases with the number of layers, eventually forming a gap aN between the Nth layer copper ring and the (N-1)th layer copper ring. The gaps can be the same or different.
[0037] In each region, copper rings 7 with progressively increasing inner dimensions are arranged separately. The projection of the adjacent layer offset test structure is detected by X-RAY equipment to determine whether the adjacent layer offset exceeds the design value.
[0038] For each region, design partitions for copper ring 7. In this example, partition 1 and partition 2 are set. The two partitions do not overlap. Determine whether the adjacent layer offset of partition 1 and partition 2 is qualified separately.
[0039] When the projections of adjacent copper rings in partition one do not overlap, such as Figure 2 The projections of the copper rings in the first layer (copper ring 1) and the second layer (copper ring 2) do not overlap, indicating that the adjacent layers are slightly smaller than the design value, which meets the requirements. When the projections of adjacent rings are tangent in partition two, as shown... Figure 2 The projection of the copper rings in the (N-1)th layer and the Nth layer is tangent, indicating that the adjacent layer offset is exactly equal to the design value, which meets the requirements. The adjacent layer offsets in sections one and two both meet the design standards and are considered to have passed the adjacent layer offset test.
[0040] When the projections of adjacent copper rings in partition one do not overlap, such as Figure 2 The projections of the copper rings in the first layer (copper ring 1) and the second layer (copper ring 2) do not overlap, indicating that the adjacent layers are slightly smaller than the design value, which meets the requirements. However, when the projections of adjacent rings in section two overlap, such as... Figure 3 The overlapping projections of copper rings 2 and 3 in the second and third layers indicate that the adjacent layer deviations are greater than the design values, failing to meet the requirements. If any deviation of adjacent layers in zones one and two does not meet the design standards, the adjacent layer deviation test is considered unqualified.
[0041] Compared with the prior art, the beneficial effects of this utility model include at least the following:
[0042] 1. Compared to testing the overall layer offset, testing the line deviation of adjacent layers of the printed circuit board for high-speed signals is more effective in ensuring the integrity of the reference ground plane of high-speed signal lines, preventing high-speed signal energy from radiating outside the reference ground plane, and improving the quality of high-speed transmission signals.
[0043] 2. It can be flexibly deployed in any location, especially in high-speed signal areas with strict requirements for adjacent layer offset. It allows for individual testing of the required adjacent layer offset in the area, and different values can be set, improving flexibility and overcoming the limitations of traditional methods that can only test the overall deviation of a single fixed value.
[0044] 3. It can test the adjacent layer deviation of one or two layers individually, instead of testing every layer, thereby reducing the floor space occupied by the test structure. At the same time, the test modules can be placed individually or in multiples according to product needs. For overall layer deviation, four modules are usually placed at the four corners. Using non-destructive optical testing methods, it can also perform adjacent layer deviation testing in any direction, reducing costs and improving testing efficiency.
[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and not to limit it. Although the utility model has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this utility model. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this utility model should be covered within the protection scope of the claims of this utility model.
Claims
1. A printed circuit board with an adjacent layer offset test structure, characterized in that: Includes printed circuit board (8) and test structure; The printed circuit board (8) includes printed circuit board layers, and the multiple printed circuit board layers are arranged sequentially from top to bottom, and are respectively denoted as: layer 1, layer 2, layer 3...N layers; On the printed circuit board (8), test structures are provided at the positions where adjacent layer offsets need to be tested and on each layer of the printed circuit board, and the test structures are provided at the same positions on each layer of the printed circuit board.
2. A printed circuit board with an adjacent layer offset test structure according to claim 1, characterized in that: The test structure is a copper ring (7), and the copper ring (7) is shaped as a circular ring.
3. A printed circuit board with an adjacent layer offset test structure according to claim 2, characterized in that: The projection of the copper rings (7) on each printed circuit board layer onto its vertical plane is a concentric ring.
4. A printed circuit board with an adjacent layer offset test structure according to claim 3, characterized in that: The inner dimensions of the copper ring (7) increase with the number of printed circuit board layers.
5. A printed circuit board with an adjacent layer offset test structure according to claim 4, characterized in that: The adjacent layer offset to be monitored is the difference between the inner dimension of the next copper ring (7) and the outer dimension of the previous copper ring (7), forming the gap (aN) between the Nth copper ring and the N-1th copper ring.
6. A printed circuit board with an adjacent layer offset test structure according to claim 5, characterized in that: The value of the gap (aN) can be set to the same or different values.
7. A printed circuit board with an adjacent layer offset test structure according to claim 2, characterized in that: The copper ring (7) is made of an X-ray-proof material. It is connected to the printed circuit board via an X-ray device to detect the overlap of the projections of adjacent layers of the test structure.
8. A printed circuit board with an adjacent layer offset test structure according to claim 7, characterized in that: If the projections of adjacent copper rings do not overlap, it means that the adjacent layers are smaller than the design value; if the projections of adjacent rings are tangent, it means that the adjacent layers are exactly equal to the design value; if the projections of adjacent rings overlap, it means that the adjacent layers are larger than the design value.
9. A printed circuit board with an adjacent layer offset test structure according to claim 1, characterized in that: To test the adjacent layer offset in different regions, copper rings (7) can be arranged separately in different regions, and the number of copper rings (7) on each printed circuit board is greater than or equal to one.
10. A printed circuit board with an adjacent layer offset test structure according to claim 1, characterized in that: To test the offset between adjacent layers at different levels, copper rings (7) can be arranged on different printed circuit board layers, with the centers of the copper rings (7) aligned in each layer.