CAN bus aftermarket instrument operating system

Abstract

The utility model discloses a CAN bus retrofit instrument working system, which includes a CPU. The display data output end of the CPU is connected to the display data input end of the OLED screen, and the asynchronous serial data transceiver end of the CPU is connected to the asynchronous serial data transceiver end of the MCU. The CAN bus data transceiver end of the MCU is connected to the CAN bus data transceiver end of the CAN transceiver, and is connected to the vehicle head unit of the automobile through the data transceiver end of the CAN transceiver by means of a connector. It can be connected to the vehicle head unit of the automobile through the CAN bus, improving the convenience of retrofit and after-installation.

Description

Technical Field

[0001] This utility model relates to the field of automotive instrument technology, specifically to a CAN bus aftermarket instrument system. Background Technology

[0002] Aftermarket instrument clusters refer to dashboard systems that are installed or modified by the user after the car leaves the factory, usually to enhance the vehicle's functionality, aesthetics, or technological feel. However, due to the different interface standards of original instrument clusters from different car manufacturers, incompatibility issues between the instrument cluster and the vehicle's infotainment system are very common during the modification process. Therefore, there is an urgent need for an aftermarket instrument cluster that can be widely compatible with different car models. Utility Model Content

[0003] This utility model aims to solve the technical problems existing in the prior art, and innovatively proposes a CAN bus aftermarket instrument working system, which can connect with the car's infotainment system through the CAN bus, improving the convenience of modification and aftermarket installation.

[0004] To achieve the above objectives, this utility model provides a CAN bus aftermarket instrument operating system, including a CPU, a CPU display data output terminal connected to an OLED screen display data input terminal, a CPU asynchronous serial data transceiver terminal connected to an MCU asynchronous serial data transceiver terminal, and an MCU CAN bus data transceiver terminal connected to a CAN transceiver CAN bus data transceiver terminal, and connected to the vehicle's infotainment system via a connector through the CAN transceiver data transceiver terminal.

[0005] The above solution also includes a power supply module, which comprises a first DC-DC converter voltage input terminal connected to the battery output power supply terminal, one end of capacitor C45, one end of capacitor C46, ​​one end of capacitor C47, and one end of capacitor C48. The other ends of capacitors C45, C46, ​​C47, and C48 are all connected to power ground. The enable terminal of the first DC-DC converter is connected to one end of resistor R38 and one end of resistor R39. The other end of resistor R38 is connected to the battery output power supply terminal. The power supply voltage of the first DC-DC converter is connected to one end of capacitor C44. The other ends of capacitor C44, resistor R39, and the ground terminal of the first DC-DC converter are connected to the first DC-DC converter. Connect the power supply to ground. The BOOT terminal of the first DC-DC converter is connected to one end of resistor R34. The other end of resistor R34 is connected to one end of capacitor C38. The other end of capacitor C38 is connected to the SW terminal of the first DC-DC converter and one end of inductor L2. The other end of inductor L2 outputs a 3.3V voltage and is connected to one end of resistor R35, one end of capacitor C40, one end of capacitor C41, one end of capacitor C42, and one end of capacitor C43. The feedback terminal of the first DC-DC converter is connected to the other end of resistor R35 and one end of resistor R36. The other ends of resistor R36, capacitor C40, capacitor C41, capacitor C42, and capacitor C43 are all connected to the power supply ground.

[0006] The power supply module also includes a second DC-DC converter whose voltage input terminal is connected to the other end of inductor L2, one end of capacitor C31, one end of capacitor C32, and one end of resistor R28. The other ends of capacitors C31 and C32, the ground terminal of the second DC-DC converter, and the MODE terminal of the second DC-DC converter are all connected to power ground. The enable terminal of the second DC-DC converter is connected to one end of resistor R102 and the MCU SOC 1.3V power supply enable terminal. The PG terminal of the second DC-DC converter is the SOC 3.3V power supply enable terminal. One end of resistor R29 is connected to one end of inductor L1. The other end of inductor L1 outputs a 1.3V voltage and is connected to the other end of resistor R29, one end of resistor R31, one end of capacitor C33, one end of capacitor C34, and one end of capacitor C35. The feedback terminal of the second DC-DC converter is connected to the other end of capacitor C33, the other end of resistor R31, and one end of resistor R30. The ground terminal of the second DC-DC converter, the other end of resistor R30, the other end of capacitor C34, and the other end of capacitor C35 are all connected to the power supply ground.

[0007] The second DC-DC converter's PG terminal is connected to one end of resistor R44. The other end of resistor R44 is connected to one end of capacitor C51 and the base of transistor Q2. The other end of capacitor C51 and the emitter of transistor Q2 are both connected to power supply ground. The collector of transistor Q2 is connected to one end of resistor R40. The other end of resistor R40 is connected to the gate of MOSFET Q1, one end of resistor R41, and one end of capacitor C49. The source of transistor Q1 is connected to the other end of resistor R41, the other end of capacitor C49, and the other end of inductor L2. The drain of transistor Q1 is the SOC 3.3V power supply terminal, used to power the CPU, and is connected to one end of resistor R42 and one end of capacitor C50. The other ends of resistor R42 and capacitor C50 are both connected to power supply ground.

[0008] The power supply module also includes a low-dropout linear regulator. The voltage input terminal of the low-dropout linear regulator is connected to the other end of inductor L2 and one end of capacitor C36. The enable terminal of the low-dropout linear regulator is connected to the CPUOLED 1.8V power supply enable terminal and one end of resistor R33. The ground terminal of the low-dropout linear regulator, the other end of resistor R33, and the other end of capacitor C36 are all connected to the power supply ground. The voltage output terminal of the low-dropout linear regulator outputs a 1.8V voltage to power the OLED screen and is connected to one end of capacitor C37. The other end of capacitor C37 is connected to the power supply ground.

[0009] The power supply module also includes a linear regulator. The voltage input terminal of the linear regulator is connected to the battery output power supply terminal, one end of capacitor C84, and one end of capacitor C85. The other ends of capacitor C84 and C85 are both connected to the power supply ground. The enable terminal of the low dropout linear regulator is connected to the MCU CAN power supply enable terminal and one end of resistor R66. The ground terminal of the low dropout linear regulator and the other end of resistor R66 are both connected to the power supply ground. The voltage output terminal of the low dropout linear regulator outputs a 5V voltage to power the CAN transceiver and is connected to one end of capacitor C87. The other end of capacitor C87 is connected to the power supply ground.

[0010] In the above scheme: the power supply module further includes an OLED power supply enable circuit. The OLED power supply enable circuit includes a resistor R45, one end of which is connected to the CPU OLED 3.3V power supply enable signal output terminal. The other end of the resistor R45 is connected to one end of the resistor R47, one end of the capacitor C53, and the base of the transistor Q3. The other end of the resistor R47, the other end of the capacitor C51, and the emitter of the transistor Q3 are all connected to the power supply ground. The collector of the transistor Q3 is connected to one end of the resistor R48. The other end of the resistor R48 is connected to the gate of the field-effect transistor Q4, one end of the resistor R46, and one end of the capacitor C52. The source of the transistor Q4 is connected to the other end of the resistor R46, the other end of the capacitor C52, and the other end of the inductor L2. The drain of the transistor Q4 is the OLED 3.3V power supply terminal, used to power the OLED screen, and is connected to one end of the resistor R49 and one end of the capacitor C54. The other end of the resistor R49 and the other end of the capacitor C54 are both connected to the power supply ground.

[0011] The power supply module also includes a battery sampling circuit, which includes a resistor R51. One end of the resistor R51 is connected to the MCU battery sampling signal output terminal. The other end of the resistor R51 is connected to one end of the resistor R53, one end of the capacitor C63, and the base of the transistor Q5. The other ends of the resistor R53, the other end of the capacitor C63, and the emitter of the transistor Q5 are all connected to the power supply ground. The collector of the transistor Q5 is connected to one end of the resistor R54. The other end of the resistor R54 is connected to the base of the transistor Q6, one end of the resistor R52, and one end of the capacitor C62. The emitter of the transistor Q6 is connected to the other ends of the resistor R52, the other end of the capacitor C62, and the battery output power supply terminal. The collector of the transistor Q6 is connected to one end of the resistor R56 and one end of the capacitor C67. The other end of the resistor R56 is connected to one end of the resistor R57, one end of the capacitor C91, and the MCU battery analog signal terminal. The other ends of the capacitor C67, the other ends of the resistor R57, and the other ends of the capacitor C91 are all connected to the power supply ground.

[0012] In the above scheme: the MCU asynchronous serial data receiving end is connected to one end of resistor R97 and the CPU asynchronous serial data transmitting end, and the other end of resistor R97 is connected to the other end of inductor L2; the MCU asynchronous serial data transmitting end is connected to one end of resistor R96 and the CPU asynchronous serial data receiving end; the other end of resistor R96 is connected to the other end of inductor L2; the MCU PTB_2 end is connected to one end of resistor R63 and the CPU first input / output detection end, and the other end of resistor R63 is connected to the other end of inductor L2; the MCU PTB_3 end is connected to one end of resistor R62 and the CPU second input / output detection end, and the other end of resistor R62 is connected to the other end of inductor L2.

[0013] The output terminal of the MCU oscillator is connected to one end of resistor R64, the first end of crystal Y3, and one end of capacitor C82. The other end of capacitor C82 and the normally open terminal of crystal Y3 are both connected to the power supply ground. The input terminal of the MCU oscillator is connected to the other end of resistor R64, the second end of crystal Y3, and one end of capacitor C83. The other end of capacitor C83 is connected to the power supply ground.

[0014] The MCU's internal operating voltage terminal is connected to one end of capacitor C81, one end of capacitor C80, one end of capacitor C78, ​​one end of capacitor C79, one end of capacitor C76, and one end of ferrite bead FB1. The other end of ferrite bead FB1 is connected to the other end of inductor L2. The MCU's common ground voltage terminal, the other ends of capacitors C81, C80, C78, ​​C79, and C76 are all connected to the power supply ground.

[0015] The MCUCAN enable control terminal is connected to the CAN transceiver enable control signal receiving terminal. The MCUCAN receiving terminal is connected to one end of resistor R72. The other end of resistor R72 is connected to the CAN transceiver CAN transmitting terminal. The MCUCAN transmitting terminal is connected to one end of resistor R71. The other end of resistor R71 is connected to the CAN transceiver CAN receiving terminal.

[0016] The MCUSWD clock terminal is connected to the third terminal of terminal block P8 and one end of resistor R59. The other end of resistor R59 is connected to power ground. The MCUSWD data terminal is connected to the first terminal of terminal block P8 and one end of resistor R58. The other end of resistor R58 is connected to the other end of inductor L2. The MCUSWD reset terminal is connected to one end of resistor R60, one end of resistor R61, and one end of capacitor R74. The other end of resistor R61 and the second terminal of terminal block P8 are connected to the other end of inductor L2. The sixth terminal of terminal block P8 and the other end of capacitor R74 are both connected to power ground.

[0017] In the above scheme: the 3.3V positive power supply terminal of the CPU power unit is connected to the drain of transistor Q1, one end of capacitor C20, one end of capacitor C19, one end of capacitor C18, one end of capacitor C17, and one end of capacitor C16. The other ends of capacitors C20, C19, C18, C17, and C16 are all connected to power ground. The 3.3V analog circuit power supply terminal of the CPU power unit is connected to one end of resistor R7, one end of capacitor C14, and one end of capacitor C15. The other end of resistor R7 is connected to the drain of transistor Q1. The CPU power unit 3.3V... The PLL power supply terminal is connected to one end of resistor R6 and one end of capacitor C13. The other end of resistor R6 is connected to the drain of transistor Q1. The other ends of capacitors C13, C14, and C15 are all connected to power ground. The CPU power unit operating voltage terminal is connected to the other end of inductor L1, one end of capacitor C12, one end of capacitor C11, one end of capacitor C10, and one end of capacitor C9. The other ends of capacitors C12, C11, C10, and C9 are all connected to power ground. The CPU power unit 1.2V analog power supply terminal is connected to one end of capacitor C8 and one end of capacitor C7. The other ends of capacitors C8 and C7 are both connected to power ground.

[0018] The CPU power supply unit's SDVREF terminal is connected to one end of resistor R2, one end of resistor R1, and one end of capacitor C5. The other ends of resistor R1 and capacitor C5 are both connected to power ground. The other end of resistor R2 is connected to one end of resistor R27, and the other end of resistor R27 is connected to the 1.8VDDR terminal of the CPU power supply unit. The CPU power supply unit's AVDD_RTC terminal is connected to one end of resistor R3 and one end of capacitor C6. The other end of resistor R3 is connected to the drain of transistor Q1. The CPU power supply unit's AVSS_RTC terminal is connected to one end of resistor R4. The CPU power supply unit's pad port, the other end of resistor R4, and the other end of capacitor C6 are all connected to power ground.

[0019] In the above scheme: the spare serial port transmitting end of the CPU serial communication unit is connected to one end of resistor R15 and one end of resistor R19. The other end of resistor R15 is connected to the drain of transistor Q1. One end of resistor R19 is connected to one end of diode ESD4 and the second end of spare terminal block P5. The other end of diode ESD4 and the first end of spare terminal block P5 are both connected to power ground. The printing serial port receiving end of the CPU serial communication unit is connected to one end of resistor R16 and one end of resistor R20. The other end of resistor R16 is connected to the drain of transistor Q1. One end of resistor R20 is connected to one end of diode ESD3 and the third end of spare terminal block P5. The other end of diode ESD3 is connected to power ground.

[0020] The first BOOT terminal of the CPU System unit is connected to one end of resistor R8 and the first end of terminal block P1. The other end of resistor R8 is connected to the drain of transistor Q1. The second end of terminal block P1 is connected to power ground. The second BOOT terminal of the CPU System unit is connected to one end of resistor R9 and the first end of terminal block P2. The other end of resistor R9 is connected to the drain of transistor Q1. The second end of terminal block P2 is connected to power ground. The oscillator input terminal of the CPU System unit is connected to one end of resistor R12, the first end of crystal Y1, and one end of capacitor C24. The other end of capacitor C24 and the normally open end of crystal Y1 are both connected to power ground. The oscillator output terminal of the CPU System unit is connected to the other end of resistor R12, the second end of crystal Y1, and one end of capacitor C25. The other end of capacitor C25 and the normally open end of crystal Y3 are both connected to power ground.

[0021] The CPU System Unit debug port test clock terminal is connected to one end of resistor R95. The other end of resistor R95 is connected to one end of resistor R84 and the sixth terminal of terminal block P3, and is connected to an external debugging device through terminal block P3. The other end of resistor R84 is connected to the cathode of diode D4, and the anode of diode D4 is connected to the drain of transistor Q1. The CPU System Unit debug port test data output terminal is connected to one end of resistor R94. The other end of resistor R94 is connected to one end of resistor R85 and the fifth terminal of terminal block P3, and the other end of resistor R85 is connected to the cathode of diode D4. The CPU System Unit debug port test data input terminal is connected to one end of resistor R93. The other end of resistor R93 is connected to one end of resistor R86 and the fourth terminal of terminal block P3, and the other end of resistor R86 is connected to the cathode of diode D4. The CPU System Unit debug port test mode selection terminal is connected to one end of resistor R92. The other end of resistor R92 is connected to one end of resistor R87 and the third terminal of terminal block P3, and the other end of resistor R87 is connected to the cathode of diode D4. The test reset terminal of the System unit debug port is connected to one end of resistor R91. The other end of resistor R91 is connected to the second terminal of terminal block P3, one end of resistor R89, and the negative terminal of diode D4. The other end of resistor R89 ​​is connected to power ground. The seventh terminal of terminal block P3 is the system reset switch terminal, connected to one end of resistor R83. The other end of resistor R83 is connected to the negative terminal of diode D4. The eighth terminal of terminal block P3 is the clock coordination terminal, connected to one end of resistor R90. The other end of resistor R90 and the ninth terminal of terminal block P3 are connected to power ground.

[0022] In the above scheme: the CPU memory unit's chip select signal terminal is connected to the memory chip select signal terminal and one end of resistor R24, the other end of resistor R24 ​​is connected to the memory power supply voltage terminal; the CPU memory unit's clock terminal is connected to the memory clock terminal; the CPU memory unit's first storage signal terminal is connected to the memory input terminal; the CPU memory unit's second storage signal terminal is connected to the memory output terminal and one end of resistor R25, the other end of resistor R25 is connected to power ground; the CPU memory unit's third storage signal terminal is connected to the memory write-protect input terminal and one end of resistor R22, the resistor R24... 2. The other end is connected to the memory power supply voltage terminal. The fourth storage signal terminal of the CPU storage unit is connected to the memory reset terminal and one end of resistor R23. The other end of resistor R23 is connected to the memory power supply voltage terminal. The memory power supply voltage terminal is connected to one end of ferrite bead FB2, one end of capacitor C26, and one end of capacitor C27. The other end of ferrite bead FB2 is connected to the negative terminal of diode D1 and one end of capacitor C28. The positive terminal of diode D1 is connected to the drain of transistor Q1. The memory ground terminal, the other end of capacitor C26, the other end of capacitor C27, and the other end of capacitor C28 are all connected to the power supply ground.

[0023] In the above scheme: the OLED power setting output terminal of the CPU display unit is connected to the OLED screen power setting input terminal; the OLED reset output terminal of the CPU display unit is connected to the OLED screen reset input terminal; the OLED screen synchronization signal output terminal is connected to the OLED synchronization signal input terminal of the CPU display unit; the positive output terminal of the first channel of display data of the CPU display unit is connected to the positive input terminal of the first channel of display data of the OLED screen; the negative output terminal of the first channel of display data of the CPU display unit is connected to the negative input terminal of the first channel of display data of the OLED screen; the positive output terminal of the second channel of display data of the CPU display unit is connected to the positive input terminal of the second channel of display data of the OLED screen; the negative output terminal of the second channel of display data of the CPU display unit is connected to the negative input terminal of the second channel of display data of the OLED screen; the positive output terminal of the clock channel of display data of the CPU display unit is connected to the positive input terminal of the clock channel of display data of the OLED screen; the negative output terminal of the clock channel of display data of the CPU display unit is connected to the negative input terminal of the clock channel of display data of the OLED screen.

[0024] In the above scheme: the OLED screen is connected via a terminal block FPC1. The OLED screen also includes an OLED power module. The LX3 terminal of the OLED power module is connected to one end of inductor L5, and the other end of inductor L5 is connected to the other end of inductor L2. The LX1 terminal of the OLED power module is connected to one end of inductor L4, and the other end of inductor L4 is connected to the other end of inductor L2. The LX2 terminal of the OLED power module is connected to one end of inductor L3, and the other end of inductor L3 is connected to ground. The PVIN terminal of the OLED power module is connected to one end of capacitor C58, one end of capacitor C60, and one end of inductor L2. The AVIN terminal of the OLED power module is connected to one end of capacitor C59, one end of capacitor C61, and one end of inductor L2. The ground terminal of the OLED power module, the other end of capacitor C59, the other end of capacitor C61, the other end of capacitor C58, and the other end of capacitor C60 are all connected to ground. The VO3 terminal of the OLED power module is connected to... Connect one end of capacitor C55, one end of capacitor C70, and the terminal block FPC1AVDD. The other ends of capacitor C55, capacitor C70, and OLED power module PGND2 are all connected to power ground. Connect one end of capacitor C56, one end of capacitor C98, one end of capacitor C68, and terminal block FPC1ELVDD. The other ends of capacitor C56, capacitor C98, capacitor C68, and OLED power module PGND1 are all connected to power ground. Connect one end of capacitor C57, one end of capacitor C100, capacitor C69, and terminal block FPC1ELVSS. The other ends of capacitor C57, capacitor C100, and capacitor C69 are all connected to power ground. Connect terminal block FPC1IDVCC to the voltage output terminal of the low dropout linear regulator. Connect terminal block FPC1VCI to the drain of transistor Q4.

[0025] In the above scheme: the first end of the connector is connected to one end of transient voltage suppression diode TSV2, one end of capacitor C64, and the positive terminal of diode D3; the negative terminal of diode D3 is connected to one end of inductor L6, one end of capacitor C65, and one end of capacitor C77; the other end of inductor L6 is connected to the battery output power supply terminal, one end of capacitor C66, and one end of capacitor C86; the other ends of transient voltage suppression diode TSV2, capacitor C64, capacitor C65, capacitor C77, capacitor C66, capacitor C86, and the second end of the connector are all connected to power ground.

[0026] The fourth terminal of the connector is connected to one end of capacitor C89, one end of resistor R68, one end of resistor R70, and the first terminal of electrostatic discharge (ESD) diode ESD5. The other end of resistor R70 is connected to the high-level terminal of the CAN transceiver. The other end of resistor R68 is connected to one end of capacitor C90. The other ends of capacitor C89, capacitor C90, and ESD diode ESD5 are all connected to power ground. The fifth terminal of the connector is connected to one end of capacitor C88, one end of resistor R67, one end of resistor R69, and the third terminal of diode ESD5. The other end of resistor R69 is connected to the low-level terminal of the CAN transceiver. The other end of resistor R67 is connected to one end of capacitor C90. The other end of capacitor C88 is connected to power ground.

[0027] In summary, the beneficial effects of this invention are: it enables connection to the vehicle's infotainment system via the CAN bus. Compared to traditional analog signals, the CAN bus offers higher compatibility, is plug-and-play, and can be directly connected to the original vehicle's OBD-II diagnostic port or CAN gateway without requiring additional conversion equipment. Furthermore, the CAN bus has high anti-interference capabilities, using differential signals to cancel common-mode noise, improving data transmission efficiency and ensuring accurate instrument display. In addition, especially in retrofitting applications, no additional wiring is needed; the original vehicle's CAN wiring harness can be used directly, avoiding wiring and improving installation efficiency. Attached Figure Description

[0028] Figure 1 This is a system diagram of this utility model.

[0029] Figure 2 This is the circuit diagram for the connector.

[0030] Figure 3 This is the circuit diagram of the battery sampling circuit.

[0031] Figure 4 This is the circuit diagram of the first DC-DC converter.

[0032] Figure 5 This is the circuit diagram of the second DC-DC converter.

[0033] Figure 6 This is the circuit diagram of the SOC power supply enable circuit.

[0034] Figure 7 This is the circuit diagram of the OLED power supply enable circuit.

[0035] Figure 8 This is the circuit diagram of a low-dropout linear regulator.

[0036] Figure 9 This is the circuit diagram of a linear regulator.

[0037] Figure 10 This is the circuit diagram of the OLED power module.

[0038] Figure 11 This is the circuit diagram for terminal block FPC1.

[0039] Figure 12 This is the circuit diagram of an MCU.

[0040] Figure 13 This is the circuit diagram for terminal block P8.

[0041] Figure 14 This is a circuit diagram of a CAN transceiver.

[0042] Figure 15 This is the circuit diagram of the CPU power supply unit.

[0043] Figure 16 This is the circuit diagram of the CPU System unit.

[0044] Figure 17 This is a circuit diagram of the CPU serial communication unit.

[0045] Figure 18 This is a circuit diagram of the CPU's memory unit. Detailed Implementation

[0046] The present invention will be further described below with reference to embodiments and accompanying drawings:

[0047] like Figures 1 to 18 As shown, a CAN bus aftermarket instrument cluster system includes a CPUU1. The CPUU1 display data output terminal is connected to the OLED screen display data input terminal. The CPUU1 asynchronous serial data transceiver terminal is connected to the MCUU7 asynchronous serial data transceiver terminal. The MCUU7 CAN bus data transceiver terminal is connected to the CAN transceiver U9 CAN bus data transceiver terminal, and is connected to the car's infotainment system via connector P7 through the CAN transceiver U9 data transceiver terminal.

[0048] It also includes a power supply module, which includes a first DC-DC converter U3 whose voltage input terminal is connected to the battery output power supply terminal, one end of capacitor C45, one end of capacitor C46, ​​one end of capacitor C47, and one end of capacitor C48. The other ends of capacitors C45, C46, ​​C47, and C48 are all connected to the power ground. The enable terminal of the first DC-DC converter U3 is connected to one end of resistor R38 and one end of resistor R39. The other end of resistor R38 is connected to the battery output power supply terminal. The power supply voltage of the first DC-DC converter U3 is connected to one end of capacitor C44. The other ends of capacitor C44, resistor R39, and the ground terminal of the first DC-DC converter U3 are connected to... Connect the power supply to ground. The BOOT terminal of the first DC-DC converter U3 is connected to one end of resistor R34. The other end of resistor R34 is connected to one end of capacitor C38. The other end of capacitor C38 is connected to the SW terminal of the first DC-DC converter U3 and one end of inductor L2. The other end of inductor L2 outputs a 3.3V voltage and is connected to one end of resistor R35, one end of capacitor C40, one end of capacitor C41, one end of capacitor C42, and one end of capacitor C43. The feedback terminal of the first DC-DC converter U3 is connected to the other end of resistor R35 and one end of resistor R36. The other ends of resistor R36, capacitor C40, capacitor C41, capacitor C42, and capacitor C43 are all connected to the power supply ground.

[0049] The power supply module also includes a second DC-DC converter U4 whose voltage input terminal is connected to the other end of inductor L2, one end of capacitor C31, one end of capacitor C32, and one end of resistor R28. The other ends of capacitor C31 and C32, the ground terminal of the second DC-DC converter U4, and the MODE terminal of the second DC-DC converter U4 are all connected to the power ground. The enable terminal of the second DC-DC converter U4 is connected to one end of resistor R102 and the SOC 1.3V power supply enable terminal of MCUU7. The PG terminal of the second DC-DC converter U4 is the SOC 3.3V power supply enable terminal. The first terminal is connected to one end of resistor R29. The second DC-DC converter U4SW terminal is connected to one end of inductor L1. The other end of inductor L1 outputs a 1.3V voltage and is connected to the other end of resistor R29, one end of resistor R31, one end of capacitor C33, one end of capacitor C34, and one end of capacitor C35. The feedback terminal of the second DC-DC converter U4 is connected to the other end of capacitor C33, the other end of resistor R31, and one end of resistor R30. The ground terminal of the second DC-DC converter U4, the other end of resistor R30, the other end of capacitor C34, and the other end of capacitor C35 are all connected to the power supply ground.

[0050] The second DC-DC converter U4PG terminal is connected to one end of resistor R44. The other end of resistor R44 is connected to one end of capacitor C51 and the base of transistor Q2. The other end of capacitor C51 and the emitter of transistor Q2 are both connected to the power supply ground. The collector of transistor Q2 is connected to one end of resistor R40. The other end of resistor R40 is connected to the gate of MOSFET Q1, one end of resistor R41 and one end of capacitor C49. The source of transistor Q1 is connected to the other end of resistor R41, the other end of capacitor C49 and the other end of inductor L2. The drain of transistor Q1 is the SOC 3.3V power supply terminal, used to power CPUU1, and is connected to one end of resistor R42 and one end of capacitor C50. The other ends of resistor R42 and capacitor C50 are both connected to the power supply ground.

[0051] The power supply module also includes a low-dropout linear regulator U5. The voltage input terminal of the low-dropout linear regulator U5 is connected to the other end of inductor L2 and one end of capacitor C36. The enable terminal of the low-dropout linear regulator U5 is connected to the OLED 1.8V power supply enable terminal of CPUU1 and one end of resistor R33. The ground terminal of the low-dropout linear regulator U5, the other end of resistor R33, and the other end of capacitor C36 are all connected to the power supply ground. The voltage output terminal of the low-dropout linear regulator U5 outputs a 1.8V voltage to power the OLED screen and is connected to one end of capacitor C37. The other end of capacitor C37 is connected to the power supply ground.

[0052] The power supply module also includes a linear regulator U8. The voltage input terminal of the linear regulator U8 is connected to the battery output power supply terminal, one end of capacitor C84, and one end of capacitor C85. The other ends of capacitor C84 and C85 are both connected to the power supply ground. The enable terminal of the low dropout linear regulator U5 is connected to the CAN power supply enable terminal of MCU U7 and one end of resistor R66. The ground terminal of the low dropout linear regulator U5 and the other end of resistor R66 are both connected to the power supply ground. The voltage output terminal of the low dropout linear regulator U5 outputs a 5V voltage to power the CAN transceiver U9 and is connected to one end of capacitor C87. The other end of capacitor C87 is connected to the power supply ground.

[0053] The power supply module also includes an OLED power supply enable circuit. The OLED power supply enable circuit includes a resistor R45 connected to the CPUU1 OLED 3.3V power supply enable signal output terminal, the other end of the resistor R45 connected to one end of the resistor R47, one end of the capacitor C53 and the base of the transistor Q3, the other end of the resistor R47, the other end of the capacitor C51 and the emitter of the transistor Q3 are all connected to the power supply ground, the collector of the transistor Q3 is connected to one end of the resistor R48, the other end of the resistor R48 is connected to the gate of the field-effect transistor Q4, one end of the resistor R46 and one end of the capacitor C52, the source of the transistor Q4 is connected to the other end of the resistor R46, the other end of the capacitor C52 and the other end of the inductor L2, and the drain of the transistor Q4 is the OLED 3.3V power supply terminal, used to power the OLED screen, and connected to one end of the resistor R49 and one end of the capacitor C54, the other end of the resistor R49 and the other end of the capacitor C54 are all connected to the power supply ground.

[0054] The power supply module also includes a battery sampling circuit, which includes a resistor R51. One end of the resistor R51 is connected to the battery sampling signal output terminal of the MCUU7. The other end of the resistor R51 is connected to one end of the resistor R53, one end of the capacitor C63, and the base of the transistor Q5. The other ends of the resistor R53, the other end of the capacitor C63, and the emitter of the transistor Q5 are all connected to the power supply ground. The collector of the transistor Q5 is connected to one end of the resistor R54. The other end of the resistor R54 is connected to the base of the transistor Q6, one end of the resistor R52, and one end of the capacitor C62. The emitter of the transistor Q6 is connected to the other ends of the resistor R52, the other end of the capacitor C62, and the battery output power supply terminal. The collector of the transistor Q6 is connected to one end of the resistor R56 and one end of the capacitor C67. The other end of the resistor R56 is connected to one end of the resistor R57, one end of the capacitor C91, and the MCUU7 battery analog signal terminal. The other ends of the capacitor C67, the other ends of the resistor R57, and the other ends of the capacitor C91 are all connected to the power supply ground.

[0055] The asynchronous serial data receiver of MCUU7 is connected to one end of resistor R97 and the asynchronous serial data transmitter of CPUU1. The other end of resistor R97 is connected to the other end of inductor L2. The asynchronous serial data transmitter of MCUU7 is connected to one end of resistor R96 and the asynchronous serial data receiver of CPUU1. The other end of resistor R96 is connected to the other end of inductor L2. The PTB_2 terminal of MCUU7 is connected to one end of resistor R63 and the first input / output detection terminal of CPUU1. The other end of resistor R63 is connected to the other end of inductor L2. The PTB_3 terminal of MCUU7 is connected to one end of resistor R62 and the second input / output detection terminal of CPUU1. The other end of resistor R62 is connected to the other end of inductor L2.

[0056] The output terminal of the MCUU7 oscillator is connected to one end of resistor R64, the first end of crystal Y3, and one end of capacitor C82. The other end of capacitor C82 and the normally open terminal of crystal Y3 are both connected to the power supply ground. The input terminal of the MCUU7 oscillator is connected to the other end of resistor R64, the second end of crystal Y3, and one end of capacitor C83. The other end of capacitor C83 is connected to the power supply ground.

[0057] The internal operating voltage terminal of MCUU7 is connected to one end of capacitor C81, one end of capacitor C80, one end of capacitor C78, ​​one end of capacitor C79, one end of capacitor C76, and one end of ferrite bead FB1. The other end of ferrite bead FB1 is connected to the other end of inductor L2. The common ground voltage terminal of MCUU7, the other ends of capacitor C81, capacitor C80, capacitor C78, ​​capacitor C79, and capacitor C76 are all connected to the power supply ground.

[0058] The MCUU7CAN enable control terminal is connected to the CAN transceiver U9 enable control signal receiver terminal. The MCUU7CAN receiver terminal is connected to one end of resistor R72, and the other end of resistor R72 is connected to the CAN transceiver U9CAN transmitter terminal. The MCUU7CAN transmitter terminal is connected to one end of resistor R71, and the other end of resistor R71 is connected to the CAN transceiver U9CAN receiver terminal.

[0059] The MCUU7SWD clock terminal is connected to the third terminal of terminal block P8 and one end of resistor R59. The other end of resistor R59 is connected to power ground. The MCUU7SWD data terminal is connected to the first terminal of terminal block P8 and one end of resistor R58. The other end of resistor R58 is connected to the other end of inductor L2. The MCUU7SWD reset terminal is connected to one end of resistor R60, one end of resistor R61, and one end of capacitor R74. The other end of resistor R61 and the second terminal of terminal block P8 are connected to the other end of inductor L2. The sixth terminal of terminal block P8 and the other end of capacitor R74 are both connected to power ground.

[0060] The positive power supply terminal of CPU power unit U1A 3.3V is connected to the drain of transistor Q1, one end of capacitors C20, C19, C18, C17, and C16. The other ends of capacitors C20, C19, C18, C17, and C16 are all connected to ground. The analog circuit power supply terminal of CPU power unit U1A 3.3V is connected to one end of resistor R7, one end of capacitor C14, and one end of capacitor C15. The other end of resistor R7 is connected to the drain of transistor Q1. CPU power unit U1A 3.3V... The PLL power supply terminal is connected to one end of resistor R6 and one end of capacitor C13. The other end of resistor R6 is connected to the drain of transistor Q1. The other ends of capacitors C13, C14, and C15 are all connected to power ground. The CPU power unit U1A operating voltage terminal is connected to the other end of inductor L1, one end of capacitor C12, one end of capacitor C11, one end of capacitor C10, and one end of capacitor C9. The other ends of capacitors C12, C11, C10, and C9 are all connected to power ground. The CPU power unit U1A 1.2V analog power supply terminal is connected to one end of capacitor C8 and one end of capacitor C7. The other ends of capacitors C8 and C7 are both connected to power ground.

[0061] The CPU power unit U1ASDVREF terminal is connected to one end of resistor R2, one end of resistor R1, and one end of capacitor C5. The other ends of resistor R1 and capacitor C5 are both connected to power ground. The other end of resistor R2 is connected to one end of resistor R27, and the other end of resistor R27 is connected to the CPU power unit U1A1.8VDDR terminal. The CPU power unit U1AAVDD_RTC terminal is connected to one end of resistor R3 and one end of capacitor C6. The other end of resistor R3 is connected to the drain of transistor Q1. The CPU power unit U1AAVSS_RTC terminal is connected to one end of resistor R4. The CPU power unit U1A pad port, the other end of resistor R4, and the other end of capacitor C6 are all connected to power ground.

[0062] The spare serial port transmitter of the CPU serial communication unit U1C is connected to one end of resistor R15 and one end of resistor R19. The other end of resistor R15 is connected to the drain of transistor Q1. One end of resistor R19 is connected to one end of diode ESD4 and the second end of spare terminal block P5. The other end of diode ESD4 and the first end of spare terminal block P5 are both connected to power ground. The printer serial port receiver of the CPU serial communication unit U1C is connected to one end of resistor R16 and one end of resistor R20. The other end of resistor R16 is connected to the drain of transistor Q1. One end of resistor R20 is connected to one end of diode ESD3 and the third end of spare terminal block P5. The other end of diode ESD3 is connected to power ground.

[0063] The first BOOT terminal of CPU System Unit U1B is connected to one end of resistor R8 and the first end of terminal block P1. The other end of resistor R8 is connected to the drain of transistor Q1. The second end of terminal block P1 is connected to power ground. The second BOOT terminal of CPU System Unit U1B is connected to one end of resistor R9 and the first end of terminal block P2. The other end of resistor R9 is connected to the drain of transistor Q1. The second end of terminal block P2 is connected to power ground. The oscillator input terminal of CPU System Unit U1B is connected to one end of resistor R12, the first end of crystal Y1, and one end of capacitor C24. The other end of capacitor C24 and the normally open end of crystal Y1 are both connected to power ground. The oscillator output terminal of CPU System Unit U1B is connected to the other end of resistor R12, the second end of crystal Y1, and one end of capacitor C25. The other end of capacitor C25 and the normally open end of crystal Y3 are both connected to power ground.

[0064] The CPU System Unit U1B debug port test clock terminal is connected to one end of resistor R95. The other end of resistor R95 is connected to one end of resistor R84 and the sixth terminal of terminal block P3, and then connected to an external debugging device through terminal block P3. The other end of resistor R84 is connected to the cathode of diode D4, and the anode of diode D4 is connected to the drain of transistor Q1. The CPU System Unit U1B debug port test data output terminal is connected to one end of resistor R94. The other end of resistor R94 is connected to one end of resistor R85 and the fifth terminal of terminal block P3, and the other end of resistor R85 is connected to the cathode of diode D4. The CPU System Unit U1B debug port test data input terminal is connected to one end of resistor R93. The other end of resistor R93 is connected to one end of resistor R86 and the fourth terminal of terminal block P3, and the other end of resistor R86 is connected to the cathode of diode D4. The CPU System Unit U1B debug port test mode selection terminal is connected to one end of resistor R92. The other end of resistor R92 is connected to one end of resistor R87 and the third terminal of terminal block P3, and the other end of resistor R87 is connected to the cathode of diode D4. The test reset terminal of the System unit U1B debug port is connected to one end of resistor R91. The other end of resistor R91 is connected to the second terminal of terminal block P3, one end of resistor R89, and the negative terminal of diode D4. The other end of resistor R89 ​​is connected to power ground. The seventh terminal of terminal block P3 is the system reset switch terminal, connected to one end of resistor R83. The other end of resistor R83 is connected to the negative terminal of diode D4. The eighth terminal of terminal block P3 is the clock coordination terminal, connected to one end of resistor R90. The other end of resistor R90 and the ninth terminal of terminal block P3 are connected to power ground.

[0065] The CPU memory unit U1F's chip select signal terminal is connected to the memory U2's chip select signal terminal and one end of resistor R24. The other end of resistor R24 ​​is connected to the power supply voltage terminal of memory U2. The CPU memory unit U1F's clock terminal is connected to the memory U2's clock terminal. The CPU memory unit U1F's first storage signal terminal is connected to the memory U2's input terminal. The CPU memory unit U1F's second storage signal terminal is connected to the memory U2's output terminal and one end of resistor R25. The other end of resistor R25 is connected to the power supply ground. The CPU memory unit U1F's third storage signal terminal is connected to the memory U2's write-protect input terminal and one end of resistor R22. One end of resistor R22 is connected to the power supply voltage terminal of memory U2. The fourth storage signal terminal of CPU storage unit U1F is connected to the reset terminal of memory U2 and one end of resistor R23. The other end of resistor R23 is connected to the power supply voltage terminal of memory U2. The power supply voltage terminal of memory U2 is connected to one end of ferrite bead FB2, one end of capacitor C26 and one end of capacitor C27. The other end of ferrite bead FB2 is connected to the negative terminal of diode D1 and one end of capacitor C28. The positive terminal of diode D1 is connected to the drain of transistor Q1. The ground terminal of memory U2, the other end of capacitor C26, the other end of capacitor C27 and the other end of capacitor C28 are all connected to the power supply ground.

[0066] The CPU display unit U1DOLED power setting output is connected to the OLED screen power setting input; the CPU display unit U1DOLED reset output is connected to the OLED screen reset input; the OLED screen synchronization signal output is connected to the CPU display unit U1DOLED synchronization signal input; the positive output of the first channel of CPU display unit U1D display data is connected to the positive input of the first channel of OLED display data; the negative output of the first channel of CPU display unit U1D display data is connected to the negative input of the first channel of OLED display data; the positive output of the second channel of CPU display unit U1D display data is connected to the positive input of the second channel of OLED display data; the negative output of the second channel of CPU display unit U1D display data is connected to the negative input of the second channel of OLED display data; the positive output of the clock channel of CPU display unit U1D display data is connected to the positive input of the clock channel of OLED display data; the negative output of the clock channel of CPU display unit U1D display data is connected to the negative input of the clock channel of OLED display data.

[0067] The OLED screen is connected via terminal block FPC1. The OLED screen also includes an OLED power module U6. Terminal 3 of the OLED power module U6 is connected to one end of inductor L5, and the other end of inductor L5 is connected to the other end of inductor L2. Terminal 1 of the OLED power module U6 is connected to one end of inductor L4, and the other end of inductor L4 is connected to the other end of inductor L2. Terminal 2 of the OLED power module U6 is connected to one end of inductor L3, and the other end of inductor L3 is connected to ground. Terminal PVIN of the OLED power module U6 is connected to one end of capacitor C58, one end of capacitor C60, and one end of inductor L2. Terminal AVIN of the OLED power module U6 is connected to one end of capacitor C59, one end of capacitor C61, one end of capacitor C58, and one end of capacitor C60. The ground terminal of the OLED power module U6, the other end of capacitor C59, the other end of capacitor C61, the other end of capacitor C58, and the other end of capacitor C60 are all connected to ground. Terminal VO3 of the OLED power module U6 is connected to capacitor C5... One end of capacitor C55, one end of capacitor C70, and the terminal block FPC1AVDD are connected to the power supply ground. The other ends of capacitor C55, capacitor C70, and OLED power module U6PGND2 are all connected to the power supply ground. The terminal block U6VO1 of OLED power module is connected to one end of capacitor C56, one end of capacitor C98, one end of capacitor C68, and the terminal block FPC1ELVDD. The other ends of capacitor C56, capacitor C98, capacitor C68, and OLED power module U6PGND1 are all connected to the power supply ground. The terminal block U6VO2 of OLED power module is connected to one end of capacitor C57, one end of capacitor C100, one end of capacitor C69, and the terminal block FPC1ELVSS. The other ends of capacitor C57, capacitor C100, and capacitor C69 are all connected to the power supply ground. The terminal block FPC1IDVCC is connected to the voltage output terminal of low dropout linear regulator U5. The terminal block FPC1VCI is connected to the drain of transistor Q4.

[0068] The first terminal of connector P7 is connected to one end of transient voltage suppression diode TSV2, one end of capacitor C64, and the positive terminal of diode D3. The negative terminal of diode D3 is connected to one end of inductor L6, one end of capacitor C65, and one end of capacitor C77. The other end of inductor L6 is connected to the battery output power supply terminal, one end of capacitor C66, and one end of capacitor C86. The other ends of transient voltage suppression diode TSV2, capacitor C64, capacitor C65, capacitor C77, capacitor C66, capacitor C86, and the second terminal of connector P7 are all connected to the power ground.

[0069] Connector P7's fourth terminal connects to one end of capacitor C89, one end of resistor R68, one end of resistor R70, and the first terminal of ESD protection diode ESD5. The other end of resistor R70 is connected to the high-level terminal of CAN transceiver U9. The other end of resistor R68 is connected to one end of capacitor C90. The other ends of capacitor C89, capacitor C90, and ESD protection diode ESD5 are all connected to power ground. Connector P7's fifth terminal connects to one end of capacitor C88, one end of resistor R67, one end of resistor R69, and the third terminal of diode ESD5. The other end of resistor R69 is connected to the low-level terminal of CAN transceiver U9. The other end of resistor R67 is connected to one end of capacitor C90. The other end of capacitor C88 is connected to power ground.

Claims

1. A CAN bus rear instrument working system, characterized in that: It includes a CPU (U1), whose display data output terminal is connected to the OLED screen display data input terminal, and whose asynchronous serial data transceiver terminal is connected to the MCU (U7) asynchronous serial data transceiver terminal. The MCU (U7) CAN bus data transceiver terminal is connected to the CAN transceiver (U9) CAN bus data transceiver terminal, and is connected to the car's infotainment system through a connector (P7) via the CAN transceiver (U9) data transceiver terminal.

2. The CAN bus rear instrument working system according to claim 1, characterized in that: The system also includes a power supply module, comprising a first DC-DC converter (U3) whose voltage input terminal is connected to the battery output power supply terminal, one end of capacitor C45, one end of capacitor C46, ​​one end of capacitor C47, and one end of capacitor C48. The other ends of capacitors C45, C46, ​​C47, and C48 are all connected to the power ground. The enable terminal of the first DC-DC converter (U3) is connected to one end of resistor R38 and one end of resistor R39. The other end of resistor R38 is connected to the battery output power supply terminal. The power supply voltage of the first DC-DC converter (U3) is connected to one end of capacitor C44. The other ends of capacitor C44, resistor R39, and the ground terminal of the first DC-DC converter (U3) are connected to... Connected to power ground, the BOOT terminal of the first DC-DC converter (U3) is connected to one end of resistor R34, the other end of resistor R34 is connected to one end of capacitor C38, the other end of capacitor C38 is connected to the SW terminal of the first DC-DC converter (U3) and one end of inductor L2, the other end of inductor L2 outputs 3.3V voltage and is connected to one end of resistor R35, one end of capacitor C40, one end of capacitor C41, one end of capacitor C42 and one end of capacitor C43, the feedback terminal of the first DC-DC converter (U3) is connected to the other end of resistor R35 and one end of resistor R36, the other ends of resistor R36, capacitor C40, capacitor C41, capacitor C42 and capacitor C43 are all connected to power ground; The power supply module also includes a second DC-DC converter (U4) whose voltage input terminal is connected to the other end of inductor L2, one end of capacitor C31, one end of capacitor C32, and one end of resistor R28. The other ends of capacitor C31 and C32, the ground terminal of the second DC-DC converter (U4), and the MODE terminal of the second DC-DC converter (U4) are all connected to the power ground. The enable terminal of the second DC-DC converter (U4) is connected to one end of resistor R102 and the SOC 1.3V power supply enable terminal of the MCU (U7). The PG terminal of the second DC-DC converter (U4) is powered by SOC 3.3V. The enable terminal is connected to one end of resistor R29. The SW terminal of the second DC-DC converter (U4) is connected to one end of inductor L1. The other end of inductor L1 outputs a 1.3V voltage and is connected to the other end of resistor R29, one end of resistor R31, one end of capacitor C33, one end of capacitor C34, and one end of capacitor C35. The feedback terminal of the second DC-DC converter (U4) is connected to the other end of capacitor C33, the other end of resistor R31, and one end of resistor R30. The ground terminal of the second DC-DC converter (U4), the other end of resistor R30, the other end of capacitor C34, and the other end of capacitor C35 are all connected to the power supply ground. The second DC-DC converter (U4) has its PG terminal connected to one end of resistor R44. The other end of resistor R44 is connected to one end of capacitor C51 and the base of transistor Q2. The other end of capacitor C51 and the emitter of transistor Q2 are both connected to power ground. The collector of transistor Q2 is connected to one end of resistor R40. The other end of resistor R40 is connected to the gate of field-effect transistor Q1, one end of resistor R41, and one end of capacitor C49. The source of transistor Q1 is connected to the other end of resistor R41, the other end of capacitor C49, and the other end of inductor L2. The drain of transistor Q1 is the SOC 3.3V power supply terminal, used to power the CPU (U1), and is connected to one end of resistor R42 and one end of capacitor C50. The other ends of resistor R42 and capacitor C50 are both connected to power ground. The power supply module also includes a low-dropout linear regulator (U5). The voltage input terminal of the low-dropout linear regulator (U5) is connected to the other end of inductor L2 and one end of capacitor C36. The enable terminal of the low-dropout linear regulator (U5) is connected to the OLED 1.8V power supply enable terminal of CPU (U1) and one end of resistor R33. The ground terminal of the low-dropout linear regulator (U5), the other end of resistor R33, and the other end of capacitor C36 are all connected to the power supply ground. The voltage output terminal of the low-dropout linear regulator (U5) outputs a 1.8V voltage to power the OLED screen and is connected to one end of capacitor C37. The other end of capacitor C37 is connected to the power supply ground. The power supply module also includes a linear regulator (U8). The voltage input terminal of the linear regulator (U8) is connected to the battery output power supply terminal, one end of capacitor C84, and one end of capacitor C85. The other ends of capacitor C84 and capacitor C85 are both connected to the power ground. The enable terminal of the low dropout linear regulator (U5) is connected to the CAN power supply enable terminal of the MCU (U7) and one end of resistor R66. The ground terminal of the low dropout linear regulator (U5) and the other end of resistor R66 are both connected to the power ground. The voltage output terminal of the low dropout linear regulator (U5) outputs a 5V voltage to power the CAN transceiver (U9) and is connected to one end of capacitor C87. The other end of capacitor C87 is connected to the power ground.

3. The CAN bus retrofit instrument operating system according to claim 2, characterized in that: The power supply module also includes an OLED power supply enable circuit. This circuit includes a resistor R45 connected to the CPU (U1) OLED 3.3V power supply enable signal output terminal. The other end of the resistor R45 is connected to one end of a resistor R47, one end of a capacitor C53, and the base of a transistor Q3. The other ends of the resistor R47, capacitor C51, and the emitter of transistor Q3 are all connected to power ground. The collector of transistor Q3 is connected to one end of a resistor R48. The other end of the resistor R48 is connected to the gate of a field-effect transistor Q4, one end of a resistor R46, and one end of a capacitor C52. The source of transistor Q4 is connected to the other ends of a resistor R46, capacitor C52, and inductor L2. The drain of transistor Q4 is the OLED 3.3V power supply terminal, used to power the OLED screen, and is connected to one end of a resistor R49 and one end of a capacitor C54. The other ends of the resistor R49 and capacitor C54 are both connected to power ground. The power supply module also includes a battery sampling circuit, which includes a resistor R51. One end of resistor R51 is connected to the battery sampling signal output terminal of the MCU (U7). The other end of resistor R51 is connected to one end of resistor R53, one end of capacitor C63, and the base of transistor Q5. The other ends of resistor R53, capacitor C63, and the emitter of transistor Q5 are all connected to the power supply ground. The collector of transistor Q5 is connected to one end of resistor R54, and the other end of resistor R54 is connected to the base of transistor Q5. The base of transistor Q6 is connected to one end of resistor R52 and one end of capacitor C62. The emitter of transistor Q6 is connected to the other end of resistor R52, the other end of capacitor C62, and the battery output power supply terminal. The collector of transistor Q6 is connected to one end of resistor R56 and one end of capacitor C67. The other end of resistor R56 is connected to one end of resistor R57, one end of capacitor C91, and the battery analog signal terminal of MCU (U7). The other ends of capacitor C67, resistor R57, and capacitor C91 are all connected to power ground.

4. The CAN bus retrofit instrument operating system according to claim 2, characterized in that: The asynchronous serial data receiving terminal of the MCU (U7) is connected to one end of resistor R97 and the asynchronous serial data transmitting terminal of the CPU (U1). The other end of resistor R97 is connected to the other end of inductor L2. The asynchronous serial data transmitting terminal of the MCU (U7) is connected to one end of resistor R96 and the asynchronous serial data receiving terminal of the CPU (U1). The other end of resistor R96 is connected to the other end of inductor L2. The PTB_2 terminal of the MCU (U7) is connected to one end of resistor R63 and the first input / output detection terminal of the CPU (U1). The other end of resistor R63 is connected to the other end of inductor L2. The PTB_3 terminal of the MCU (U7) is connected to one end of resistor R62 and the second input / output detection terminal of the CPU (U1). The other end of resistor R62 is connected to the other end of inductor L2. The output terminal of the MCU (U7) oscillator is connected to one end of resistor R64, the first end of crystal Y3, and one end of capacitor C82. The other end of capacitor C82 and the normally open terminal of crystal Y3 are both connected to the power supply ground. The input terminal of the MCU (U7) oscillator is connected to the other end of resistor R64, the second end of crystal Y3, and one end of capacitor C83. The other end of capacitor C83 is connected to the power supply ground. The internal operating voltage terminal of the MCU (U7) is connected to one end of capacitor C81, one end of capacitor C80, one end of capacitor C78, ​​one end of capacitor C79, one end of capacitor C76, and one end of ferrite bead FB1. The other end of ferrite bead FB1 is connected to the other end of inductor L2. The common ground voltage terminal of the MCU (U7), the other ends of capacitors C81, C80, C78, ​​C79, and C76 are all connected to the power ground. The CAN enable control terminal of the MCU (U7) is connected to the enable control signal receiving terminal of the CAN transceiver (U9). The CAN receiving terminal of the MCU (U7) is connected to one end of resistor R72, and the other end of resistor R72 is connected to the CAN transmitting terminal of the CAN transceiver (U9). The CAN transmitting terminal of the MCU (U7) is connected to one end of resistor R71, and the other end of resistor R71 is connected to the CAN receiving terminal of the CAN transceiver (U9). The clock terminal of the MCU (U7) SWD is connected to the third terminal of terminal block P8 and one end of resistor R59. The other end of resistor R59 is connected to power ground. The data terminal of the MCU (U7) SWD is connected to the first terminal of terminal block P8 and one end of resistor R58. The other end of resistor R58 is connected to the other end of inductor L2. The reset terminal of the MCU (U7) SWD is connected to one end of resistor R60, one end of resistor R61, and one end of capacitor R74. The other end of resistor R61 and the second terminal of terminal block P8 are connected to the other end of inductor L2. The sixth terminal of terminal block P8 and the other end of capacitor R74 are both connected to power ground.

5. The CAN bus retrofit instrument operating system according to claim 2, characterized in that: The 3.3V positive power supply terminal of the CPU power unit (U1A) is connected to the drain of transistor Q1, one end of capacitors C20, C19, C18, C17, and C16. The other ends of capacitors C20, C19, C18, C17, and C16 are all connected to ground. The 3.3V analog circuit power supply terminal of the CPU power unit (U1A) is connected to one end of resistor R7, one end of capacitor C14, and one end of capacitor C15. The other end of resistor R7 is connected to the drain of transistor Q1. The CPU power unit (U1A) 3.3V... The PLL power supply terminal is connected to one end of resistor R6 and one end of capacitor C13. The other end of resistor R6 is connected to the drain of transistor Q1. The other ends of capacitors C13, C14, and C15 are all connected to power ground. The CPU power unit (U1A) operating voltage terminal is connected to the other end of inductor L1, one end of capacitor C12, one end of capacitor C11, one end of capacitor C10, and one end of capacitor C9. The other ends of capacitors C12, C11, C10, and C9 are all connected to power ground. The CPU power unit (U1A) 1.2V analog power supply terminal is connected to one end of capacitor C8 and one end of capacitor C7. The other ends of capacitors C8 and C7 are both connected to power ground. The CPU power unit (U1A) SDVREF terminal is connected to one end of resistor R2, one end of resistor R1, and one end of capacitor C5. The other ends of resistor R1 and capacitor C5 are both connected to power ground. The other end of resistor R2 is connected to one end of resistor R27, and the other end of resistor R27 is connected to the 1.8VDDR terminal of the CPU power unit (U1A). The CPU power unit (U1A) AVDD_RTC terminal is connected to one end of resistor R3 and one end of capacitor C6. The other end of resistor R3 is connected to the drain of transistor Q1. The CPU power unit (U1A) AVSS_RTC terminal is connected to one end of resistor R4. The CPU power unit (U1A) pad port, the other end of resistor R4, and the other end of capacitor C6 are all connected to power ground.

6. The CAN bus retrofit instrument operating system according to claim 5, characterized in that: The spare serial port transmitter of the CPU serial communication unit (U1C) is connected to one end of resistor R15 and one end of resistor R19. The other end of resistor R15 is connected to the drain of transistor Q1. One end of resistor R19 is connected to one end of diode ESD4 and the second terminal of spare terminal block P5. The other end of diode ESD4 and the first terminal of spare terminal block P5 are both connected to power ground. The printer serial port receiver of the CPU serial communication unit (U1C) is connected to one end of resistor R16 and one end of resistor R20. The other end of resistor R16 is connected to the drain of transistor Q1. One end of resistor R20 is connected to one end of diode ESD3 and the third terminal of spare terminal block P5. The other end of diode ESD3 is connected to power ground. The CPU System unit (U1B) has its first BOOT terminal connected to one end of resistor R8 and the first end of terminal block P1. The other end of resistor R8 is connected to the drain of transistor Q1. The second end of terminal block P1 is connected to power ground. The CPU System unit (U1B) has its second BOOT terminal connected to one end of resistor R9 and the first end of terminal block P2. The other end of resistor R9 is connected to the drain of transistor Q1. The second end of terminal block P2 is connected to power ground. The CPU System unit (U1B) oscillator input terminal is connected to one end of resistor R12, the first end of crystal Y1, and one end of capacitor C24. The other end of capacitor C24 and the normally open end of crystal Y1 are both connected to power ground. The CPU System unit (U1B) oscillator output terminal is connected to the other end of resistor R12, the second end of crystal Y1, and one end of capacitor C25. The other end of capacitor C25 and the normally open end of crystal Y3 are both connected to power ground. The CPU System Unit (U1B) debug port test clock terminal is connected to one end of resistor R95. The other end of resistor R95 is connected to one end of resistor R84 and the sixth terminal of terminal block P3, and is connected to an external debugging device through terminal block P3. The other end of resistor R84 is connected to the cathode of diode D4, and the anode of diode D4 is connected to the drain of transistor Q1. The CPU System Unit (U1B) debug port test data output terminal is connected to one end of resistor R94. The other end of resistor R94 is connected to one end of resistor R85 and the fifth terminal of terminal block P3, and the other end of resistor R85 is connected to the cathode of diode D4. The CPU System Unit (U1B) debug port test data input terminal is connected to one end of resistor R93. The other end of resistor R93 is connected to one end of resistor R86 and the fourth terminal of terminal block P3, and the other end of resistor R86 is connected to the cathode of diode D4. The CPU The test mode selection terminal of the System Unit (U1B) debug port is connected to one end of resistor R92. The other end of resistor R92 is connected to one end of resistor R87 and the third terminal of terminal block P3. The other end of resistor R87 is connected to the cathode of diode D4. The test reset terminal of the CPU System Unit (U1B) debug port is connected to one end of resistor R91. The other end of resistor R91 is connected to the second terminal of terminal block P3, one end of resistor R89, and the cathode of diode D4. The other end of resistor R89 ​​is connected to power ground. The seventh terminal of terminal block P3 is the system reset switch terminal, connected to one end of resistor R83. The other end of resistor R83 is connected to the cathode of diode D4. The eighth terminal of terminal block P3 is the clock coordination terminal, connected to one end of resistor R90. The other end of resistor R90 and the ninth terminal of terminal block P3 are connected to power ground.

7. The CAN bus retrofit instrument operating system according to claim 5, characterized in that: The CPU memory unit (U1F) chip select signal terminal is connected to the memory (U2) chip select signal terminal and one end of resistor R24. The other end of resistor R24 ​​is connected to the power supply voltage terminal of memory (U2). The CPU memory unit (U1F) clock terminal is connected to the memory (U2) clock terminal. The first storage signal terminal of the CPU memory unit (U1F) is connected to the input terminal of memory (U2). The second storage signal terminal of the CPU memory unit (U1F) is connected to the output terminal of memory (U2) and one end of resistor R25. The other end of resistor R25 is connected to the power supply ground. The third storage signal terminal of the CPU memory unit (U1F) is connected to the write-protect input terminal of memory (U2) and one end of resistor R22. The other end of resistor R22 is connected to the power supply voltage terminal of memory (U2). The fourth storage signal terminal of the storage unit (U1F) is connected to the reset terminal of the memory (U2) and one end of the resistor R23. The other end of the resistor R23 is connected to the power supply voltage terminal of the memory (U2). The power supply voltage terminal of the memory (U2) is connected to one end of the ferrite bead FB2, one end of the capacitor C26, and one end of the capacitor C27. The other end of the ferrite bead FB2 is connected to the negative terminal of the diode D1 and one end of the capacitor C28. The positive terminal of the diode D1 is connected to the drain of the transistor Q1. The ground terminal of the memory (U2), the other end of the capacitor C26, the other end of the capacitor C27, and the other end of the capacitor C28 are all connected to the power supply ground.

8. The CAN bus retrofit instrument operating system according to claim 5, characterized in that: The CPU display unit (U1D) OLED power setting output is connected to the OLED screen power setting input; the CPU display unit (U1D) OLED reset output is connected to the OLED screen reset input; the OLED screen synchronization signal output is connected to the CPU display unit (U1D) OLED synchronization signal input; the positive output of the first channel of display data of the CPU display unit (U1D) is connected to the positive input of the first channel of display data of the OLED screen; the negative output of the first channel of display data of the CPU display unit (U1D) is connected to the negative input of the first channel of display data of the OLED screen; the positive output of the second channel of display data of the CPU display unit (U1D) is connected to the positive input of the second channel of display data of the OLED screen; the negative output of the second channel of display data of the CPU display unit (U1D) is connected to the negative input of the second channel of display data of the OLED screen; the positive output of the clock channel of display data of the CPU display unit (U1D) is connected to the positive input of the clock channel of display data of the OLED screen; and the negative output of the clock channel of display data of the CPU display unit (U1D) is connected to the negative input of the clock channel of display data of the OLED screen.

9. The CAN bus retrofit instrument operating system according to claim 8, characterized in that: The OLED screen is connected via a terminal block FPC1. The OLED screen also includes an OLED power module (U6). The LX3 terminal of the OLED power module (U6) is connected to one end of inductor L5, and the other end of inductor L5 is connected to the other end of inductor L2. The LX1 terminal of the OLED power module (U6) is connected to one end of inductor L4, and the other end of inductor L4 is connected to the other end of inductor L2. The LX2 terminal of the OLED power module (U6) is connected to one end of inductor L3, and the other end of inductor L3 is connected to ground. The PVIN terminal of the OLED power module (U6) is connected to one end of capacitor C58, one end of capacitor C60, and one end of inductor L2. The AVIN terminal of the OLED power module (U6) is connected to one end of capacitor C59, one end of capacitor C61, and one end of inductor L2. The ground terminal of the OLED power module (U6), the other end of capacitor C59, the other end of capacitor C61, the other end of capacitor C58, and the other end of capacitor C60 are all connected to ground. The VO terminal of the OLED power module (U6)... The three terminals are connected to one end of capacitor C55, one end of capacitor C70, and the terminal of terminal block FPC1AVDD. The other ends of capacitors C55 and C70, and the PGND2 terminal of the OLED power module (U6) are all connected to the power ground. The VO1 terminal of the OLED power module (U6) is connected to one end of capacitors C56, C98, and C68, and the terminal of terminal block FPC1ELVDD. The other ends of capacitors C56, C98, and C68 are connected to the OLED power ground. The PGND1 terminal of module (U6) is connected to the power ground. The VO2 terminal of the OLED power module (U6) is connected to one end of capacitor C57, one end of capacitor C100, one end of capacitor C69 and the terminal of terminal block FPC1ELVSS. The other ends of capacitors C57, C100 and C69 are connected to the power ground. The terminal of terminal block FPC1IDVCC is connected to the voltage output terminal of low dropout linear regulator (U5). The terminal of terminal block FPC1VCI is connected to the drain of transistor Q4.

10. The CAN bus retrofit instrument operating system according to claim 2, characterized in that: The first end of the connector (P7) is connected to one end of the transient voltage suppression diode TSV2, one end of the capacitor C64, and the positive terminal of the diode D3. The negative terminal of the diode D3 is connected to one end of the inductor L6, one end of the capacitor C65, and one end of the capacitor C77. The other end of the inductor L6 is connected to the battery output power supply terminal, one end of the capacitor C66, and one end of the capacitor C86. The other ends of the transient voltage suppression diode TSV2, capacitor C64, capacitor C65, capacitor C77, capacitor C66, capacitor C86, and the second end of the connector (P7) are all connected to the power ground. The fourth terminal of connector (P7) is connected to one end of capacitor C89, one end of resistor R68, one end of resistor R70, and the first terminal of electrostatic discharge protection diode ESD5. The other end of resistor R70 is connected to the high-level terminal of CAN transceiver (U9). The other end of resistor R68 is connected to one end of capacitor C90. The other ends of capacitor C89, capacitor C90, and ESD5 are all connected to power ground. The fifth terminal of connector (P7) is connected to one end of capacitor C88, one end of resistor R67, one end of resistor R69, and the third terminal of diode ESD5. The other end of resistor R69 is connected to the low-level terminal of CAN transceiver (U9). The other end of resistor R67 is connected to one end of capacitor C90. The other end of capacitor C88 is connected to power ground.

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