Interface circuits, interface chips and electronic devices

Abstract

This disclosure relates to an interface circuit, an interface chip, and an electronic device. The interface circuit includes: a detection circuit, electrically connected to at least one functional terminal of the interface, for detecting electrical information of the functional terminal, which indicates the presence of foreign matter on the interface; and a protection circuit, electrically connected to the detection circuit, at least some of the functional terminals, and the control circuit of the electronic device, for protecting the control circuit. By using a detection circuit and a protection circuit to construct the interface circuit, the interface circuit can not only detect the presence of foreign matter on the interface but also protect the control circuit, thereby improving the reliability of the interface circuit. Furthermore, since the detection circuit and the protection circuit can be electrically connected to the same functional terminal, the number of lines in the interface circuit is reduced, thus lowering the complexity of the interface circuit.

Description

Technical Field

[0001] This disclosure relates to the field of interface technology, and in particular to an interface circuit, an interface chip, and an electronic device. Background Technology

[0002] Electronic devices are equipped with interfaces, through which external devices are electrically connected. Each interface contains multiple functional terminals, each with its own function. These terminals work together to enable the functionality of the connected external device. Utility Model Content

[0003] To overcome the problems existing in related technologies, this disclosure provides an interface circuit, an interface chip, and an electronic device.

[0004] According to a first aspect of this disclosure, an interface circuit is provided, the interface circuit comprising:

[0005] A detection circuit is provided, wherein the detection circuit is electrically connected to at least one functional terminal of the interface, the detection circuit is used to detect the electrical information of the functional terminal, and the electrical information is used to reflect whether there is a foreign object in the interface;

[0006] A protection circuit is provided, which is electrically connected to the detection circuit, at least a portion of the functional terminals, and the control circuit of the electronic device. The protection circuit is used to protect the control circuit.

[0007] In this embodiment, by constructing an interface circuit with a detection circuit and a protection circuit, the interface circuit can not only detect the presence of foreign objects at the interface but also protect the control circuit, thereby improving the reliability of the interface circuit. Furthermore, since the detection circuit and the protection circuit can be electrically connected to the same functional terminal, the number of lines in the interface circuit is reduced, thus lowering the complexity of the interface circuit.

[0008] In some embodiments of this disclosure, the detection circuit includes:

[0009] An impedance detection circuit, wherein the impedance detection circuit is electrically connected to at least one of the functional terminals, and the impedance detection circuit is used to detect the impedance of the functional terminal as the electrical information; or,

[0010] A voltage detection circuit is provided, wherein the voltage detection circuit is electrically connected to at least one of the functional terminals, and the voltage detection circuit is used to detect the voltage of the functional terminals as electrical information.

[0011] In this embodiment, an impedance detection circuit detects the impedance of the functional terminals to determine if there are foreign objects in the interface, thereby improving the reliability of the interface circuit. Similarly, a voltage detection circuit detects the voltage of the functional terminals to determine if there are foreign objects in the interface, further improving the reliability of the interface circuit.

[0012] In some embodiments of this disclosure, the functional terminals include a first sideband usage terminal, a second sideband usage terminal, a first communication terminal, and a second communication terminal; the detection circuit is electrically connected to the first sideband usage terminal, the second sideband usage terminal, the first communication terminal, and the second communication terminal.

[0013] In this embodiment, by performing foreign object detection on the aforementioned terminals, the impact of foreign objects on the interface of the electronic device can be minimized, thereby further improving the reliability of the interface circuit and reducing its complexity.

[0014] In some embodiments of this disclosure, the functional terminal further includes a first configuration channel terminal and a second configuration channel terminal; the detection circuit is also electrically connected to both the first configuration channel terminal and the second configuration channel terminal.

[0015] In this embodiment, by performing foreign object detection on the first configuration channel terminal and the second configuration channel terminal, the impact of foreign objects on the interface of the electronic device can be further reduced, thereby further improving the reliability of the interface circuit and reducing the complexity of the interface circuit.

[0016] In some embodiments of this disclosure, the functional terminals include a first sideband usage terminal and a second sideband usage terminal; the protection circuit includes:

[0017] A first protection circuit is electrically connected between the first sideband terminal, the second sideband terminal, the first terminal of the control circuit, and the second terminal of the control circuit. The first protection circuit is used to trigger overvoltage protection and / or overcurrent protection.

[0018] A first switching circuit is electrically connected between the first sideband usage terminal, the second sideband usage terminal, the first terminal of the control circuit, and the second terminal of the control circuit, and is also electrically connected to the first protection circuit. The first switching circuit is used to disconnect when the first protection circuit triggers overvoltage protection and / or overcurrent protection, and to select the first sideband usage terminal and the second sideband usage terminal corresponding to one end of the control circuit to be turned on.

[0019] In this embodiment, by reusing the first switching circuit, the forward and reverse insertion switching function of the interface can be realized, thereby further improving the reliability of the interface circuit.

[0020] In some embodiments of this disclosure, the functional terminal includes a first communication terminal and a second communication terminal; the protection circuit includes:

[0021] The second protection circuit is electrically connected between the first communication terminal, the second communication terminal, the third terminal of the control circuit, and the fourth terminal of the control circuit. The second protection circuit is used to trigger overvoltage protection and / or overcurrent protection.

[0022] The second switching circuit is electrically connected between the first communication terminal, the second communication terminal, the third terminal of the control circuit, and the fourth terminal of the control circuit, and is also electrically connected to the second protection circuit. The second switching circuit is used to disconnect when the second protection circuit triggers overvoltage protection and / or overcurrent protection.

[0023] In this embodiment, the second switching circuit prevents excessive voltage and / or current flowing into the control circuit from damaging the control circuit, thereby improving the reliability of the interface circuit.

[0024] In some embodiments of this disclosure, the second protection circuit is electrically connected to the third and fourth terminals of the control circuit via a power management circuit.

[0025] In this embodiment, the voltage of the first communication terminal and the second communication terminal is reduced by the power management circuit before being input to the control circuit, thereby avoiding damage to the control circuit and improving the reliability of the interface circuit.

[0026] In some embodiments of this disclosure, the interface circuit further includes:

[0027] A gating circuit, wherein each first terminal of the gating circuit is electrically connected to one of the functional terminals, and the second terminal of the gating circuit is electrically connected to the detection circuit, and the gating circuit is used to selectively connect one of the plurality of functional terminals to the detection circuit.

[0028] In this embodiment, since the gating circuit can electrically connect as many functional terminals as possible, it can increase the number of functional terminals detected by the detection circuit, thereby improving the reliability of the interface circuit.

[0029] In some embodiments of this disclosure, the interface circuit further includes:

[0030] A communication circuit is provided, which is electrically connected to both the detection circuit and the control circuit. The communication circuit is used to transmit electrical information from the detection circuit to the control circuit.

[0031] In this embodiment, since the communication circuit can transmit the electrical information of the detection circuit to the control circuit, the control circuit can combine the electrical information to perform corresponding actions to avoid the influence of foreign objects, thereby improving the reliability of the interface circuit.

[0032] In some embodiments of this disclosure, the communication circuit is also electrically connected to the protection circuit, and the communication circuit is also used to transmit the configuration signal of the control circuit to the protection circuit.

[0033] In this embodiment, the control circuit can transmit configuration signals to the protection circuit through the communication circuit to flexibly adjust the threshold for triggering protection by the protection circuit, thereby improving the reliability of the interface circuit.

[0034] According to a second aspect of this disclosure, an interface chip is provided, the interface chip including the interface circuit described above.

[0035] In this embodiment, integrating the interface circuit onto the interface chip reduces the size of the electronic device occupied by the interface circuit, thereby reducing the size of the electronic device.

[0036] In some embodiments of this disclosure, the interface chip further includes:

[0037] Multiple first pins are electrically connected to the detection circuit, the protection circuit, and the multiple functional terminals;

[0038] Multiple second pins are provided, and the multiple second pins are electrically connected to the detection circuit, the protection circuit and the control circuit.

[0039] In this embodiment, by dividing the first pin and the second pin, the arrangement of the first pin and the second pin can be appropriately carried out to reduce the number and length of the lines, thereby reducing the complexity of the interface chip.

[0040] In some embodiments of this disclosure, the plurality of first pins are arranged in a first region along a first preset direction, some of the second pins are arranged in a second region along the first preset direction, and another portion of the second pins are arranged in a third region along the first preset direction; or, the first region, the third region, and the second region are arranged along a second preset direction.

[0041] The first region, the second region, and the third region are arranged along a second preset direction, and the first preset direction and the second preset direction are perpendicular.

[0042] In this embodiment, since the areas where the first pin is located are different from the areas where the second pin is located, it is convenient for the first pin to be electrically connected to the functional terminal and the second pin to be electrically connected to the control circuit, thereby further reducing the complexity of the interface chip.

[0043] In some embodiments of this disclosure, the first region is closer to the interface than the second and third regions, and the second and third regions are closer to the control circuit than the first region.

[0044] In this embodiment, by placing the first region close to the interface and the second and third regions close to the control circuit, it is easier for the interface chip to be electrically connected to the interface and the control circuit, thereby improving the reliability of the interface chip.

[0045] In some embodiments of this disclosure, the plurality of first pins and the plurality of second pins are arranged adjacently to perform the same function.

[0046] In this embodiment, by arranging multiple pins with the same function adjacent to each other, the difference in line connection length between multiple pins with the same function and the interface or control circuit is small, avoiding problems such as different timing of signals transmitted by pins with the same function, thereby improving the reliability of the interface chip.

[0047] In some embodiments of this disclosure, the first pin located in the first region includes adjacent first sideband pins and second sideband pins, as well as adjacent first communication pins and second communication pins.

[0048] In this embodiment, by setting the first sideband pin, the second sideband pin, the third sideband pin, and the fourth sideband pin in the first area, it is convenient to electrically connect to the functional terminals of the interface.

[0049] In some embodiments of this disclosure, the first sideband pin, the second sideband pin, the first communication pin, and the second communication pin are arranged sequentially along the first preset direction.

[0050] In this embodiment, by arranging the first pins sequentially along a first preset direction, it is not only convenient to connect the first pins to the functional terminals of the interface, but also to reduce the complexity of the circuit connection.

[0051] In some embodiments of this disclosure, the first sideband uses pins that are electrically connected to the detection circuit, the protection circuit, and the first sideband uses terminals; the second sideband uses pins that are electrically connected to the detection circuit, the protection circuit, and the second sideband uses terminals; the first communication pin is electrically connected to the detection circuit, the protection circuit, and the first communication terminal; and the second communication pin is electrically connected to the detection circuit, the protection circuit, and the second communication terminal.

[0052] In this embodiment, the interface chip is electrically connected to the detection circuit, protection circuit, and functional terminals of the interface through multiple pins. The interface chip can not only protect the control circuit but also detect whether there are foreign objects in the interface, thereby improving the reliability of the interface chip.

[0053] In some embodiments of this disclosure, the second pin located in the second region includes adjacent third sideband use pins and fourth sideband use pins, as well as adjacent third communication pins and fourth communication pins.

[0054] In this embodiment, by setting the third sideband pin, the fourth sideband pin, the third communication pin, and the fourth communication pin in the second area, it is convenient to connect them to the control circuit.

[0055] In some embodiments of this disclosure, the third sideband pin, the fourth sideband pin, the third communication pin, and the fourth communication pin are arranged sequentially along the first preset direction.

[0056] In this embodiment, by arranging the third sideband pin, the fourth sideband pin, the third communication pin, and the fourth communication pin sequentially along the first preset direction, it is possible to facilitate the electrical connection of these pins with the control circuit, thereby reducing the complexity of the circuit connection.

[0057] In some embodiments of this disclosure, the third sideband is electrically connected to both the protection circuit and the control circuit via pins, the fourth sideband is electrically connected to both the protection circuit and the control circuit via pins, the third communication pin is electrically connected to both the protection circuit and the control circuit, and the fourth communication pin is electrically connected to both the protection circuit and the control circuit.

[0058] In this embodiment, the interface chip is electrically connected to the detection circuit, protection circuit, functional terminals of the interface, and control circuit through multiple pins. The interface chip can not only protect the control circuit but also detect whether there are foreign objects in the interface, thereby improving the reliability of the interface chip.

[0059] In some embodiments of this disclosure, the third communication pin and the fourth communication pin are electrically connected to the control circuit via a power management circuit.

[0060] In this embodiment, the voltage transmitted to the third and fourth communication pins is reduced by the power management circuit before being input to the control circuit, thereby improving the reliability of the interface chip.

[0061] In some embodiments of this disclosure, the second pin located in the third region includes adjacent serial data pins and serial clock pins, as well as adjacent first ground pins and power supply pins.

[0062] In this embodiment, by setting the serial data pin, serial clock pin, first ground pin, and power supply pin in the third area, it is convenient to connect them to the control circuit and power management circuit.

[0063] In some embodiments of this disclosure, the serial data pin, the serial clock pin, the first ground pin, and the power supply pin are arranged sequentially along the first preset direction.

[0064] In this embodiment, by arranging the serial data pin, serial clock pin, first ground pin, and power supply pin sequentially along a first preset direction, it is possible to facilitate the electrical connection of these pins with the control circuit and power management circuit, thereby reducing the complexity of the line connection.

[0065] In some embodiments of this disclosure, the serial data pin is electrically connected to both the detection circuit and the control circuit, the serial clock pin is electrically connected to both the detection circuit and the control circuit, the first ground pin is electrically connected to both the detection circuit, the protection circuit, and the control circuit, and the power supply pin is electrically connected to both the detection circuit, the protection circuit, and the control circuit.

[0066] In this embodiment, the interface chip is electrically connected to the detection circuit, protection circuit, functional terminals of the interface, and control circuit through multiple pins. The interface chip can not only protect the control circuit but also detect whether there are foreign objects in the interface, thereby improving the reliability of the interface chip.

[0067] In some embodiments of this disclosure, the first pin located in the first region includes a first configuration channel pin, the second pin located in the second region includes a second configuration channel pin, and the second pin located in the third region includes a second ground pin.

[0068] In this embodiment, by setting a first configuration channel pin and a second configuration channel pin, the interface chip can also detect whether there are foreign objects in the interface through the first configuration channel terminal and the second configuration channel terminal, thereby improving the reliability of the interface chip.

[0069] In some embodiments of this disclosure, the first configuration channel pin is closer to the power management circuit than each of the plurality of first pins other than the first configuration channel pin, and the second configuration channel pin is closer to the power management circuit than each of the plurality of second pins other than the second configuration channel pin.

[0070] In this embodiment, the first configuration channel pin and the second configuration channel pin are located close to the power management circuit, which facilitates electrical connection with the power management circuit and reduces the complexity of the connection between the interface chip and the power management circuit.

[0071] In some embodiments of this disclosure, the first configuration channel pin is adjacent to a second communication pin among the plurality of first pins, the second configuration channel pin is adjacent to a fourth communication pin among the plurality of second pins, and the second ground pin is adjacent to a serial data pin among the plurality of second pins.

[0072] In this embodiment, the pins are arranged in an array, thereby reducing the complexity of the interface chip structure.

[0073] In some embodiments of this disclosure, both the first configuration channel pin and the second configuration channel pin are electrically connected to the detection circuit, and the second ground pin is electrically connected to the detection circuit, the protection circuit, and the control circuit.

[0074] In this embodiment, by adding a first configuration channel pin and a second configuration channel pin, the foreign object detection range of the interface is increased, thereby improving the reliability of the interface chip.

[0075] According to a third aspect of this disclosure, an electronic device is provided, the electronic device including the interface chip described above.

[0076] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0077] The interface circuit includes a detection circuit and a protection circuit. The detection circuit is electrically connected to at least one functional terminal of the interface, and the protection circuit is electrically connected to the detection circuit, at least some of the functional terminals, and the control circuit of the electronic device. By constructing the interface circuit with a detection circuit and a protection circuit, the interface circuit can not only detect the presence of foreign objects on the interface but also protect the control circuit, thereby improving the reliability of the interface circuit. Moreover, since the detection circuit and the protection circuit can be electrically connected to the same functional terminal, the number of lines in the interface circuit is reduced, thus reducing the complexity of the interface circuit.

[0078] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0079] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the present invention.

[0080] Figure 1 This is a schematic diagram of the structure of an interface circuit provided in an exemplary embodiment of the present disclosure;

[0081] Figure 2 This is a schematic diagram of the structure of an interface circuit provided in another exemplary embodiment of this disclosure;

[0082] Figure 3 This is a schematic diagram of the structure of an interface circuit provided in another exemplary embodiment of this disclosure;

[0083] Figure 4 This is a schematic diagram of the structure of an interface circuit provided in another exemplary embodiment of this disclosure;

[0084] Figure 5 This is a schematic diagram of the structure of an interface circuit provided in another exemplary embodiment of this disclosure;

[0085] Figure 6 This is a schematic diagram of the structure of an interface circuit provided in another exemplary embodiment of this disclosure;

[0086] Figure 7 This is a schematic diagram of the structure of an interface circuit provided in another exemplary embodiment of this disclosure;

[0087] Figure 8 This is a schematic diagram of the structure of an interface chip provided in an exemplary embodiment of the present disclosure;

[0088] Figure 9 This is a schematic diagram of the structure of an interface chip provided in another exemplary embodiment of this disclosure;

[0089] Figure 10 This is a schematic diagram of the structure of an interface chip provided in another exemplary embodiment of this disclosure;

[0090] Figure 11 This is a schematic diagram of the structure of an interface chip provided in another exemplary embodiment of this disclosure;

[0091] Figure 12 This is a schematic diagram of the structure of an interface chip provided in another exemplary embodiment of this disclosure;

[0092] Figure 13 This is a system block diagram of an electronic device provided in an exemplary embodiment of the present disclosure.

[0093] In the picture:

[0094] 1-First overvoltage protection circuit; 2-Second overvoltage protection circuit; 3-First switch; 4-Second switch; 5-Control chip; 10-Detection circuit; 20-Protection circuit; 21-First protection circuit; 22-First switch circuit; 23-Second protection circuit; 24-Second switch circuit; 30-Control circuit; 40-Power management circuit; 50-Gating circuit; 60-Communication circuit; 400-Electronic device; 402-Processing component; 404-Memory; 406-Power supply component; 408-Multimedia component; 410-Audio component; 412-Input / output interface; 414-Sensor component; 416-Communication component; 420-Processor; AP-Application processor; MUX-Multiplexer; P-Function terminal; SBU1-First sideband terminal; SBU2-Second sideband terminal ; DP - First communication terminal; DN - Second communication terminal; CC1 - First configuration channel terminal; CC2 - Second configuration channel terminal; Pin1 - First pin; Pin2 - Second pin; P-SBU1 - First sideband pin; P-SBU2 - Second sideband pin; P-SBUH1 - Third sideband pin; P-SBUH2 - Fourth sideband pin; P-DP - First communication pin; P-DN - Second communication pin; P-DPH - Third communication pin; P-DNH - Fourth communication pin; P-CC1 - First configuration channel pin; P-CC2 - Second configuration channel pin; P-SDA - Serial data pin; P-SCL - Serial clock pin; P-GND1 - First ground pin; P-GND2 - Second ground pin; P-VCC - Power supply pin. Detailed Implementation

[0095] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this invention as detailed in the appended claims. It should also be understood that the term “and / or” as used herein refers to any or all possible combinations including one or more of the associated listed items.

[0096] Electronic devices are equipped with interfaces, through which external devices are electrically connected. For example, chargers, headphones, and other external devices can be plugged into the interface for electrical connection. The interface contains multiple functional terminals, each with its own function. These terminals work together to enable the functionality of the external device. For instance, a configuration channel terminal transmits configuration signals, a power supply terminal transmits electrical energy, and a communication terminal transmits differential signals.

[0097] An exemplary embodiment of this disclosure provides an interface circuit, such as Figure 1 As shown, the interface circuit includes a first overvoltage protection circuit 1, a second overvoltage protection circuit 2, a first switch 3, and a second switch 4. The first terminal of the first overvoltage protection circuit 1 is electrically connected to the first sideband terminal SBU1 of the interface, the second terminal is electrically connected to the second sideband terminal SBU2 of the interface, the third terminal is electrically connected to the first terminal of the first switch 3, and the fourth terminal is electrically connected to the second terminal of the first switch 3. The third and fourth terminals of the first switch 3 are respectively electrically connected to the first and second pins of the control chip 5. The first terminal of the second overvoltage protection circuit 2 is electrically connected to the first communication terminal DP of the interface, the second terminal is electrically connected to the second communication terminal DN of the interface, the third terminal is electrically connected to the first terminal of the second switch 4, and the fourth terminal is electrically connected to the second terminal of the second switch 4. The third and fourth terminals of the second switch 4 are respectively electrically connected to the third and fourth pins of the control chip 5. When the first overvoltage protection circuit 1 detects a large voltage transmitted through the first sideband terminal SBU1 and / or the second sideband terminal SBU2, it triggers the first switch 3 to open to protect the control chip 5. When the second overvoltage protection circuit 2 detects a high voltage transmitted through the first communication terminal DP and / or the second communication terminal DN, it triggers the second switch 4 to open to protect the control chip 5. However, when foreign objects are present in the interface, short circuits may occur between the functional terminals of the interface, leading to damage to the electronic equipment. Since the interface circuit can only provide overvoltage protection for the control chip 5 and does not have foreign object detection capabilities, the interface circuit suffers from low reliability.

[0098] An exemplary embodiment of this disclosure provides an interface circuit, such as Figure 2 As shown, the interface circuit includes a detection circuit 10 and a protection circuit 20. The detection circuit 10 is electrically connected to at least one functional terminal P of the interface, and is used to detect the electrical information of the functional terminal P, which reflects the presence of foreign objects in the interface. The protection circuit 20 is electrically connected to the detection circuit 10, at least some of the functional terminals P, and the control circuit 30 of the electronic device, and is used to protect the control circuit 30.

[0099] In this embodiment, the interface circuit includes a detection circuit and a protection circuit. The detection circuit is electrically connected to at least one functional terminal of the interface, and the protection circuit is electrically connected to the detection circuit, at least some of the functional terminals, and the control circuit of the electronic device. By using a detection circuit and a protection circuit to form the interface circuit, the interface circuit can not only detect the presence of foreign objects on the interface but also protect the control circuit, thereby improving the reliability of the interface circuit. Moreover, since the detection circuit and the protection circuit can be electrically connected to the same functional terminal, the number of lines in the interface circuit is reduced, thereby reducing the complexity of the interface circuit.

[0100] For example, the detection circuit 10 and the protection circuit 20 can be electrically connected to the same functional terminal P, or they can be electrically connected to different functional terminals P respectively. Foreign objects include, but are not limited to, liquids, dust, and metals. Interfaces include, but are not limited to, one of the following: Type-A interface, Type-B interface, Type-C interface, and Micro USB interface.

[0101] In one embodiment, the detection circuit 10 includes an impedance detection circuit. The impedance detection circuit is electrically connected to at least one functional terminal P, and is used to detect the impedance of the functional terminal P as electrical information.

[0102] In this embodiment, the impedance value of the functional terminals is fixed when there are no foreign objects in the interface, but changes when foreign objects are present. An impedance detection circuit detects the impedance of the functional terminals to determine if foreign objects are present in the interface, thereby improving the reliability of the interface circuit.

[0103] For example, the impedance detection circuit can output either an impedance value or a result indicating the presence of foreign objects. When there are no foreign objects in the interface, the impedance detection circuit detects a higher impedance to ground value. When there are foreign objects in the interface, the impedance detection circuit detects a lower impedance to ground value. When the impedance detection circuit outputs a result indicating the presence of foreign objects, the impedance detection circuit includes, in addition to a voltage divider circuit and a logic circuit for converting voltage to impedance, a circuit or processing circuit consisting of an operational amplifier circuit and a comparator circuit, etc., to perform impedance comparison.

[0104] For example, the detection circuit 10 may include one or more impedance detection circuits.

[0105] In one embodiment, the detection circuit 10 includes a voltage detection circuit. The voltage detection circuit is electrically connected to at least one functional terminal P, and the voltage detection circuit is used to detect the voltage of the functional terminal P as electrical information.

[0106] In this embodiment, the voltage of the functional terminals is within a preset range when there are no foreign objects in the interface, and exceeds the preset range when there are foreign objects in the interface. The voltage detection circuit detects the voltage of the functional terminals to determine whether there are foreign objects in the interface, thereby improving the reliability of the interface circuit.

[0107] For example, the voltage detection circuit can output either a voltage value or a result indicating the presence of foreign objects. When there are no foreign objects in the interface, the voltage detection circuit detects a larger voltage value. When there are foreign objects in the interface, the voltage detection circuit detects a smaller voltage value. When the voltage detection circuit outputs a result indicating the presence of foreign objects, the voltage detection circuit includes, in addition to a voltage divider circuit, a circuit or processing circuit consisting of an operational amplifier circuit and a comparator circuit, etc., to perform voltage comparison.

[0108] For example, the detection circuit 10 may include one or more voltage detection circuits.

[0109] In one embodiment, such as Figure 3 As shown, the functional terminal P includes a first sideband usage terminal SBU1, a second sideband usage terminal SBU2, a first communication terminal DP, and a second communication terminal DN. The detection circuit 10 is electrically connected to the first sideband usage terminal SBU1, the second sideband usage terminal SBU2, the first communication terminal DP, and the second communication terminal DN.

[0110] In this embodiment, since foreign objects may exist in different locations on the interface, the detection circuit is electrically connected to multiple functional terminals of the interface, increasing the detection range and thus improving the reliability of the interface circuit. Furthermore, since the first sideband terminal, the second sideband terminal, the first communication terminal, and the second communication terminal are commonly used functional terminals for signal transmission, foreign object detection on these terminals minimizes the impact of foreign objects on the electronic device, further improving the reliability of the interface circuit and reducing its complexity.

[0111] In one embodiment, the functional terminal P further includes a first configuration channel terminal CC1 and a second configuration channel terminal CC2. The detection circuit 10 is also electrically connected to both the first configuration channel terminal CC1 and the second configuration channel terminal CC2.

[0112] In this embodiment, by electrically connecting the detection circuit to the first configuration channel terminal and the second configuration channel terminal, the range of foreign object detection is expanded, thereby improving the reliability of the interface circuit. Furthermore, since the first and second configuration channel terminals are used to implement configuration functions, foreign object detection on these terminals further reduces the impact of interface foreign objects on the electronic device, thereby further improving the reliability of the interface circuit and reducing its complexity.

[0113] For example, the first configuration channel terminal CC1 and the second configuration channel terminal CC2 are also electrically connected to the power management circuit 40.

[0114] For example, the control circuit 30 may include an application processor and its peripheral circuits, etc.

[0115] In one embodiment, such as Figure 4 As shown, the interface circuit also includes a gating circuit 50. Each first terminal of the gating circuit 50 is electrically connected to a functional terminal P, and the second terminal of the gating circuit 50 is electrically connected to the detection circuit 10. The gating circuit 50 is used to selectively connect one of the multiple functional terminals P to the detection circuit 10.

[0116] In this embodiment, by electrically connecting the gating circuit between the detection circuit and multiple functional terminals, the detection circuit only needs to include one impedance detection circuit or voltage detection circuit to detect the electrical information of multiple functional terminals, thereby reducing the complexity of the interface circuit structure. Moreover, since the gating circuit can electrically connect as many functional terminals as possible, it can increase the number of functional terminals detected by the detection circuit, thereby improving the reliability of the interface circuit.

[0117] For example, the gating circuit 50 may be configured with a preset gating sequence, and the gating circuit 50 may sequentially turn on each functional terminal P and the detection circuit 10 according to the preset gating sequence. The gating circuit 50 may also be controlled by the detection circuit 10 or the control circuit 30 to turn on the selected functional terminal P and the detection circuit 10. The gating circuit may be composed of multiple transistors electrically connected, or it may be a multiplexer (MUX).

[0118] In one embodiment, such as Figure 5 As shown, the functional terminal P includes a first sideband usage terminal SBU1 and a second sideband usage terminal SBU2. The protection circuit 20 includes a first protection circuit 21 and a first switching circuit 22. The first protection circuit 21 is electrically connected between the first sideband usage terminal SBU1, the second sideband usage terminal SBU2, the first terminal of the control circuit 30, and the second terminal of the control circuit 30. The first protection circuit 21 is used to trigger overvoltage protection and / or overcurrent protection. The first switching circuit 22 is electrically connected between the first sideband usage terminal SBU1, the second sideband usage terminal SBU2, the first terminal of the control circuit 30, and the second terminal of the control circuit 30, and is also electrically connected to the first protection circuit 21. The first switching circuit 22 is used to disconnect when the first protection circuit 21 triggers overvoltage protection and / or overcurrent protection, and to select the corresponding terminal of the first sideband usage terminal SBU1 and the second sideband usage terminal SBU2 to be turned on by the control circuit 30.

[0119] In this embodiment, when the first protection circuit detects that the voltage and / or current flowing into the first sideband terminal and the second sideband terminal is large, the first switching circuit is disconnected to prevent excessive voltage and / or current flowing into the control circuit from damaging the control circuit, thereby improving the reliability of the interface circuit. Furthermore, by reusing the first switching circuit, the reversible insertion function of the interface can be realized, further improving the reliability of the interface circuit.

[0120] For example, the first protection circuit 21 may include an overvoltage protection circuit and / or an overcurrent protection circuit. The first terminal of the first switching circuit 22 is electrically connected to the first sideband using terminal SBU1, the second terminal is electrically connected to the second sideband using terminal SBU2, the third terminal is electrically connected to the first terminal of the first protection circuit 21, and the fourth terminal is electrically connected to the second terminal of the first protection circuit 21. The third terminal of the first protection circuit 21 is electrically connected to the first terminal of the control circuit 30, and the fourth terminal is electrically connected to the second terminal of the control circuit 30. Alternatively, the first terminal of the first protection circuit 21 is electrically connected to the first sideband using terminal SBU1, the second terminal is electrically connected to the second sideband using terminal SBU2, the third terminal is electrically connected to the first terminal of the first switching circuit 22, and the fourth terminal is electrically connected to the second terminal of the first switching circuit 22. The third terminal of the first switching circuit 22 is electrically connected to the first terminal of the control circuit 30, and the fourth terminal is electrically connected to the second terminal of the control circuit 30. The detection circuit 10 may be electrically connected to both the first and second terminals of the first protection circuit 21, or it may be electrically connected to both the third and fourth terminals of the first protection circuit 21.

[0121] For example, the first switching circuit 22 includes, but is not limited to, at least one of the following structures: a single-pole double-throw switch, a double-pole double-throw switch, and multiple electrically connected transistors. Under the action of the first switching circuit 22, the first sideband terminal SBU1 can be electrically connected to the first terminal of the control circuit 30 and the second sideband terminal SBU2 can be electrically connected to the second terminal of the control circuit 30, or the first sideband terminal SBU1 can be electrically connected to the second terminal of the control circuit 30 and the second sideband terminal SBU2 can be electrically connected to the first terminal of the control circuit 30, so as to realize the reversible insertion switching function of the interface.

[0122] In one embodiment, the functional terminal P includes a first communication terminal DP and a second communication terminal DN. The protection circuit 20 includes a second protection circuit 23 and a second switching circuit 24. The second protection circuit 23 is electrically connected between the first communication terminal DP, the second communication terminal DN, the third terminal of the control circuit 30, and the fourth terminal of the control circuit 30, and is used to trigger overvoltage protection and / or overcurrent protection. The second switching circuit 24 is electrically connected between the first communication terminal DP, the second communication terminal DN, the third terminal of the control circuit 30, and the fourth terminal of the control circuit 30, and is also electrically connected to the second protection circuit 23, and is used to disconnect when the second protection circuit 23 triggers overvoltage protection and / or overcurrent protection.

[0123] In this embodiment, when the second protection circuit detects that the voltage and / or current flowing into the first communication terminal and the second communication terminal is large, the second switch circuit is disconnected to prevent the voltage and / or current flowing into the control circuit from being too large and causing damage to the control circuit, thereby improving the reliability of the interface circuit.

[0124] For example, the second protection circuit 23 may include an overvoltage protection circuit and an overcurrent protection circuit. The first terminal of the second switching circuit 24 is electrically connected to the first communication terminal DP, the second terminal is electrically connected to the second communication terminal DN, the third terminal is electrically connected to the first terminal of the second protection circuit 23, and the fourth terminal is electrically connected to the second terminal of the second protection circuit 23. The third terminal of the second protection circuit 23 is electrically connected to the third terminal of the control circuit 30, and the fourth terminal is electrically connected to the fourth terminal of the control circuit 30. The detection circuit 10 may be electrically connected to both the third and fourth terminals of the second protection circuit 23. Alternatively, the first terminal of the second protection circuit 23 is electrically connected to the first communication terminal DP, the second terminal is electrically connected to the second communication terminal DN, the third terminal is electrically connected to the first terminal of the second switching circuit 24, and the fourth terminal is electrically connected to the second terminal of the second switching circuit 24. The third terminal of the second switching circuit 24 is electrically connected to the first terminal of the control circuit 30, and the fourth terminal is electrically connected to the second terminal of the control circuit 30. The detection circuit 10 may be electrically connected to both the first and second terminals of the second protection circuit 23, or it may be electrically connected to both the third and fourth terminals of the second protection circuit 23.

[0125] For example, the second switching circuit 24 includes, but is not limited to, at least one of the following structures: a single-pole single-throw switch, a single-pole double-throw switch, a double-pole double-throw switch, and a plurality of electrically connected transistors.

[0126] In one embodiment, the second protection circuit 23 is electrically connected to the third and fourth terminals of the control circuit 30 via the power management circuit 40.

[0127] In this embodiment, since the voltages of the first and second communication terminals are relatively high, directly inputting them to the control circuit would damage the control circuit. By using a power management circuit to reduce the voltages of the first and second communication terminals before inputting them to the control circuit, damage to the control circuit is avoided, thereby improving the reliability of the interface circuit.

[0128] In one embodiment, the interface circuit further includes a communication circuit 60. The communication circuit 60 is electrically connected to both the detection circuit 10 and the control circuit 30, and is used to transmit electrical information from the detection circuit 10 to the control circuit 30.

[0129] In this embodiment, since the communication circuit can transmit the electrical information from the detection circuit to the control circuit, the control circuit can perform corresponding actions based on the electrical information to avoid the influence of foreign objects, thereby improving the reliability of the interface circuit. Simultaneously, by reusing the control circuit of the electronic device, the interface circuit does not need to be included, thus reducing its complexity.

[0130] In one embodiment, the communication circuit 60 is also electrically connected to the protection circuit 20, and the communication circuit 60 is also used to transmit the configuration signal of the control circuit 30 to the protection circuit 20.

[0131] In this embodiment, the control circuit can transmit configuration signals to the protection circuit through the communication circuit to flexibly adjust the threshold for triggering protection by the protection circuit, thereby improving the reliability of the interface circuit.

[0132] For example, the communication circuit 60 may also be electrically connected to the gating circuit 50 to control the gating sequence of the gating circuit 50.

[0133] An exemplary embodiment of this disclosure provides an interface circuit, such as Figure 6 As shown, the interface circuit includes a detection circuit 10, a first overvoltage protection circuit 1, a first switching circuit 22, a second overvoltage protection circuit 2, a second switching circuit 24, a multiplexer MUX, and a communication circuit 60. The first terminal of the first overvoltage protection circuit 1 is electrically connected to the first sideband terminal SBU1, the second terminal is electrically connected to the second sideband terminal SBU2, the third terminal is electrically connected to the first terminal of the first switching circuit 22, and the fourth terminal is electrically connected to the second terminal of the first switching circuit 22. The third terminal of the first switching circuit 22 is electrically connected to both the first terminal of the multiplexer MUX and the first terminal of the application processor AP, and the fourth terminal is electrically connected to both the second terminal of the multiplexer MUX and the second terminal of the application processor AP. The first terminal of the second overvoltage protection circuit 2 is electrically connected to the first communication terminal DP, the second terminal is electrically connected to the second communication terminal DN, the third terminal is electrically connected to the first terminal of the second switching circuit 24, and the fourth terminal is electrically connected to the second terminal of the second switching circuit 24. The third terminal of the second switching circuit 24 is electrically connected to both the third first terminal of the multiplexer MUX and the first terminal of the power management circuit 40. The fourth terminal is electrically connected to both the fourth first terminal of the multiplexer MUX and the second terminal of the power management circuit 40. The third terminal of the power management circuit 40 is electrically connected to the third terminal of the application processor AP, and the fourth terminal of the power management circuit 40 is electrically connected to the fourth terminal of the application processor AP. The second terminal of the multiplexer MUX is electrically connected to the detection circuit 10. The communication circuit 60 is electrically connected to the detection circuit 10, the first overvoltage protection circuit 1 of the multiplexer MUX, the second overvoltage protection circuit 2 of the multiplexer MUX, the application processor AP, and the multiplexer MUX. The first configuration channel terminal CC1 and the second configuration channel terminal CC2 are electrically connected to the fifth and sixth terminals of the power management circuit 40.

[0134] For example, such as Figure 7 As shown, the first configuration channel terminal CC1 is electrically connected to the fifth first terminal of the multiplexer MUX. The second configuration channel terminal CC2 is electrically connected to the sixth first terminal of the multiplexer MUX.

[0135] An exemplary embodiment of this disclosure provides an interface chip, which includes the interface circuit described above.

[0136] In this embodiment, by integrating the interface circuit onto the interface chip, the size of the interface circuit can be reduced, thereby reducing the size of the electronic device.

[0137] In one embodiment, such as Figure 8 As shown, the interface chip also includes multiple first pins Pin1 and multiple second pins Pin2. The multiple first pins Pin1 are electrically connected to the detection circuit 10, the protection circuit 20 and multiple functional terminals P, and the multiple second pins Pin2 are electrically connected to the detection circuit 10, the protection circuit 20 and the control circuit 30.

[0138] In this embodiment, by dividing the first pin and the second pin, the first pin is used to electrically connect to the functional terminal, and the second pin is used to electrically connect to the control circuit. The arrangement of the first pin and the second pin can be appropriately arranged to reduce the number and length of the lines, thereby reducing the complexity of the interface chip.

[0139] In one embodiment, a plurality of first pins Pin1 are arranged in a first region along a first preset direction, a portion of second pins Pin2 are arranged in a second region along the first preset direction, and another portion of second pins Pin2 are arranged in a third region along the first preset direction. The first region, the second region, and the third region are arranged along a second preset direction, or the first region, the third region, and the second region are arranged along the second preset direction. The first preset direction and the second preset direction are perpendicular.

[0140] In this embodiment, since both the first and second pins are arranged along a first preset direction, and the first, second, and third regions are arranged along a second preset direction, the first and second pins are arranged in an array on the interface chip, thereby reducing the complexity of the interface chip structure. Furthermore, because the regions where the first and second pins are located are different, it facilitates electrical connection between the first pin and the functional terminal, and between the second pin and the control circuit, further reducing the complexity of the interface chip.

[0141] In one embodiment, the first region is closer to the interface than the second and third regions, and the second and third regions are closer to the control circuit 30 than the first region.

[0142] In this embodiment, since the first pin of the first region needs to be electrically connected to the functional terminal of the interface, placing the first region close to the interface facilitates the electrical connection between the interface and the interface chip. Similarly, the second pins of the second and third regions need to be electrically connected to the control circuit of the electronic device, and placing the second and third regions close to the control circuit facilitates the electrical connection between the control circuit and the interface chip. By placing the first region close to the interface and the second and third regions close to the control circuit, the interface chip is facilitated to connect to both the interface and the control circuit, thereby improving the reliability of the interface chip.

[0143] In one embodiment, multiple first pins (Pin1) and multiple second pins (Pin2) that perform the same function are arranged adjacently.

[0144] In this embodiment, by arranging multiple pins with the same function adjacent to each other, the difference in line connection length between multiple pins with the same function and the interface or control circuit is small, avoiding problems such as different timing of signals transmitted by pins with the same function, thereby improving the reliability of the interface chip.

[0145] In one embodiment, such as Figure 9 As shown, the first pin Pin1 located in the first region includes the adjacent first sideband use pin P-SBU1 and second sideband use pin P-SBU2, as well as the adjacent first communication pin P-DP and second communication pin P-DN.

[0146] In this embodiment, by setting the first sideband pin, the second sideband pin, the third sideband pin, and the fourth sideband pin in the first area, it is convenient to electrically connect to the functional terminals of the interface.

[0147] In one embodiment, the first sideband pin P-SBU1, the second sideband pin P-SBU2, the first communication pin P-DP, and the second communication pin P-DN are arranged sequentially along a first preset direction.

[0148] In this embodiment, by arranging the first pins sequentially along a first preset direction, it is not only convenient to connect the first pins to the functional terminals of the interface, but also to reduce the complexity of the circuit connection.

[0149] In one embodiment, the first sideband pin is electrically connected to the detection circuit 10, the protection circuit 20, and the first sideband terminal SBU1; the second sideband pin is electrically connected to the detection circuit 10, the protection circuit 20, and the second sideband terminal SBU2; the first communication pin is electrically connected to the detection circuit 10, the protection circuit 20, and the first communication terminal DP; and the second communication pin is electrically connected to the detection circuit 10, the protection circuit 20, and the second communication terminal DN.

[0150] In this embodiment, by electrically connecting multiple pins of the interface chip to the detection circuit, protection circuit, and functional terminals of the interface, the interface chip can not only protect the control circuit but also detect the presence of foreign objects on the interface, thereby improving the reliability of the interface chip. Furthermore, some pins of the interface chip can be electrically connected to both the detection circuit and the protection circuit simultaneously, reducing the number of lines in the interface chip and thus lowering its complexity.

[0151] In one embodiment, the second pin Pin2 located in the second region includes adjacent third sideband pins P-SBU1H and fourth sideband pins P-SBU2H, as well as adjacent third communication pins P-DPH and fourth communication pins P-DNH.

[0152] In this embodiment, by setting the third sideband pin, the fourth sideband pin, the third communication pin, and the fourth communication pin in the second area, it is convenient to connect them to the control circuit.

[0153] In one embodiment, the third sideband pin P-SBU1H, the fourth sideband pin P-SBU2H, the third communication pin P-DPH, and the fourth communication pin P-DNH are arranged sequentially along a first preset direction.

[0154] In this embodiment, by arranging the third sideband pin, the fourth sideband pin, the third communication pin, and the fourth communication pin sequentially along the first preset direction, it is not only convenient to connect these pins to the control circuit, but also to reduce the complexity of the circuit connection.

[0155] In one embodiment, the third sideband uses pins that are electrically connected to both the protection circuit 20 and the control circuit 30, the fourth sideband uses pins that are electrically connected to both the protection circuit 20 and the control circuit 30, the third communication pin is electrically connected to both the protection circuit 20 and the control circuit 30, and the fourth communication pin is electrically connected to both the protection circuit 20 and the control circuit 30.

[0156] In this embodiment, the interface chip is electrically connected to the detection circuit, protection circuit, functional terminals of the interface, and control circuit through multiple pins. This allows the interface chip to not only protect the control circuit but also detect the presence of foreign objects on the interface, thereby improving its reliability. Furthermore, since some pins of the interface chip can be electrically connected to both the detection and protection circuits simultaneously, the number of lines on the interface chip is reduced, thus lowering its complexity.

[0157] In one embodiment, the third communication pin P-DPH and the fourth communication pin P-DNH are electrically connected to the control circuit 30 through the power management circuit 40.

[0158] In this embodiment, since the voltages of the first and second communication pins are relatively high, directly inputting them to the control circuit would damage the control circuit. By using a power management circuit to reduce the voltage transmitted to the third and fourth communication pins before inputting them to the control circuit, the reliability of the interface chip is improved.

[0159] In one embodiment, the second pin Pin2 located in the third region includes adjacent serial data pin P-SDA and serial clock pin P-SCL, as well as adjacent first ground pin P-GND1 and power supply pin P-VCC.

[0160] In this embodiment, by placing the serial data pin, serial clock pin, first ground pin, and power supply pin in the third area, electrical connection with the control circuit and power management circuit is facilitated. By placing pins with different functions in corresponding areas, electrical connection with the interface and control circuit is facilitated, thereby reducing the complexity of the interface chip. Furthermore, by setting the aforementioned 12 pins on the interface chip, not only can multiple functions of the interface circuit be realized, but the size of the interface chip can also be reduced.

[0161] In one embodiment, the serial data pin P-SDA, the serial clock pin P-SCL, the first ground pin P-GND1, and the power supply pin P-VCC are arranged sequentially along a first preset direction.

[0162] In this embodiment, by arranging the serial data pin, serial clock pin, first ground pin, and power supply pin sequentially along a first preset direction, it is not only convenient to connect these pins to the control circuit and power management circuit, but also to reduce the complexity of the line connection.

[0163] In one embodiment, the serial data pin P-SDA is electrically connected to both the detection circuit 10 and the control circuit 30, the serial clock pin P-SCL is electrically connected to both the detection circuit 10 and the control circuit 30, the first ground pin P-GND1 is electrically connected to both the detection circuit 10, the protection circuit 20, and the control circuit 30, and the power supply pin P-VCC is electrically connected to both the detection circuit 10, the protection circuit 20, and the control circuit 30.

[0164] In this embodiment, the interface chip is electrically connected to the detection circuit, protection circuit, functional terminals of the interface, and control circuit through multiple pins. This allows the interface chip to not only protect the control circuit but also detect the presence of foreign objects on the interface, thereby improving its reliability. Furthermore, since some pins of the interface chip can be electrically connected to both the detection and protection circuits simultaneously, the number of lines on the interface chip is reduced, thus lowering its complexity.

[0165] In one embodiment, such as Figure 10 As shown, the first pin Pin1 in the first region includes a first configuration channel pin P-CC1, the second pin in the second region includes a second configuration channel pin P-CC2, and the second pin Pin2 in the third region includes a second ground pin P-GND2.

[0166] In this embodiment, by setting a first configuration channel pin and a second configuration channel pin, the interface chip can also detect whether there are foreign objects in the interface through the first configuration channel terminal and the second configuration channel terminal, thereby improving the reliability of the interface chip.

[0167] In one embodiment, the first configuration channel pin P-CC1 is closer to the power management circuit 40 than each of the plurality of first pins Pin1 other than the first configuration channel pin P-CC1, and the second configuration channel pin P-CC2 is closer to the power management circuit 40 than each of the plurality of second pins Pin2 other than the second configuration channel pin P-CC2.

[0168] In this embodiment, since the first configuration channel pin and the second configuration channel pin need to be electrically connected to the power management circuit, the first configuration channel pin and the second configuration channel pin are located close to the power management circuit, which facilitates the electrical connection with the power management circuit and reduces the complexity of the connection between the interface chip and the power management circuit.

[0169] In one embodiment, the first configuration channel pin P-CC1 is adjacent to the second communication pin P-DN of Pin1 among a plurality of first pins, the second configuration channel pin P-CC2 is adjacent to the fourth communication pin P-DNH of Pin2 among a plurality of second pins, and the second ground pin P-GND2 is adjacent to the serial data pin P-SDA of Pin2 among a plurality of second pins.

[0170] In this embodiment, the pins are arranged in an array, thereby reducing the complexity of the interface chip structure.

[0171] In one embodiment, the first configuration channel pin P-CC1 and the second configuration channel pin P-CC2 are both electrically connected to the detection circuit 10, and the second ground pin P-GND2 is electrically connected to the detection circuit 10, the protection circuit 20 and the control circuit 30.

[0172] In this embodiment, by adding a first configuration channel pin and a second configuration channel pin, the interface chip can perform foreign object detection on the interface through the first configuration channel pin and the second configuration channel pin, thereby increasing the foreign object detection range of the interface and improving the reliability of the interface chip.

[0173] An exemplary embodiment of this disclosure provides an interface chip, such as Figure 9As shown, the interface chip includes a first sideband pin P-SBU1, a second sideband pin P-SBU2, a third sideband pin P-SBU1H, a fourth sideband pin P-SBU2H, a first communication pin P-DP, a second communication pin P-DN, a third communication pin P-DPH, a fourth communication pin P-DNH, a serial data pin P-SDA, a serial clock pin P-SCL, a first ground pin P-GND1, and a power supply pin P-VCC. Along the first preset direction, the first sideband pin P-SBU1, the second sideband pin P-SBU2, the first communication pin P-DP, and the second communication pin P-DN are arranged in sequence. The third sideband pin P-SBU1H, the fourth sideband pin P-SBU2H, the third communication pin P-DPH, and the fourth communication pin P-DNH are arranged in sequence. The serial clock pin P-SCL, the serial data pin P-SDA, the first ground pin P-GND1, and the power supply pin P-VCC are arranged in sequence. Along the second preset direction, the first sideband pin P-SBU1, the third sideband pin P-SBU1H, and the serial clock pin P-SCL are arranged in sequence; the second sideband pin P-SBU2, the fourth sideband pin P-SBU2H, and the serial data pin P-SDA are arranged in sequence; the first communication pin P-DP, the third communication pin P-DPH, and the first ground pin P-GND1 are arranged in sequence; and the second communication pin P-DN, the fourth communication pin P-DNH, and the power supply pin P-VCC are arranged in sequence. The first preset direction is perpendicular to the second preset direction.

[0174] For example, such as Figure 11As shown, the first sideband pin P-SBU1 is electrically connected to both the first sideband terminal SBU1 of the interface and the first terminal of the first overvoltage protection circuit 1. The second sideband pin P-SBU2 is electrically connected to both the second sideband terminal SBU2 of the interface and the second terminal of the first overvoltage protection circuit 1. The first communication pin P-DP is electrically connected to both the first communication terminal DP of the interface and the first terminal of the second overvoltage protection circuit 2. The second communication pin P-DN is electrically connected to both the second communication terminal DN of the interface and the second terminal of the second overvoltage protection circuit 2. The third sideband pin P-SBU1H is electrically connected to both the third terminal of the first switching circuit 22, the first terminal of the multiplexer MUX, and the first terminal of the application processor AP. The fourth sideband pin P-SBU2H is electrically connected to both the fourth terminal of the first switching circuit 22, the second terminal of the multiplexer MUX, and the second terminal of the application processor AP. The third communication pin, P-DPH, is electrically connected to the third terminal of the second switching circuit 24, the multiplexer MUX, and the first terminal of the power management circuit 40. The fourth communication pin, P-DNH, is electrically connected to the fourth terminal of the second switching circuit 24, the multiplexer MUX, and the second terminal of the power management circuit 40. The third terminal of the power management circuit 40 is electrically connected to the third terminal of the application processor AP, and the fourth terminal of the power management circuit 40 is electrically connected to the fourth terminal of the application processor AP. The first ground pin, P-GND1, and the power supply pin, P-VCC, are both electrically connected to the detection circuit 10, the first overvoltage protection circuit 1, the second protection circuit 23, the communication circuit 60, and the power management circuit 40. The serial clock pin, P-SCL, is electrically connected to the fifth terminal of the application processor AP and the communication circuit 60. The serial data pin, P-SDA, is electrically connected to the sixth terminal of the application processor AP and the communication circuit 60.

[0175] For example, such as Figure 10As shown, the interface chip also includes a first configuration channel pin P-CC1, a second configuration channel pin P-CC2, and a second ground pin P-GND2. Along a first preset direction, the second communication pin P-DN and the first configuration channel pin P-CC1 are arranged in sequence, the fourth communication pin P-DNH and the second configuration channel pin P-CC2 are arranged in sequence, and the second ground pin P-GND2 and the serial data pin P-SDA are arranged in sequence. Along the second preset direction, the first sideband pin P-SBU1, the third sideband pin P-SBU1H, and the second ground pin P-GND2 are arranged in sequence. The second sideband pin P-SBU2, the fourth sideband pin P-SBU2H, and the serial data pin P-SDA are arranged in sequence. The first communication pin P-DP, the third communication pin P-DPH, and the serial clock pin P-SCL are arranged in sequence. The second communication pin P-DN, the fourth communication pin P-DNH, and the first ground pin P-GND1 are arranged in sequence. The first configuration channel pin P-CC1, the second configuration channel pin P-CC2, and the power supply pin P-VCC are arranged in sequence.

[0176] For example, such as Figure 12 As shown, the first configuration channel pin P-CC1 is electrically connected to the first configuration channel terminal CC1 of the interface, the multiplexer MUX, and the fifth terminal of the power management circuit 40. The second configuration channel pin P-CC2 is electrically connected to the second configuration channel terminal CC2 of the interface, the multiplexer MUX, and the sixth terminal of the power management circuit 40. The second ground pin P-GND2 is electrically connected to the detection circuit 10, the first protection circuit 21, the second protection circuit 23, the communication circuit 60, and the power management circuit 40.

[0177] An exemplary embodiment of this disclosure provides an electronic device including the interface chip described above. The electronic device includes, for example, a mobile phone, a laptop computer, a tablet computer, and a wearable device.

[0178] refer to Figure 13 As shown, the electronic device 400 may include one or more of the following components: a processing component 402, a memory 404, a power supply component 406, a multimedia component 408, an audio component 410, an input / output (I / O) interface 412, a sensor component 414, and a communication component 416.

[0179] Processing component 402 typically controls the overall operation of electronic device 400, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 402 may include one or more modules to facilitate interaction between processing component 402 and other components. For example, processing component 402 may include a multimedia module to facilitate interaction between multimedia component 408 and processing component 402.

[0180] Memory 404 is configured to store various types of data to support the operation of electronic device 400. Examples of this data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, videos, etc. Memory 404 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0181] Power supply component 406 provides power to various components of electronic device 400. Power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 400.

[0182] Multimedia component 408 includes a screen that provides an output interface between electronic device 400 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 408 includes a front-facing camera module and / or a rear-facing camera module. When electronic device 400 is in an operating mode, such as shooting mode or video mode, the front-facing camera module and / or rear-facing camera module may receive external multimedia data. Each front-facing camera module and rear-facing camera module may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0183] Audio component 410 is configured to output and / or input audio signals. For example, audio component 410 includes a microphone (MIC) configured to receive external audio signals when electronic device 400 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 404 or transmitted via communication component 416. In some embodiments, audio component 410 also includes a speaker for outputting audio signals.

[0184] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0185] Sensor assembly 414 includes one or more sensors for providing state assessments of various aspects of electronic device 400. For example, sensor assembly 414 may detect the on / off state of electronic device 400, the relative positioning of components such as the display and keypad of electronic device 400, changes in position of electronic device 400 or a component of electronic device 400, the presence or absence of user contact with electronic device 400, orientation or acceleration / deceleration of electronic device 400, and temperature changes of electronic device 400. Sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 414 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0186] Communication component 416 is configured to facilitate wired or wireless communication between electronic device 400 and other terminals. Electronic device 400 can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G, 5G, or combinations thereof. In one exemplary embodiment, communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 416 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0187] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing terminals (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0188] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0189] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0190] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the utility models disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0191] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. An interface circuit, characterized by The interface circuit includes: A detection circuit is provided, wherein the detection circuit is electrically connected to at least one functional terminal of the interface, the detection circuit is used to detect the electrical information of the functional terminal, and the electrical information is used to reflect whether there is a foreign object in the interface; A protection circuit is provided, which is electrically connected to the detection circuit, at least a portion of the functional terminals, and the control circuit of the electronic device. The protection circuit is used to protect the control circuit.

2. The interface circuit of claim 1, wherein, The detection circuit includes: An impedance detection circuit, wherein the impedance detection circuit is electrically connected to at least one of the functional terminals, and the impedance detection circuit is used to detect the impedance of the functional terminal as the electrical information; or, A voltage detection circuit is provided, wherein the voltage detection circuit is electrically connected to at least one of the functional terminals, and the voltage detection circuit is used to detect the voltage of the functional terminals as electrical information.

3. The interface circuit of claim 1, wherein, The functional terminals include a first sideband usage terminal, a second sideband usage terminal, a first communication terminal, and a second communication terminal; the detection circuit is electrically connected to the first sideband usage terminal, the second sideband usage terminal, the first communication terminal, and the second communication terminal.

4. The interface circuit of claim 3, wherein, The functional terminals also include a first configuration channel terminal and a second configuration channel terminal; the detection circuit is also electrically connected to both the first configuration channel terminal and the second configuration channel terminal.

5. The interface circuit of claim 1, wherein, The functional terminals include a first sideband usage terminal and a second sideband usage terminal; the protection circuit includes: A first protection circuit is electrically connected between the first sideband terminal, the second sideband terminal, the first terminal of the control circuit, and the second terminal of the control circuit. The first protection circuit is used to trigger overvoltage protection and / or overcurrent protection. A first switching circuit is electrically connected between the first sideband usage terminal, the second sideband usage terminal, the first terminal of the control circuit, and the second terminal of the control circuit, and is also electrically connected to the first protection circuit. The first switching circuit is used to disconnect when the first protection circuit triggers overvoltage protection and / or overcurrent protection, and to select the first sideband usage terminal and the second sideband usage terminal corresponding to one end of the control circuit to be turned on.

6. The interface circuit of claim 1, wherein, The functional terminals include a first communication terminal and a second communication terminal; the protection circuit includes: The second protection circuit is electrically connected between the first communication terminal, the second communication terminal, the third terminal of the control circuit, and the fourth terminal of the control circuit. The second protection circuit is used to trigger overvoltage protection and / or overcurrent protection. The second switching circuit is electrically connected between the first communication terminal, the second communication terminal, the third terminal of the control circuit, and the fourth terminal of the control circuit, and is also electrically connected to the second protection circuit. The second switching circuit is used to disconnect when the second protection circuit triggers overvoltage protection and / or overcurrent protection.

7. The interface circuit of claim 6, wherein, The second protection circuit is electrically connected to the third and fourth terminals of the control circuit through the power management circuit.

8. The interface circuit of claim 1, wherein, The interface circuit also includes: A gating circuit, wherein each first terminal of the gating circuit is electrically connected to one of the functional terminals, and the second terminal of the gating circuit is electrically connected to the detection circuit, and the gating circuit is used to selectively connect one of the plurality of functional terminals to the detection circuit.

9. The interface circuit of any one of claims 1 to 8, wherein, The interface circuit also includes: A communication circuit is provided, which is electrically connected to both the detection circuit and the control circuit. The communication circuit is used to transmit electrical information from the detection circuit to the control circuit.

10. The interface circuit of claim 9, wherein, The communication circuit is also electrically connected to the protection circuit, and the communication circuit is also used to transmit the configuration signal of the control circuit to the protection circuit.

11. An interface chip, characterized by The interface chip includes the interface circuit as described in any one of claims 1 to 10.

12. The interface chip of claim 11, wherein, The interface chip also includes: Multiple first pins are electrically connected to the detection circuit, the protection circuit, and the multiple functional terminals; Multiple second pins are provided, and the multiple second pins are electrically connected to the detection circuit, the protection circuit and the control circuit.

13. The interface chip of claim 12, wherein, The plurality of first pins are arranged in a first preset direction in a first region, a portion of the second pins are arranged in a second region in a first preset direction, another portion of the second pins are arranged in a third region in a first preset direction, the first region, the second region and the third region are arranged in a second preset direction, or the first region, the third region and the second region are arranged in a second preset direction; Wherein, the first preset direction and the second preset direction are perpendicular.

14. The interface chip of claim 13, wherein, The first region is closer to the interface than the second and third regions, and the second and third regions are closer to the control circuit than the first region.

15. The interface chip of claim 13, wherein, The plurality of first pins and the plurality of second pins are arranged adjacently to perform the same function.

16. The interface chip of claim 13, wherein, The first pin located in the first region includes a first sideband use pin and a second sideband use pin arranged adjacent to each other, as well as a first communication pin and a second communication pin arranged adjacent to each other.

17. The interface chip of claim 16, wherein, The first sideband pin, the second sideband pin, the first communication pin, and the second communication pin are arranged sequentially along the first preset direction.

18. The interface chip according to claim 16, characterized in that, The first sideband uses pins that are electrically connected to the detection circuit, the protection circuit, and the first sideband uses terminals. The second sideband uses pins that are electrically connected to the detection circuit, the protection circuit, and the second sideband uses terminals. The first communication pin is electrically connected to the detection circuit, the protection circuit, and the first communication terminal. The second communication pin is electrically connected to the detection circuit, the protection circuit, and the second communication terminal.

19. The interface chip according to claim 13, characterized in that, The second pin located in the second region includes adjacent third sideband use pins and fourth sideband use pins, as well as adjacent third communication pins and fourth communication pins.

20. The interface chip according to claim 19, characterized in that, The third sideband pin, the fourth sideband pin, the third communication pin, and the fourth communication pin are arranged sequentially along the first preset direction.

21. The interface chip according to claim 19, characterized in that, The third sideband uses pins that are electrically connected to both the protection circuit and the control circuit. The fourth sideband uses pins that are electrically connected to both the protection circuit and the control circuit. The third communication pin is electrically connected to both the protection circuit and the control circuit. The fourth communication pin is electrically connected to both the protection circuit and the control circuit.

22. The interface chip according to claim 19, characterized in that, The third and fourth communication pins are electrically connected to the control circuit via a power management circuit.

23. The interface chip according to claim 13, characterized in that, The second pin located in the third region includes adjacent serial data pins and serial clock pins, as well as adjacent first ground pins and power supply pins.

24. The interface chip according to claim 23, characterized in that, The serial data pin, the serial clock pin, the first ground pin, and the power supply pin are arranged sequentially along the first preset direction.

25. The interface chip according to claim 23, characterized in that, The serial data pin is electrically connected to both the detection circuit and the control circuit; the serial clock pin is electrically connected to both the detection circuit and the control circuit; the first ground pin is electrically connected to both the detection circuit, the protection circuit, and the control circuit; and the power supply pin is electrically connected to both the detection circuit, the protection circuit, and the control circuit.

26. The interface chip according to any one of claims 13 to 25, characterized in that, The first pin located in the first region includes a first configuration channel pin, the second pin located in the second region includes a second configuration channel pin, and the second pin located in the third region includes a second ground pin.

27. The interface chip according to claim 26, characterized in that, The first configuration channel pin is closer to the power management circuit than each of the plurality of first pins other than the first configuration channel pin, and the second configuration channel pin is closer to the power management circuit than each of the plurality of second pins other than the second configuration channel pin.

28. The interface chip according to claim 26, characterized in that, The first configuration channel pin is adjacent to the second communication pin among the plurality of first pins, the second configuration channel pin is adjacent to the fourth communication pin among the plurality of second pins, and the second ground pin is adjacent to the serial data pin among the plurality of second pins.

29. The interface chip according to claim 26, characterized in that, Both the first configuration channel pin and the second configuration channel pin are electrically connected to the detection circuit, and the second ground pin is electrically connected to the detection circuit, the protection circuit, and the control circuit.

30. An electronic device, characterized in that, The electronic device includes the interface chip as described in any one of claims 11 to 29.

Images