Integrated circuit devices

Abstract

This invention provides an integrated circuit device including a dielectric structure on a semiconductor substrate, a plurality of active bonding pads in the dielectric structure, and a plurality of auxiliary bonding pads in the dielectric structure and laterally offset from the active bonding pads by a first distance, the first distance being greater than the spacing of the active bonding pads. The active bonding pads are electrically coupled to corresponding auxiliary bonding pads in the auxiliary bonding pads, so that the spare bonding pads have good electrical coupling, thereby improving the performance, reliability and yield of the integrated circuit device.

Description

Technical Field

[0001] Embodiments of this utility model relate to an integrated circuit device, and more particularly to an integrated circuit device comprising a bonding structure including an active bonding pad and an auxiliary bonding pad. Background Technology

[0002] Many modern electronic devices (such as smartphones, digital cameras, and automotive imaging systems) include image sensors. An image sensor comprises one or more photodetectors (such as photodiodes, phototransistors, and photoresistors) configured to absorb incident radiation and output an electrical signal corresponding to the incident radiation. Image sensors may include stacked chips to reduce the footprint of each pixel and increase device density. Utility Model Content

[0003] An embodiment of the present invention provides an integrated circuit device including a dielectric structure on a semiconductor substrate, a plurality of active bonding pads in the dielectric structure, and a plurality of auxiliary bonding pads in the dielectric structure and laterally offset from the active bonding pads by a first distance, the first distance being greater than the spacing of the active bonding pads, wherein the active bonding pads are electrically coupled to corresponding auxiliary bonding pads in the auxiliary bonding pads.

[0004] Embodiments of this utility model provide an integrated circuit device including a first integrated circuit chip, a second integrated circuit chip, and a bonding interface. The first integrated circuit chip includes a first substrate, a first interconnect structure on the first substrate, and a first bonding structure on the first interconnect structure. The first bonding structure includes a plurality of first active bonding pads, a plurality of first auxiliary bonding pads, and a plurality of dummy bonding pads, wherein at least one of the dummy bonding pads is laterally disposed between the first active bonding pads and the first auxiliary bonding pads. The second integrated circuit chip includes a second substrate, a second interconnect structure on the second substrate, and a second bonding structure on the second interconnect structure. The bonding interface is disposed between the first bonding structure and the second bonding structure. The first active bonding pads are configured to provide a first electrical connection between the first integrated circuit chip and the second integrated circuit chip, and the first auxiliary bonding pads are configured to provide a second electrical connection between the first integrated circuit chip and the second integrated circuit chip that repeats the first electrical connection.

[0005] Based on the above, the integrated circuit device of the present invention includes an active bonding pad, which facilitates electrical coupling between the devices of the first and second integrated circuit chips. A spare bonding pad is electrically coupled to a corresponding active bonding pad via a first interconnect structure of the first integrated circuit chip. A bonding defect region may be aligned with the active bonding pad, resulting in poor electrical coupling (e.g., an open circuit) between the first and second integrated circuit chips at the active bonding pad. However, good electrical coupling exists at the spare bonding pad between the first and second integrated circuit chips. Therefore, the devices of the first and second integrated circuit chips can be appropriately electrically coupled together, thereby improving the performance, reliability, and yield of the integrated circuit device.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figures 1A to 1C Various views of some embodiments of a stacked integrated circuit (IC) device having a bonding structure including multiple active bonding pads and multiple spare bonding pads are shown.

[0008] Figures 2A to 2C It shows Figures 1A to 1C Various top layout views of some other embodiments of the bonding structure of stacked IC devices.

[0009] Figures 3A to 3E Various cross-sectional views of some embodiments of a stacked IC device having a bonding structure including multiple active bonding pads and multiple spare bonding pads are shown.

[0010] Figures 4A to 4C Various top-view layout views of some embodiments of the bonding structure of stacked IC devices are shown.

[0011] Figure 5A and Figure 5B Various cross-sectional views of some embodiments of a stacked IC device having a bonding structure including multiple active bonding pads and multiple spare bonding pads are shown.

[0012] Figure 6 Cross-sectional views of some embodiments of a stacked integrated circuit (IC) device having a bonding structure including multiple active bonding pads and multiple spare bonding pads are shown.

[0013] Figure 7 It shows along Figure 6 The line A-A' intercepts Figure 6 Top view of some embodiments of a stacked IC device.

[0014] Figures 8 to 14Various cross-sectional views are shown of some embodiments of a method for forming a stacked IC device having a bonding structure including active bonding pads and spare bonding pads.

[0015] Figure 15 Methods for forming some embodiments of a stacked IC device having a bonding structure including active bonding pads and spare bonding pads are shown. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0017] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations illustrated in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein may be interpreted in the same manner. Unless otherwise explicitly stated, each component with the same reference numerals is assumed to have the same material composition and thickness within the same thickness range.

[0018] A stacked integrated circuit (IC) device may include a first IC chip and a second IC chip stacked perpendicularly to each other. The first IC chip includes a first substrate, a first interconnect structure on the first substrate, and a first bonding structure on the first interconnect structure. The first IC chip houses a first circuit disposed on the first substrate. The second IC chip includes a second substrate, a second interconnect structure on the second substrate, and a second bonding structure on the second interconnect structure. The second IC chip houses a second circuit disposed on the second substrate. The first bonding structure and the second bonding structure intersect each other at a bonding interface and facilitate electrical coupling between the first circuit and the second circuit.

[0019] The first bonding structure includes a plurality of conductive bonding pads disposed within a dielectric bonding structure. The plurality of conductive bonding pads includes a plurality of active bonding pads and a plurality of spare bonding pads. The active bonding pads are configured to facilitate electrical coupling between devices (e.g., transistors, pixels, etc.) of the first and second circuits. The spare bonding pads are electrically coupled to corresponding active bonding pads via a first interconnect structure. Thus, the active bonding pads provide a first electrical connection between the first and second IC chips, and the spare bonding pads provide a second electrical connection between the first and second IC chips, wherein the second electrical connection repeats or replicates the first electrical connection. Therefore, the stacked IC devices have dual-connection electrical coupling between the first and second IC chips at the bonding interface, wherein each electrical path between devices of the first and second circuits includes at least two connections at the bonding interface (e.g., an active bonding pad provides one connection and a spare bonding pad provides a second connection). The spare bonding pads are directly and laterally adjacent to the active bonding pads, such that the lateral distance between the spare bonding pads and the active bonding pads is relatively small (e.g., less than the spacing of the plurality of conductive bonding pads).

[0020] During the manufacturing process of a stacked IC device, a first IC chip is bonded to a second IC chip. However, limitations of the processing equipment, surface irregularities, depressions, corrosion, etc., of the first and second bonding structures can lead to voids and / or bubbles between the first and second IC chips. This can result in one or more bonding defect areas between the first and second IC chips. These bonding defect areas may include unbonded areas and / or open-circuit areas between the first and second IC chips. These bonding defect areas can lead to poor electrical coupling (e.g., open circuits) at one or more active bonding pads between the first and second IC chips. Corresponding spare bonding pads electrically coupled to one or more active bonding pads are configured to provide additional electrical paths between the first and second IC chips. However, a relatively small distance between the one or more active bonding pads and their corresponding spare bonding pads can cause the bonding defect area to extend to the corresponding spare bonding pad, resulting in poor electrical coupling (e.g., open circuits) at the corresponding spare bonding pad as well. Therefore, the devices of the first and second circuits are not properly electrically coupled together, which reduces the performance of the stacked IC device, reduces the yield of the stacked IC device, and / or causes the stacked IC device to fail wafer acceptance testing (WAT).

[0021] Therefore, various embodiments of this application relate to a stacked IC device with a bonding structure comprising a plurality of active bonding pads and a plurality of spare bonding pads configured to improve electrical connectivity and increase reliability in the stacked IC device. The stacked IC device includes a first IC chip stacked with a second IC chip. The first IC device includes a first substrate and a first bonding structure on the first substrate. The first bonding structure is disposed on a second bonding structure of the second IC chip. The first bonding structure includes a plurality of active bonding pads and a plurality of spare bonding pads disposed in a dielectric bonding structure. The active bonding pads facilitate electrical coupling between the devices of the first and second IC chips. The spare bonding pads are electrically coupled to corresponding active bonding pads via a first interconnect structure of the first IC chip. The spare bonding pads are laterally offset from their corresponding active bonding pads by a large lateral distance (e.g., a lateral distance greater than or equal to twice the spacing between the active and spare bonding pads). Bond defect regions may be aligned with the active bonding pads, resulting in poor electrical coupling (e.g., open circuits) between the first and second IC chips at the active bonding pads. However, the relatively large lateral distance between the active and spare bonding pads can be greater than the length or width of the bonding defect region, resulting in good electrical coupling (e.g., ohmic contact) at the spare bonding pad between the first and second IC chips. Therefore, the devices of the first and second IC chips can be appropriately electrically coupled together, thereby improving the performance, reliability, and yield of the stacked IC devices.

[0022] Figure 1A A cross-sectional view 100a is shown of some embodiments of a stacked integrated circuit (IC) device having a bonding structure including active bonding pads and spare bonding pads.

[0023] The stacked IC device includes a first IC chip 102 having a first bonding structure 114 and a second IC chip 104 having a second bonding structure 116. The first bonding structure 114 and the second bonding structure 116 intersect at a bonding interface 105. The first IC chip 102 also includes a first substrate 106, a first interconnect structure 110 between the first substrate 106 and the first bonding structure 114, and a first circuit 118 disposed on the first substrate 106. In some embodiments, the first circuit 118 includes a transistor, a photodetector, a capacitor, other semiconductor devices, or any combination thereof. The second IC chip 104 also includes a second substrate 108, a second interconnect structure 112 between the second substrate 108 and the second bonding structure 116, and a second circuit 120 disposed on the second substrate 108. In some embodiments, the second circuit 120 includes a transistor, a capacitor, a resistor, a memory device, other semiconductor devices, or any combination thereof.

[0024] The first interconnect structure 110 and the second interconnect structure 112 each include a conductive interconnect 122 (e.g., a conductive metal wire, a via, a conductive contact, etc.). In some embodiments, the conductive interconnect 122 is in... Figure 1A The data is shown as lines. The stacked IC device includes a device region 101 and a peripheral region 103. In some embodiments, the peripheral region 103 laterally surrounds the outer periphery of the device region 101. Devices of a first circuit 118 and a second circuit 120 (not shown) are disposed in the device region 101. The devices of the first circuit 118 and the second circuit 120 are electrically coupled to each other via a first bonding structure 114 and a second bonding structure 116, and a first interconnect structure 110 and a second interconnect structure 112.

[0025] The first bonding structure 114 and the second bonding structure 116 each include a dielectric bonding structure 124 and a plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) disposed in the dielectric bonding structure 124. In various embodiments, the plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) are arranged in multiple rows and columns including a spacing P (e.g., ...). Figure 1B The array is shown. In some embodiments, the spacing P is defined as the distance between the first edge of an individual conductive bonding pad in the plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) and the corresponding second edge of an adjacent conductive bonding pad in the plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) (e.g., the spacing between the left edges of the conductive bonding pads or between the right edges of the conductive bonding pads).

[0026] The plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) includes a plurality of dummy bonding pads 126, a plurality of active bonding pads (128a, 128b), and a plurality of spare bonding pads (130a, 130b). The dummy bonding pads 126 are disposed in device region 101 and in peripheral region 103. The dummy bonding pads 126 are configured to enhance the bonding strength between the first IC chip 102 and the second IC chip 104. In various embodiments, the dummy bonding pads 126 are electrically isolated from the conductive interconnects 122 of the first interconnect structure 110 and the second interconnect structure 112. Active bonding pads (128a, 128b) are configured to electrically couple the first IC chip 102 to the second IC chip 104, such that the active bonding pads (128a, 128b) of the first bonding structure 114 and the second bonding structure 116 provide a first electrical connection between the bonding interface 105 of the first IC chip 102 and the second IC chip 104. For example, the active bonding pads (128a, 128b) electrically couple a device of the first circuit 118 to a corresponding device of the second circuit 120. Spare bonding pads (130a, 130b) are configured to provide a second electrical connection at the bonding interface 105 between the first IC chip 102 and the second IC chip 104.

[0027] The plurality of active bonding pads (128a, 128b) in the first bonding structure 114 and the second bonding structure 116 are electrically coupled to corresponding spare bonding pads (130a, 130b) via conductive interconnects 122 of the first interconnect structure 110 and the second interconnect structure 112. In various embodiments, the second electrical connection of the spare bonding pads (130a, 130b) repeats the electrical wiring of the active bonding pads (128a, 128b) at the bonding interface 105 between the first IC chip 102 and the second IC chip 104. For example, the first active bonding pad 128a of the first bonding structure 114 is directly electrically coupled to the first spare bonding pad 130a of the first bonding structure 114 via a first conductive path 140 in the first interconnect structure 110. Furthermore, the second active bonding pad 128b of the first bonding structure 114 is directly electrically coupled to the second spare bonding pad 130b of the first bonding structure 114 via a second conductive path 142 in the first interconnect structure 110. Therefore, the spare bonding pads (130a, 130b) are configured to provide a second electrical connection at the bonding interface 105 between the first IC chip 102 and the second IC chip 104 at a location laterally offset from the active bonding pads (128a, 128b).

[0028] In various embodiments, the spare bonding pads (130a, 130b) are laterally offset from their corresponding active bonding pads among the plurality of active bonding pads (128a, 128b) by a relatively large lateral distance (e.g., a lateral distance greater than the spacing P). For example, the first active bonding pad 128a is laterally offset from the first spare bonding pad 130a by a lateral distance 132. In some embodiments, the lateral distance 132 is greater than the spacing P, greater than twice the width of an individual bonding pad among the plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b), or greater than or equal to twice the spacing P. During the manufacture of the stacked IC device, bonding defect areas (e.g., unbonded areas) may be formed in the region between the first IC chip 102 and the second IC chip 104 aligned with one or more active bonding pads (128a, 128b) or one or more spare bonding pads (130a, 130b). A bonding defect region can cause an open circuit between the first IC chip 102 and the second IC chip 104, potentially disrupting the electrical connection between the devices of the first circuit 118 and the second circuit 120. The relatively large lateral distance between the active bonding pads (128a, 128b) and the spare bonding pads (130a, 130b) prevents or mitigates the chance of a bonding defect region affecting both the active bonding pads (128a, 128b) and the spare bonding pads (130a, 130b). Therefore, although an open circuit may exist at one or more active bonding pads (128a, 128b), the corresponding spare bonding pads (130a, 130b) can maintain good electrical coupling (e.g., ohmic contact) between the first IC chip 102 and the second IC chip 104. Thus, the devices of the first circuit 118 and the second circuit 120 are properly electrically coupled together, thereby increasing the efficiency and yield of the stacked IC devices.

[0029] Figure 1B It shows along Figure 1A The line A-A' in the middle intercepts Figure 1A Top layout view 100b of some embodiments of the stacked IC device. Figure 1A The sectional view 100a may be, for example, along... Figure 1B Cut off line A-A' in the middle.

[0030] As shown in the top layout view 100b, in some embodiments, the plurality of active bonding pads (128a, 128b) and the plurality of spare bonding pads (130a, 130b) are each arranged in an array comprising multiple rows and columns. The plurality of active bonding pads (128a, 128b) includes a plurality of first active bonding pads 128a and a plurality of second active bonding pads 128b. The first active bonding pads 128a are arranged in a first column of the plurality of active bonding pads (128a, 128b), and the second active bonding pads 128b are arranged in a second column of the plurality of active bonding pads (128a, 128b). Similarly, the plurality of spare bonding pads (130a, 130b) includes a plurality of first spare bonding pads 130a arranged in a first column and a plurality of second spare bonding pads 130b arranged in a second column. Each active bonding pad (128a, 128b) is electrically coupled to a corresponding spare bonding pad (130a, 130b). For example, each of the plurality of first active bonding pads 128a is electrically coupled to a corresponding spare bonding pad in the plurality of first spare bonding pads 130a, and each of the plurality of second active bonding pads 128b is electrically coupled to a corresponding spare bonding pad in the plurality of second spare bonding pads 130b. The electrical coupling between the active bonding pads (128a, 128b) and the spare bonding pads (130a, 130b) is shown by lines extending between the active bonding pads (128a, 128b) and the spare bonding pads (130a, 130b). The electrical coupling between each of the active bonding pads (128a, 128b) and the spare bonding pads (130a, 130b) is performed on the first IC chip (…). Figure 1A The first internal interconnect structure of 102) Figure 1A Implemented in 110). In some embodiments, the spare bonding pads (130a, 130b) may be referred to as auxiliary bonding pads, secondary active bonding pads, or redundant active bonding pads.

[0031] In various embodiments, in the first IC chip ( Figure 1A 102) and the second IC chip ( Figure 1A There is a bonding defect region 136 between the first chip (104). The bonding defect region may be, for example, an unbonded region, which is located between the first chip (104) and the bonding defect region 136. Figure 1A 102) and the second IC chip ( Figure 1A The areas between 104) that are not bonded or will not bond together during the bonding process. Furthermore, bonding defect areas can be areas where the first bonding structure 114 and / or the second bonding structure (104) of the stacked IC chips are not bonded or will not bond together. Figure 1A The conductive bonding pads in (116) suffer from corrosion, have increased pitting, etc., and in the first chip ( Figure 1A 102) and the second IC chip ( Figure 1A There are poor electrical connections or no electrical connections (e.g., open circuits) between the conductive bonding pads of (104). Therefore, in the bonding defect region 136, the first chip ( Figure 1A 102) and the second IC chip ( Figure 1A There is a poor or non-existent electrical connection (e.g., an open circuit) between the conductive bonding pads in bonding defect region 136. For example, in bonding defect region 136, the first and second bonding structures ( Figure 1A The active bonding pads (128a, 128b) of 114, 116 have poor electrical connection or no electrical connection (e.g., open circuit) with each other in the bonding defect area 136. However, due to the relatively large lateral distance between the active bonding pads (128a, 128b) and the corresponding spare bonding pads (130a, 130b), the poor electrical connection or no electrical connection in the bonding defect area 136 does not disrupt the first circuit. Figure 1A 118) and the second circuit ( Figure 1A The electrical connection between 120) is due to the spare bonding pads (130a, 130b) in the region 144 offset laterally from the bonding defect region 136, in the first chip ( Figure 1A 102) and the second IC chip ( Figure 1A There is a good electrical connection (e.g., ohmic contact) between 104 and the junction. Therefore, although the first circuit in the junction defect region 136 ( Figure 1A 118) and the second circuit ( Figure 1A The first electrical connection between 120) is disrupted / inoperable due to the bonding defect area 136, and the first circuit is provided by the spare bonding pads (130a, 130b) in area 144. Figure 1A 118) and the second circuit ( Figure 1A The second electrical connection between (120) is beneficial to the first circuit ( Figure 1A 118) and the second circuit ( Figure 1A The devices of 120) are properly coupled together. Therefore, the spare bonding pads (130a, 130b) are in the first circuit ( Figure 1A 118) and the second circuit ( Figure 1A The interface between 120) Figure 1A Additional or redundant electrical connections are provided at 105, which increases the reliability, efficiency and yield of stacked IC devices.

[0032] In some embodiments, the spacing P is in the range of about 0.5 to 5 μm, 5 to 10 μm, 0.5 to 10 μm, greater than about 0.5 μm, less than about 10 μm, or some other suitable value. The active bonding pads (128a, 128b) are laterally offset from their corresponding spare bonding pads (130a, 130b) by a lateral distance 132. In various embodiments, the lateral distance 132 is equal to or greater than twice the spacing P (e.g., equal to or greater than P*2), greater than 10 μm, greater than 30 μm, in the range of 10 to 80 μm, or some other suitable value. A lateral distance 132 equal to or greater than at least twice the spacing P mitigates the bonding defect area 136 of poor electrical connection (e.g., open circuit) at both the active bonding pads (128a, 128b) and the corresponding spare bonding pads (130a, 130b).

[0033] Figure 1C It shows along Figure 1B A cross-sectional view 100c of some other embodiments of a stacked IC device, taken by line B-B'.

[0034] In some embodiments, an aperture 146 is present in a bonding defect region 136 between a first IC chip 102 and a second IC chip 104. The aperture 146 can cause an open circuit between at least a portion of the active bonding pads (128a, 128b) of the first IC chip 102 and the second IC chip 104 in the bonding defect region 136. In various embodiments, the spare bonding pads (130a, 130b) of the first IC chip 102 and the second IC chip 104 in region 144 of the bonding defect region 136, which are laterally offset, have good electrical connections (e.g., ohmic contacts) and facilitate proper electrical coupling between the first circuit 118 and the second circuit 120. Therefore, the relatively large lateral distance 132 between the spare bonding pads (130a, 130b) and the active bonding pads (128a, 128b) increases the efficiency and yield of the stacked IC device.

[0035] Figure 2A A top layout view 200a illustrates some embodiments of the bonding structure of a stacked IC device. In some embodiments, top layout view 200a shows... Figure 1A The layout of the first joining structure 114.

[0036] In some embodiments, the first bonding structure 114 includes a plurality of dummy bonding pads 126 arranged in an array, a plurality of active bonding pads (128a, 128b, 128c, 128d, 128e, 128f, 128g, 128h, 128i, hereinafter referred to as 128a-128i), and a plurality of spare bonding pads (130a, 130b, 130c, 130d, 130e, 130f, 130g, 130h, 130i, hereinafter referred to as 130a-130i). The active bonding pads (128a-128i) are directly electrically coupled to a corresponding spare bonding pad among the plurality of spare bonding pads (130a-130i), as shown in conductive path 202. It should be understood that, for ease of illustration, only some of the conductive paths 202 between the active bonding pads (128a-128i) and the spare bonding pads (130a-130i) are labeled and / or shown. The plurality of active bonding pads (128a-128i) are arranged in multiple columns and rows (204a, 204b, 204c, 204d, 204e, hereinafter referred to as 204a-204e). The plurality of spare bonding pads (130a-130i) are arranged in multiple columns and rows (206a, 206b, 206c, 206d, 206e, hereinafter referred to as 206a-206e). Individual active bonding pads in the multiple rows (204a-204e) are directly electrically coupled to individual spare bonding pads in the corresponding columns of the multiple rows (206a-206e). For example, the first active bonding pad 208 of the plurality of active bonding pads (128a-128i) is directly electrically coupled to the first spare bonding pad 212 of the plurality of spare bonding pads (130a-130i), the second active bonding pad 210 of the plurality of active bonding pads (128a-128i) is directly electrically coupled to the second spare bonding pad 214 of the plurality of spare bonding pads (130a-130i), and so on.

[0037] In some embodiments, one or more of the dummy bonding pads 126 are arranged between the active bonding pads (128a-128i) and the spare bonding pads (130a-130i). Therefore, the lateral distance 132 between the directly coupled active and spare bonding pads is greater than the column length 216 of the array of active bonding pads (128a-128i). This partially mitigates problems (e.g., poor electrical coupling) arising from bonding defect regions 136 aligned with at least a portion of the array of active bonding pads (128a-128i) and increases the yield and performance of the stacked IC device. Furthermore, it should be understood that while the plurality of active bonding pads (128a-128i) and the plurality of spare bonding pads (130a-130i) are each shown as having five rows and nine columns, any number of columns and rows is within the scope of this disclosure, provided that at least one row or column exists. In some embodiments, the spare bonding pads (130a-130i) may be referred to as auxiliary bonding pads, secondary active bonding pads, or redundant active bonding pads.

[0038] Figure 2B A top layout view 200b illustrates some embodiments of the bonding structure of a stacked IC device having an active bonding pad, a spare bonding pad, and an external spare bonding pad. In some embodiments, top layout view 200b shows... Figure 1A The layout of the first joining structure 114.

[0039] In some embodiments, the first bonding structure 114 includes a plurality of conductive bonding pads (126, 128a-128i, 130a-130i, 222a-222i), comprising a plurality of dummy bonding pads 126, a plurality of active bonding pads (128a-128i), a plurality of spare bonding pads (130a-130i), and a plurality of external spare bonding pads (222a, 222b, 222c, 222d, 222e, 222f, 222g, 222h, 222i, hereinafter referred to as 222a-222i). In various embodiments, the active bonding pads (128a-128i) are directly electrically coupled to corresponding spare bonding pads among the plurality of spare bonding pads (130a-130i) and corresponding external spare bonding pads among the plurality of external spare bonding pads (222a-222i), as shown in conductive path 202. The conductive path 202 between each active bonding pad (128a-128i) and its corresponding spare bonding pad and its corresponding external spare bonding pad is in the first IC chip ( Figure 1A The first internal interconnect structure of 102) Figure 1A Implemented in 110). In some embodiments, the external spare bonding pads (222a-222i) may be referred to as external auxiliary bonding pads, external secondary active bonding pads, or external redundant active bonding pads.

[0040] The active bonding pads (128a-128i) are spaced apart from the spare bonding pads (130a-130i) by a first distance 218. Furthermore, the active bonding pads (128a-128i) are spaced apart from the external spare bonding pads (222a-222i) by a second distance 220 greater than the first distance 218. In some embodiments, the first distance 218 is smaller than the spacing P of the plurality of conductive bonding pads (126, 128a-128i, 130a-130i, 222a-222i). In other embodiments, the first distance 218 is less than about 5 μm or some other suitable value. In various embodiments, a first distance 218 less than about 5 μm and / or less than the spacing P can reduce the complexity and / or number of conductive interconnects used to facilitate direct coupling between the active bonding pads (128a-128i) and the corresponding spare bonding pads (130a-130i). This can reduce manufacturing costs and / or alleviate the burden on the first IC chip ( Figure 1A The first internal interconnect structure of 102) Figure 1A The parasitic capacitance in (110).

[0041] In some embodiments, the second distance 220 is at least three times larger than the pitch P. In other embodiments, the second distance 220 is greater than 30 μm or some other suitable value. In various embodiments, the second distance 220, greater than 30 μm and / or at least three times larger than the pitch P, provides a first chip ( Figure 1A 102) and the second IC chip ( Figure 1A The external electrical connection between 104 and the active bonding pad (128d-128g) and the spare bonding pad (130d-130g) in the bonding defect region 136. Figure 1A 102) and the second IC chip ( Figure 1A Poor electrical connections (e.g., open circuits) between the 104 and the stacked IC devices will not adversely affect the performance of the stacked IC devices. This is because the external spare bonding pads (222a-222i) provide a connection to the first chip ( Figure 1A 102) and the second IC chip ( Figure 1A External electrical connections between (104) are beneficial to the first chip ( Figure 1A 102) and the second IC chip ( Figure 1AThe devices of 104) are properly coupled together. In another embodiment, if the external spare bonding pads (222a-222i) are omitted when the first distance 218 is relatively small (e.g., less than the pitch P and / or less than 5 μm), then poor electrical connections (e.g., open circuits) at the active bonding pads (128d-128g) and spare bonding pads (130d-130g) in the bonding defect region 136 may cause the stacked IC device to malfunction and / or fail to load. Therefore, the spare bonding pads (130a-130i) at the first chip ( Figure 1A 102) and the second IC chip ( Figure 1A A first spare or redundant electrical connection is provided between 104 and the external spare bonding pads (222a-222i) on the first chip ( Figure 1A 102) and the second IC chip ( Figure 1A A second backup or redundant electrical connection is provided between the 104 and the stacked IC device, thereby further improving the overall performance and yield of the stacked IC device.

[0042] Figure 2C It shows Figure 2B Top layout view 200c of some other embodiments of the joining structure. In some embodiments, top layout view 200c shows Figure 1A The layout of the first joining structure 114.

[0043] In some embodiments, the plurality of active bonding pads (128a-128i), the plurality of spare bonding pads (130a-130i), and the plurality of external spare bonding pads (222a-222i) are arranged in an array comprising multiple rows and columns. The active bonding pads (128a-128i) are directly and electrically coupled to corresponding spare bonding pads among the plurality of spare bonding pads (130a-130i) and corresponding external spare bonding pads among the plurality of external spare bonding pads (222a-222i), as shown in conductive path 202. It should be understood that, for ease of illustration, only some of the conductive paths 202 between the active bonding pads (128a-128i) and the spare bonding pads (130a-130i) are labeled and / or shown. In various embodiments, at least five rows of the dummy bonding pads 126 are arranged between the plurality of spare bonding pads (130a-130i) and the plurality of external spare bonding pads (222a-222i). It should be understood that any number of columns of the dummy bonding pads 126 may be arranged between the plurality of spare bonding pads (130a-130i) and the plurality of external spare bonding pads (222a-222i). In another embodiment, a first number of rows of the dummy bonding pads 126 between the plurality of active bonding pads (128a-128i) and the plurality of spare bonding pads (130a-130i) is less than a first number of rows of the dummy bonding pads 126 between the plurality of spare bonding pads (130a-130i) and the plurality of external spare bonding pads (222a-222i).

[0044] The active bonding pads (128a-128i) are laterally offset from their corresponding spare bonding pads (130a-130i) by a first distance 218. In some embodiments, the first distance 218 is equal to or greater than at least twice the spacing P of the bonding pads. In another embodiment, the first distance 218 is at least three times larger than the spacing P and / or larger than the column length 216 of the plurality of active bonding pads (128a-128i). This partially facilitates the spare bonding pads (130a-130i) in providing a first spare or repeated electrical connection at a location electrically connected to the active bonding pads (128a-128i) remotely. Furthermore, the active bonding pads (128a-128i) are laterally offset from their corresponding external spare bonding pads (222a-222i) by a second distance 220. The second distance 220 is greater than the first distance 218. In some embodiments, the second distance 220 is at least six times larger than the spacing P and / or at least twice larger than the column length 216 of the plurality of active bonding pads (128a-128i). Therefore, the plurality of external spare bonding pads (222a-222i) provide a second spare or repeated electrical connection at an external location relatively far from the first spare or repeated electrical connection of the spare bonding pads (130a-130i). Therefore, the spacing between the spare bonding pads (130a-130i) and the external spare bonding pads (222a-222i) and the active bonding pads (128a-128i), and the coupling between the active bonding pads (128a-128i) and the corresponding bonding pads in the spare bonding pads (130a-130i) and the external spare bonding pads (222a-222i), reduces the coupling caused by the first chip ( Figure 1A 102) and the second IC chip ( Figure 1A Problems caused by one or more joint defect areas 136 between 104).

[0045] In various embodiments, it should be understood that, although Figures 2A to 2C Various embodiments of the first joining structure 114 are shown, but Figure 1A The second bonding structure 116 of the second IC chip 104 can be as follows Figures 2A to 2C The second bonding structure 116 of the second IC chip 104 may be configured as shown and / or described. For example, the layout of the first bonding structure 114 and the second bonding structure 116 is symmetrical.

[0046] Figure 3A A cross-sectional view 300a of some embodiments of a stacked IC device having a bonding structure including active bonding pads and spare bonding pads is shown.

[0047] The stacked IC device includes a first IC chip 102 stacked with a second IC chip 104. The first IC chip 102 includes a first substrate 106, a first interconnect structure 110 on the first substrate 106, and a first bonding structure 114 on the first interconnect structure 110. The second IC chip 104 includes a second substrate 108, a second interconnect structure 112 on the second substrate 108, and a second bonding structure 116 on the second interconnect structure 112. The first substrate 106 and the second substrate 108 may, for example, be or include silicon, single-crystal silicon, a silicon wafer, a CMOS bulk material, silicon germanium, one or more epitaxial layers (e.g., epitaxial silicon layers), silicon-on-insulator (SOI) substrates, or some other type of semiconductor substrate.

[0048] In some embodiments, the first IC chip 102 may be configured as a CMOS image chip, including a plurality of photodetectors 302, a first plurality of transistors 304, and a second plurality of transistors 306 disposed in a first substrate 106. It should be understood that only a single transistor of the second plurality of transistors 306 is shown, but the other transistors are arranged on the first substrate 106 in a device region 101 outside the view. The photodetectors 302 are configured to absorb incident light (e.g., photons) and generate a corresponding electrical signal corresponding to the incident light. For example, the photodetector 302 may generate electron-hole pairs from the incident light. The first plurality of transistors 304 may be configured as transmission transistors and configured to control the current between the photodetector 302 and a corresponding floating diffusion node 312 in the first substrate 106. In some embodiments, the first substrate 106 includes a first doping type (e.g., p-type), and the photodetector 302 includes a second doping type (e.g., n-type) opposite to the first doping type. In various embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. In various embodiments, the plurality of photodetectors 302, the first plurality of transistors 304, and the second plurality of transistors 306 are part of a first circuit 118 arranged on the first IC chip 102.

[0049] In various embodiments, photodetector 302 may be configured, for example, as a photodiode, a single-photon avalanche diode, or the like. In various embodiments, photodetector 302 is configured to sense visible light (e.g., wavelengths in the range of about 380 to 700 nanometers, near-infrared (NIR) wavelengths (e.g., wavelengths in the range of about 700 to 1400 nm), short-wave infrared (SWIR) wavelengths (e.g., wavelengths in the range of about 1 to 3 μm), or the like. Photodetector 302 may be part of a pixel sensor configured as a four-transistor CMOS active pixel sensor (APS) or some other suitable pixel configuration. In further embodiments, photodetector 302 may be used for depth sensing applications, such as indirect time-of-flight (iTof), direct time-of-flight (dTof), or the like.

[0050] In some embodiments, the second plurality of transistors 306 may be, for example, or include a reset transistor, a source follower transistor, a select transistor, other semiconductor devices, or any combination thereof. In various embodiments, the second plurality of transistors 306 cooperating with the first plurality of transistors 304 are configured to facilitate reading from the plurality of photodetectors 302 an electrical signal corresponding to incident light received at the photodetectors 302. The first plurality of transistors 304 and the second plurality of transistors 306 each include a gate dielectric layer 310 and a gate 308, wherein the gate dielectric layer 310 is disposed between the gate 308 and the first substrate 106. In various embodiments, the second plurality of transistors 306 includes a pair of source / drain regions disposed on opposite sides of the corresponding gate 308 in the first substrate 106. One or more source / drain regions may individually or collectively refer to a source or drain, depending on the context.

[0051] In some embodiments, the second IC chip 104 includes a second circuit 120, which includes a plurality of semiconductor devices 316 disposed on a second substrate 108. The second circuit 120 may be configured to or include an application-specific integrated circuit (ASIC), in-pixel circuitry, another suitable circuit, or any combination thereof. For example, the second circuit 120 may include one or more amplifiers, analog-to-digital converters (ADCs), digital signal processing (DSP) units, control logic units, power control units, registers, buffers, row and column drive units, other suitable circuitry, or any combination thereof. The plurality of semiconductor devices 316 may, for example, be configured as logic devices, transistors, other suitable electronic devices, or any combination thereof. In various embodiments, the plurality of semiconductor devices 316 includes a gate dielectric layer 320 on the second substrate 108, a gate 318 on the gate dielectric layer 320, and a pair of source / drain regions 322 on opposite sides of the gate 318.

[0052] In various embodiments, the first interconnect structure 110 and the second interconnect structure 112 each include a plurality of conductive interconnects (326, 328, 330) configured as an interconnect dielectric structure 324. The plurality of conductive interconnects (326, 328, 330) includes a plurality of conductive metal lines 326, a plurality of vias 328, and a plurality of conductive contacts 330. The interconnect dielectric structure 324 may include a plurality of dielectric layers stacked perpendicularly to each other, which may be, for example, each of which is or includes silicon dioxide, a low dielectric constant dielectric material, silicon nitride, silicon carbide, or some other dielectric material. The conductive metal lines 326, vias 328, and contacts 330 may be, for example, aluminum, copper, tungsten, ruthenium, titanium nitride, tantalum nitride, some other conductive materials, or any combination thereof. The first interconnect structure 110 and the second interconnect structure 112 are configured to facilitate electrical coupling between the devices of the first circuit 118 and the second circuit 120 and to each other, as well as to another electronic device (not shown).

[0053] The first IC chip 102 and the second IC chip 104 intersect at a bonding interface 105. The bonding interface 105 includes dielectric-to-dielectric bonding and conductor-to-conductor bonding. Furthermore, the first bonding structure 114 and the second bonding structure 116 each include a dielectric bonding structure 124 and a plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) disposed within the dielectric bonding structure 124. The plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) includes a plurality of dummy bonding pads 126, a plurality of active bonding pads (128a, 128b), and a plurality of spare bonding pads (130a, 130b). The dummy bonding pads 126 are configured to enhance the bonding strength between the first IC chip 102 and the second IC chip 104. In various embodiments, the dummy bonding pads 126 are electrically floating and electrically isolated from the conductive structures of the first interconnect structure 110 and the second interconnect structure 112. In some embodiments, the entire top surface of each of the dummy bonding pads 126 in the first bonding structure 114 is in direct contact with the lower surface of the interconnect dielectric structure 324 of the first interconnect structure 110. In another embodiment, the entire bottom surface of each of the dummy bonding pads 126 in the second bonding structure 116 is in direct contact with the upper surface of the interconnect dielectric structure 324 of the second interconnect structure 112.

[0054] Active bonding pads (128a, 128b) are configured to electrically couple a device of the first circuit 118 to a device of the second circuit 120, such that the active bonding pads (128a, 128b) provide a first electrical connection at a bonding interface 105 between the first IC chip 102 and the second IC chip 104. Spare bonding pads (130a, 130b) are directly electrically coupled to a corresponding active bonding pad among the plurality of active bonding pads (128a, 128b). Spare bonding pads (130a, 130b) are configured to provide a second electrical connection in a region laterally offset by a lateral distance 132 from the first electrical connection and at the bonding interface 105 between the first IC chip 102 and the second IC chip 104. For example, the first active bonding pad 128a is directly electrically coupled to the first spare bonding pad 130a via a first conductive metal line 328a of the first interconnect structure 110. The first interconnect structure 110 includes conductive paths 140 to individual transistors among the first plurality of transistors 304.

[0055] In various embodiments, the lateral distance 132 is at least twice as large as the spacing P of the plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b). If a poor electrical connection (e.g., an open circuit) exists at any of the active bonding pads (128a, 128b) between the first IC chip 102 and the second IC chip 104, the second electrical connection of the spare bonding pads (130a, 130b) provides an alternative or repeatable electrical connection between the first IC chip 102 and the second IC chip 104, which facilitates proper electrical coupling of the first circuit 118 and the second circuit 120. Poor electrical connections may be caused by bonding defect areas between the first IC chip 102 and the second IC chip 104. Because the lateral distance 132 is relatively large (e.g., at least twice as large as the spacing P), bonding defect areas affecting the active bonding pads (128a, 128b) may not affect the spare bonding pads (130a, 130b), and vice versa. For example, in some instances, a bonding defect region (not shown) may be aligned with the first active bonding pad 128a, where the bonding defect region causes poor electrical coupling (e.g., an open circuit) between the first active bonding pad 128a of the first IC chip 102 and the second IC chip 104. The bonding defect region may result in a void between the first IC chip 102 and the second IC chip 104 due to corrosion of the first active bonding pad 128a, problems during the bonding process, etc. However, poor electrical coupling at the first active bonding pad 128a does not adversely affect the performance of the stacked IC device because the first spare bonding pad 130a provides good electrical coupling (e.g., an ohmic contact) with the second IC chip 104, thus maintaining a conductive path between individual devices of the first circuit 118 and individual devices of the second circuit 120.

[0056] Furthermore, it should be understood that if poor electrical coupling exists between the first IC chip 102 and the second IC chip 104 at the spare bonding pads (130a, 130b), the active bonding pads (128a, 128b) can provide proper electrical coupling between the first IC chip 102 and the second IC chip 104. Therefore, the stacked IC device includes repeatable or spare electrical connections between the devices of the first circuit 118 and the second circuit 120 at the bonding interface 105, which are laterally offset from each other by a relatively large lateral distance, thereby mitigating problems caused by one or more bonding defect areas and increasing the efficiency and yield of the stacked IC device.

[0057] In various embodiments, the stacked IC device can be used, for example, in safety applications requiring high reliability, such as automotive sensors, autonomous driving applications, advanced driver-assistance systems (ADAS), or the like. In this case, the stacked IC device, having dual connections at the bonding interface 105 due to the spare bonding pads (130a, 130b), mitigates the possibility of failures during operation of the stacked IC device. Therefore, the backup or repeatable electrical connections provided by the spare bonding pads (130a, 130b) further increase the reliability and performance of the stacked IC device, where failures during operation could cause harm to the user.

[0058] Figure 3B It shows Figure 3A Cross-sectional view 300b of some other embodiments of the stacked IC device.

[0059] In some embodiments, the first bonding structure 114 and the second bonding structure 116 respectively include a plurality of conductive bonding contacts 332 disposed on active bonding pads (128a, 128b) and spare bonding pads (130a, 130b). The conductive bonding contacts 332 are disposed in the dielectric bonding structure 124 and configured to electrically couple the active bonding pads (128a, 128b) and spare bonding pads (130a, 130b) to conductive interconnects in the first interconnect structure 110 and the second interconnect structure 112. For example, the conductive bonding contacts 332 of the first bonding structure 114 are electrically coupled to the conductive metal wire 326 of the first interconnect structure 110, and the conductive bonding contacts 332 of the second bonding structure 116 are electrically coupled to the conductive metal wire of the second interconnect structure 112. In various embodiments, the dielectric bonding structure 124 of the first bonding structure 114 extends continuously along the entire top surface of each of the dummy bonding pads 126 of the first bonding structure 114 and directly contacts the entire top surface of each of the dummy bonding pads 126 of the first bonding structure 114. In another embodiment, the dielectric bonding structure 124 of the second bonding structure 116 extends continuously along the entire bottom surface of each of the dummy bonding pads 126 of the second bonding structure 116. The conductive bonding contact 332 may be, for example, or include copper, aluminum, nickel, titanium, tantalum, nitrides (e.g., titanium nitride, tantalum nitride, etc.), some other conductive materials, or any combination thereof.

[0060] In various embodiments, when the output of the first circuit 118 is pixel-level coupled to the input of the second circuit 120, the first bonding structure 114 and the second bonding structure 116 include conductive bonding contacts 332. For example, the semiconductor device 316 of the second circuit 120 may include, for instance, a reset transistor, a source follower transistor, a select transistor, or the like. In various embodiments, one or more semiconductor devices 316 in the second circuit 120 may, for example, be directly coupled to a floating diffusion node 312 on the first substrate 106.

[0061] Figure 3C It shows Figure 3A A cross-sectional view 300c of some other embodiments of the stacked IC device.

[0062] In some embodiments, the plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) of the first bonding structure 114 and the second bonding structure 116 are each trapezoidal in shape. In some embodiments, the width of the conductive bonding pads (126, 128a, 128b, 130a, 130b) of the first bonding structure 114 decreases continuously from the bottom surface of the first bonding structure 114 toward the first substrate 106 along a first direction. In another embodiment, the width of the conductive bonding pads (126, 128a, 128b, 130a, 130b) of the second bonding structure 116 decreases continuously from the top surface of the second bonding structure 116 toward the second substrate 108 along a second direction.

[0063] Figure 3D It shows Figure 3A A cross-sectional view 300d of some other embodiments of the stacked IC device.

[0064] In some embodiments, the plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) of the first bonding structure 114 and the second bonding structure 116 are each trapezoidal in shape. In some embodiments, the width of the conductive bonding pads (126, 128a, 128b, 130a, 130b) of the first bonding structure 114 increases continuously from the bottom surface of the first bonding structure 114 toward the first substrate 106 along a first direction. In another embodiment, the width of the conductive bonding pads (126, 128a, 128b, 130a, 130b) of the second bonding structure 116 increases continuously from the top surface of the second bonding structure 116 toward the second substrate 108 along a second direction.

[0065] Figure 3E It shows Figure 3A A cross-sectional view 300e of some other embodiments of the stacked IC device.

[0066] In some embodiments, the centers of the conductive bonding pads (126, 128a, 128b, 130a, 130b) of the first bonding structure 114 are respectively offset laterally by a lateral distance 334 from the center of the corresponding conductive bonding pad in the conductive bonding pads (126, 128a, 128b, 130a, 130b) of the second bonding structure 116. The lateral distance 334 is not zero. In various embodiments, the lateral distance 334 is less than the spacing P or less than the width of an individual conductive bonding pad in the plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b). The lateral offset between the conductive bonding pads (126, 128a, 128b, 130a, 130b) of the first bonding structure 114 and the second bonding structure 116 may be caused, for example, by misalignment during the bonding process performed on the first IC chip 102 and the second IC chip 104.

[0067] Figure 4A A top layout view 400a illustrates some embodiments of the bonding structure of a stacked IC device. In some embodiments, top layout view 400a shows... Figure 1A or Figures 3A to 3E The layout of the first joining structure 114.

[0068] The stacked IC device includes a device region 101 and a peripheral region 103 disposed around the outer periphery of the device region 101. The peripheral region 103 includes a first side 401a, a second side 401b, a third side 401c, and a fourth side 401d. In some embodiments, a protective ring 402 is disposed in the peripheral region 103 and defines the peripheral region 103. In some embodiments, the protective ring 402 includes a conductive material (e.g., copper, aluminum, titanium, etc.) and is configured to mitigate or prevent damage to the conductive bonding pads (126, 128a-128d, 130a-130d) of the first bonding structure 114 during a dicing process. In yet another embodiment, the first interconnect structure ( Figure 1A 110) includes a sealing ring structure (not shown) that includes a plurality of through holes and lines aligned with the protective ring 402.

[0069] The conductive bonding pads (126, 128a-128d, 130a-130d) include the plurality of dummy bonding pads 126, the plurality of active bonding pads (128a-128d), and the plurality of spare bonding pads (130a-130d). The plurality of dummy bonding pads 126 are arranged in an array comprising a plurality of rows and columns in the device area 101. The plurality of active bonding pads (128a-128d) include a plurality of first active bonding pads 128a, a plurality of second active bonding pads 128b, a plurality of third active bonding pads 128c, and a plurality of fourth active bonding pads 128d. The plurality of spare bonding pads (130a-130d) include a plurality of first spare bonding pads 130a, a plurality of second spare bonding pads 130b, a plurality of third spare bonding pads 130c, and a plurality of fourth spare bonding pads 130d. The active bonding pads (128a-128d) are directly electrically coupled to the corresponding spare bonding pads (130a-130d) in the plurality of first spare bonding pads, as shown in conductive path 202. It should be understood that, for ease of illustration, only some of the conductive paths 202 are labeled and / or shown.

[0070] In various embodiments, individual active bonding pads among the plurality of first active bonding pads 128a are directly electrically coupled to corresponding individual spare bonding pads among the plurality of first spare bonding pads 130a, and individual active bonding pads among the plurality of second active bonding pads 128b are directly electrically coupled to corresponding individual spare bonding pads among the plurality of second spare bonding pads 130b, and so on. For example, a first active bonding pad 404 among the plurality of first active bonding pads 128a is directly electrically coupled to a first spare bonding pad 408 among the plurality of first spare bonding pads 130a, a second active bonding pad 406 among the plurality of first active bonding pads 128a is directly electrically coupled to a second spare bonding pad 410 among the plurality of first spare bonding pads 130a, and so on. The plurality of first active bonding pads 128a and second active bonding pads 128b, as well as the plurality of first spare bonding pads 130a and second spare bonding pads 130b, are arranged on a first side 401a of the peripheral region 103.

[0071] The plurality of third active bonding pads 128c and fourth active bonding pads 128d, and the plurality of third spare bonding pads 130c and fourth spare bonding pads 130d are arranged on the second side 401b of the peripheral region 103. A first active bonding pad 412 in the plurality of third active bonding pads 128c is directly electrically coupled to a first spare bonding pad 416 in the plurality of third spare bonding pads 130c, and a first active bonding pad 414 in the plurality of fourth active bonding pads 128d is directly electrically coupled to a first spare bonding pad 418 in the plurality of fourth spare bonding pads 130d, and so on. In various embodiments, a bonding defect region 136 is arranged on the right-hand side of the plurality of third spare bonding pads 130c and fourth spare bonding pads 130d, such that in the first chip ( Figure 1A 102) and the second IC chip ( Figure 1A A poor electrical connection (e.g., an open circuit) exists at the bonding defect region 136 between the 104 and the bonding defect region. However, the corresponding active bonding pads of the plurality of third active bonding pads 128c and fourth active bonding pads 128d arranged on the right-hand side are sufficiently laterally offset from the plurality of third spare bonding pads 130c and fourth spare bonding pads 130d, such that in the first chip ( Figure 1A 102) and the second IC chip ( Figure 1A The poor electrical connection at the junction defect area 136 between 104) will not adversely affect the performance of the stacked IC device.

[0072] Figure 4B It shows Figure 4A Top layout view 400b of some other embodiments of the stacked IC device.

[0073] In some embodiments, the plurality of first and second active bonding pads (128a-128d) are arranged on a first side 401a of the peripheral region 103, and the plurality of first and second spare bonding pads (130a-130d) are arranged on a third side 401c of the peripheral region 103. In various embodiments, the lateral distance between individual active bonding pads of the first active bonding pad 128a and the second active bonding pad 128b that are directly coupled to corresponding individual spare bonding pads of the first spare bonding pad 130a and the second spare bonding pad 130b is greater than the length 420 of the device region 101. The plurality of third active bonding pads 128c and fourth active bonding pads 128d are arranged on a second side 401b of the peripheral region 103, and the plurality of third spare bonding pads 130c and fourth spare bonding pads 130d are arranged on a fourth side 401d of the peripheral region 103. In various embodiments, the lateral distance between the individual active pads of the third active pad 128c and the fourth active pad 128d, which are directly coupled to the corresponding individual spare pads in the third spare pad 130c and the fourth spare pad 130d, is greater than the width 422 of the device region 101. The active pads (128a-128d) are disposed on the side of the peripheral region 103 opposite to the corresponding spare pads (130a-130d), further increasing the distance between the active pads (128a-128d) and the spare pads (130a-130d). Therefore, the first chip (…) is affected by one or more bonding defect regions 136. Figure 1A 102) and the second IC chip ( Figure 1A Poor electrical connections between 104) may not adversely affect the performance of stacked IC devices.

[0074] In various embodiments, the lateral distance between the first active bonding pad 128a and the second active bonding pad 128b, and between the first spare bonding pad 130a and the second spare bonding pad 130b, is greater than 100 μm, within the range of about 100 to 300 μm, or some other suitable value. In other embodiments, the lateral distance between the third active bonding pad 128c and the fourth active bonding pad 128d, and between the third spare bonding pad 130c and the fourth spare bonding pad 130d, is greater than 100 μm, within the range of about 100 to 300 μm, or some other suitable value.

[0075] Figure 4C It shows Figure 4A Top layout view 400c of some other embodiments of the stacked IC device.

[0076] In some embodiments, the plurality of active bonding pads (128a-128d) and the plurality of spare bonding pads (130a-130d) are arranged within device region 101. This partially reduces the number of conductive interconnects and / or the length of conductive wires used to couple the active bonding pads (128a-128d) to the spare bonding pads (130a-130d). Therefore, manufacturing costs and complexity can be reduced, and the corresponding interconnect structure (e.g., ...) can be simplified. Figure 1A The parasitic capacitance in the first interconnect structure 110).

[0077] In various embodiments, it should be understood that, although Figures 4A to 4C Various embodiments of the first joining structure 114 are shown, but Figure 1A The second bonding structure 116 of the second IC chip 104 can be as follows Figures 4A to 4C The second bonding structure 116 of the second IC chip 104 may be configured as shown and / or described. For example, the layout of the first bonding structure 114 and the second bonding structure 116 is symmetrical.

[0078] Figure 5A A cross-sectional view 500a is shown of some embodiments of a stacked IC device having a bonding structure including active bonding pads and spare bonding pads. In some embodiments, Figure 5A The sectional view 500a can be viewed along... Figure 4B The line A-A' is cut off in the middle, where, for ease of explanation... Figure 5A Only a subset of the dummy bonding pads 126 in device area 101 is shown.

[0079] The stacked IC device includes a first IC chip 102 and a second IC chip 104. The first IC chip 102 includes a first substrate 106, a first interconnect structure 110, and a first bonding structure 114. The first IC chip 102 houses a first circuit 118. In various embodiments, the first circuit 118 includes a plurality of photodetectors 302, a first plurality of transistors 304, and a second plurality of transistors 306. The devices of the first circuit 118 (e.g., photodetectors 302 and transistors 304, 306) are arranged in a device region 101 of the stacked IC device. The second IC chip 104 includes a second substrate 108, a second interconnect structure 112, and a second bonding structure 116. The second IC chip 104 houses a second circuit 120. In some embodiments, the second circuit 120 includes a plurality of semiconductor devices 316 on the second substrate 108. The plurality of semiconductor devices 316 are arranged in the device region 101.

[0080] The first bonding structure 114 and the second bonding structure 116 each include a plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) disposed in the dielectric bonding structure 124 and arranged with a spacing P. The plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) includes a plurality of dummy bonding pads 126, a plurality of active bonding pads (128a, 128b), and a plurality of spare bonding pads (130a, 130b). The dummy bonding pads 126 are at least partially disposed in the device region 101. In various embodiments, the plurality of active bonding pads (128a, 128b) and the plurality of spare bonding pads (130a, 130b) are disposed on opposite sides of the device region 101.

[0081] Active bonding pads (128a, 128b) are configured to provide a first electrical connection (510a, 510b) at a bonding interface 105 between the first IC chip 102 and the second IC chip 104 (as shown by dashed lines). Spare bonding pads (130a, 130b) are configured to provide a second electrical connection (512a, 512b) at the bonding interface 105 between the first IC chip 102 and the second IC chip 104 (as shown by dashed lines). The active bonding pads (128a, 128b) are electrically coupled to corresponding spare bonding pads among the plurality of spare bonding pads (130a, 130b). In various embodiments, the second electrical connection (512a, 512b) repeats or replicates the first electrical connection (510a, 510b) between the devices of the first circuit 118 and the second circuit 120, such that the individual electrical path between the devices of the first circuit 118 and the second circuit 120 includes at least two connections at the bonding interface 105 (e.g., a first connection provided by active bonding pads (128a, 128b) and a second connection provided by spare bonding pads (130a, 130b). Therefore, the spare bonding pads (130a, 130b) facilitate dual-connection electrical coupling between the stacked IC devices of the first circuit 118 and the devices of the second circuit 120.

[0082] In various embodiments, a first active bonding pad 128a is directly electrically coupled to a first spare bonding pad 130a. The first active bonding pad 128a is laterally offset from the first spare bonding pad 130a by a first distance 502. A second active bonding pad 128b is directly electrically coupled to a second spare bonding pad 130b. The second active bonding pad 128b is laterally offset from the second spare bonding pad 130b by a second distance 504. In various embodiments, the first distance 502 and the second distance 504 are at least twice the pitch P and / or greater than the length of the device region 101. In yet another embodiment, the second distance 504 is greater than the first distance 502. Since the active bonding pads (128a, 128b) and the spare bonding pads (130a, 130b) are located on opposite sides of the device region 101, bonding defects (not shown) aligned with the active bonding pads (128a, 128b) do not affect the spare bonding pads (130a, 130b). In this situation, the first electrical connection (510a, 510b) may fail. However, the second electrical connection (512a, 512b) provided by the spare bonding pads (130a, 130b) remains intact, ensuring that the devices of the first circuit 118 and the second circuit 120 are properly coupled together. Therefore, the efficiency, reliability, and yield of the stacked IC device are increased.

[0083] Figure 5B A cross-sectional view 500b is shown of some embodiments of a stacked IC device having a bonding structure including active bonding pads and spare bonding pads. In some embodiments, Figure 5B The sectional view 500b can be viewed along... Figure 4B The line B-B' in the diagram is cut off, where, for ease of explanation... Figure 5B Only a subset of the dummy bonding pads 126 in device area 101 is shown.

[0084] In various embodiments, the bonding defect region 136 is aligned with the plurality of active bonding pads (128a, 128b), causing the first electrical connection (510a, 510b) to break and / or malfunction. This could be due, for example, to a void 146 at the bonding defect region 136 between the first IC chip 102 and the second IC chip 104. Since the active bonding pads (128a, 128b) and the spare bonding pads (130a, 130b) are located on opposite sides of the device region 101, the second electrical connection (512a, 512b) provided by the spare bonding pads (130a, 130b) is sufficiently far away from the bonding defect region 136. Therefore, the spare bonding pads (130a, 130b) maintain a good electrical connection between the first IC chip 102 and the second IC chip 104. Thus, the first circuit 118 and the second circuit 120 are properly coupled together, thereby increasing the efficiency, reliability, and yield of the stacked IC device.

[0085] Figure 6 A cross-sectional view 600 is shown of some embodiments of a stacked IC device having a bonding structure including multiple active bonding pads and multiple spare bonding pads. Figure 6 The stacked IC device may include Figure 3A Some aspects of stacked IC devices (and vice versa), therefore, the above regarding Figure 3A The explained features and / or figure references also apply. Figure 6 Stacked IC devices.

[0086] The stacked IC device includes a first IC chip 102 and a second IC chip 104. A first substrate 106 includes a front surface 106f opposite to a back surface 106b. In various embodiments, the first IC chip 102 also includes a deep trench isolation (DTI) structure 604 disposed in the first substrate 106. The DTI structure 604 is disposed between adjacent photodetectors of the plurality of photodetectors 302. In various embodiments, the DTI structure 604 surrounds the outer periphery of the plurality of photodetectors 302. The DTI structure 604 is configured to increase optical isolation between photodetectors 302 and increase electrical isolation between transistors (304, 306).

[0087] A mesh structure 606 is overlaid on the back surface 106b of the first substrate 106 and includes a plurality of sidewalls defining openings above the photodetectors 302. The mesh structure 606 is configured to reduce crosstalk between the plurality of photodetectors 302. An upper dielectric structure 608 is disposed on the back surface 106b of the first substrate 106. The upper dielectric structure 608 may be, for example, or include an oxide (e.g., silicon dioxide) or some other suitable dielectric material. A plurality of filters 610 are overlaid on the plurality of photodetectors 302. The filters 610 each include a material configured to allow wavelengths of a first range to pass while blocking wavelengths of a second range different from the first range. In addition, a plurality of microlenses 612 are overlaid on the filters 610 and configured to guide incident light toward the photodetectors 302.

[0088] A first shallow trench isolation (STI) structure 602 is disposed in the first substrate 106. Furthermore, an upper bonding assembly 614 is disposed in the peripheral region 103 and extends through the first substrate 106 to one or more conductive structures (e.g., conductive metal lines 326) in the first interconnect structure 110. In various embodiments, the upper bonding assembly 614 is configured to electrically couple a stacked IC device to some other electronic device (not shown). In some embodiments, the upper bonding assembly 614 is wire-bonded to another electronic device. The upper bonding assembly 614 may be configured for input / output (I / O) terminals, power terminals, or the like of the stacked IC device. In various embodiments, the upper bonding assembly 614 comprises copper, aluminum, some other conductive material, or any combination thereof. In some embodiments, the upper bonding assembly 614 extends through the first STI structure 602. In various embodiments, the second IC chip 104 includes a second STI structure 616 disposed in the second substrate 108 and between adjacent semiconductor devices in the plurality of semiconductor devices 316.

[0089] In various embodiments, the plurality of active bonding pads (128a, 128b) and the plurality of spare bonding pads (130a, 130b) are arranged on opposite sides of the upper bonding assembly 614. Therefore, the forces applied to the upper bonding assembly 614 when bonding or coupling it to another electronic device will not adversely affect the plurality of active bonding pads (128a, 128b) and the plurality of spare bonding pads (130a, 130b). For example, if the active bonding pads (128a, 128b) or spare bonding pads (130a, 130b) are laterally aligned with the upper bonding assembly 614, the mechanical stresses from bonding or coupling the upper bonding assembly 614 to another electronic device may cause damage (e.g., delamination, cracking, etc.) to the active bonding pads (128a, 128b) or spare bonding pads (130a, 130b). Therefore, the plurality of active bonding pads (128a, 128b) and the plurality of spare bonding pads (130a, 130b) arranged on opposite sides of the upper bonding assembly 614 increase the reliability and yield of the stacked IC device.

[0090] Figure 7 The diagram shows the section cut along line A-A'. Figure 6 Top layout view 700 of some embodiments of a stacked IC device.

[0091] In various embodiments, the stacked IC device includes a plurality of upper bonding assemblies 614, wherein a plurality of active bonding pads 128 and a plurality of spare bonding pads 130 are arranged on opposite sides of each of the upper bonding assemblies 614. The active bonding pads 128 are directly electrically coupled to corresponding spare bonding pads among the plurality of spare bonding pads 130, as shown in conductive path 202. It should be understood that, for ease of illustration, only some of the conductive paths 202 between the active bonding pads 128 and the spare bonding pads 130 are labeled and / or shown. In various embodiments, a bonding defect region 136 is aligned with a plurality of active bonding pads 128 adjacent to a first side 702 of the first upper bonding assembly 614a. The plurality of active bonding pads 128 on the first side 702 are electrically coupled to corresponding spare bonding pads 130 on a second side 704 of the first upper bonding assembly 614a. In some embodiments, the bonding defect area 136 aligned with the active bonding pad 128 on the first side 702 may be due to mechanical stress from bonding or coupling the first upper bonding assembly 614a to other electronic devices (not shown) and / or due to the first IC chip ( Figure 6 102) is bonded to the second IC chip ( Figure 6 This is caused by a problem at point 104. The plurality of active bonding pads 128 on the first side 702 are laterally offset from the plurality of spare bonding pads 130 on the second side 704 by a distance greater than at least twice the spacing P of the active bonding pads 128 or greater than the width 706 of the first upper bonding assembly 614a. Because the active bonding pads 128 on the first side 702 are relatively far from the spare bonding pads 130 on the second side 704, the bonding defect area 136 will not adversely affect the spare bonding pads 130 on the second side 704.

[0092] Figures 8 to 14 Various cross-sectional views (800-1400) are shown for some embodiments of a method for forming a stacked IC device having a bonding structure including active bonding pads and spare bonding pads. Although the method is described with reference to the method... Figures 8 to 14 The sectional views shown are (800-1400), but it should be understood that... Figures 8 to 14 The structure shown is not limited to the method shown, but can be independent of the method. Furthermore, although Figures 8 to 14 The actions are described as a series of actions, but it should be understood that these actions are not limited, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted, in whole or in part.

[0093] like Figure 8As shown in cross-sectional view 800, a first circuit 118 and a first interconnect structure 110 are provided or otherwise formed in a first IC chip 102. The first IC chip 102 includes a first substrate 106, the first circuit 118 on the first substrate 106, and the first interconnect structure 110 on the first substrate 106. In some embodiments, the first circuit 118 includes a plurality of photodetectors 302 disposed in the first substrate 106, a first plurality of transistors 304 disposed on the first substrate 106, and a second plurality of transistors 306 disposed on the first substrate 106. The first interconnect structure 110 includes a plurality of conductive metal lines 326, a plurality of vias 328, and a plurality of conductive contacts 330 disposed in an interconnect dielectric structure 324.

[0094] In some embodiments, the plurality of photodetectors 302 are formed in the first substrate 106 by one or more ion implantation processes. The first plurality of transistors 304 and the second plurality of transistors 306 may be formed on the first substrate 106 by one or more deposition processes, one or more ion implantation processes, one or more patterning processes, one or more planarization processes, some other suitable manufacturing processes, or any combination thereof. The plurality of conductive metal lines 326, the plurality of vias 328, and the plurality of conductive contacts 330 may be formed, for example, by one or more single damascene processes, dual damascene processes, or some other suitable manufacturing processes.

[0095] like Figure 9 As shown in the cross-sectional view 900, a dielectric bonding structure 124 is formed on the first interconnect structure 110. In some embodiments, the dielectric bonding structure 124 is formed on the first interconnect structure 110 by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable growth or deposition process. The dielectric bonding structure 124 may be, for example, an oxide (e.g., silicon dioxide) or some other dielectric material.

[0096] like Figure 10 As shown in the cross-sectional view 1000, a patterning process is performed on the dielectric bonding structure 124 to form a plurality of openings 1002 in the dielectric bonding structure 124. In some embodiments, the patterning process includes: forming a mask layer (not shown) on the dielectric bonding structure 124, performing an etching process (e.g., a dry etching process) on the dielectric bonding structure 124, and performing a removal process to remove the mask layer.

[0097] like Figure 11As shown in cross-sectional view 1100, a plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) are formed in a dielectric bonding structure 124, thereby forming or defining a first bonding structure 114 on a first interconnect structure 110. In some embodiments, the process for forming the plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) includes: over a first substrate 106 and in the plurality of openings ( Figure 10 The conductive material (e.g., copper, aluminum, tungsten, etc.) is deposited (e.g., by CVD, PVD, sputtering, electroplating, electroless plating, etc.) in 1002, and a planarization process (e.g., chemical mechanical planarization, CMP) is performed on the conductive material. The plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) may be, for example, or include copper, aluminum, tungsten, titanium nitride, tantalum nitride, some other conductive materials, or any combination thereof. In various embodiments, the process for forming the first bonding structure 114 includes... Figures 9 to 11 The processing steps shown and / or described.

[0098] The plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) comprises a plurality of dummy bonding pads 126, a plurality of active bonding pads (128a, 128b), and a plurality of spare bonding pads (130a, 130b) arranged at a spacing P. In various embodiments, the active bonding pads (128a, 128b) are directly coupled to their corresponding spare bonding pads (130a, 130b) via a first interconnect structure 110. The spacing P may be, for example, in the range of about 0.5 to 5 μm, 5 to 10 μm, 0.5 to 10 μm, greater than about 0.5 μm, less than about 10 μm, or some other suitable value. The active bonding pads (128a, 128b) are laterally offset from their corresponding spare bonding pads (130a, 130b) by a lateral distance 132. In various embodiments, the lateral distance 132 is equal to or greater than twice the spacing P (e.g., equal to or greater than P*2), greater than 10 μm, greater than 30 μm, in the range of 10 to 80 μm, or some other suitable value. The plurality of spare bonding pads (130a, 130b) facilitate the first IC chip 102 having at least two electrical connection points at the first bonding structure 114 for each connection to the first circuit 118. For example, the gate 308 of the first transistor 304a in the first plurality of transistors 304 includes a first connection point at the first active bonding pad 128a and a second connection point at the first spare bonding pad 130a.

[0099] In various embodiments, dishing can cause the upper surfaces of the active bonding pads (128a, 128b) to bend and extend below the top surface of the dielectric bonding structure 124. In various embodiments, dishing may occur due to problems in the planarization process, differences in material hardness between the active bonding pads (128a, 128b) and the dielectric bonding structure 124, etc. For example, active bonding pads (128a, 128b) may dig due to uneven pressure distribution of the CMP head used to perform the planarization process, while adjacent dummy bonding pads 126 may not dig.

[0100] In various embodiments, it should be understood that although the first engagement structure 114 is shown as... Figure 1B The layout shown and / or described is formed, but the first joining structure 114 may be formed by, for example, Figure 2A , Figure 2B , Figure 2C , Figure 4A , Figure 4B or Figure 4C Any of the layouts shown and / or described herein shall be formed.

[0101] like Figure 12 As shown in cross-sectional view 1200, a second circuit 120 and a second interconnect structure 112 are provided or otherwise formed on the second IC chip 104. The second IC chip 104 includes a second substrate 108, the second circuit 120 on the second substrate 108, and the second interconnect structure 112 on the second substrate 108. In some embodiments, the second circuit 120 includes a plurality of semiconductor devices 316 on the second substrate 108. The second interconnect structure 112 includes a plurality of conductive metal lines 326, a plurality of vias 328, and a plurality of conductive contacts 330 disposed in an interconnect dielectric structure 324.

[0102] The plurality of semiconductor devices 316 may be formed on the second substrate 108 by one or more deposition processes, one or more ion implantation processes, one or more patterning processes, one or more planarization processes, some other suitable manufacturing processes, or any combination thereof. The plurality of conductive metal lines 326, the plurality of vias 328, and the plurality of conductive contacts 330 may be formed, for example, by one or more single damascene processes, dual damascene processes, or some other suitable manufacturing processes.

[0103] like Figure 13As shown in the cross-sectional view 1300, a second bonding structure 116 is formed on the second interconnect structure 112. In some embodiments, the second bonding structure 116 includes a plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) disposed in the dielectric bonding structure 124. The plurality of conductive bonding pads (126, 128a, 128b, 130a, 130b) of the second bonding structure 116 include a plurality of dummy bonding pads 126, a plurality of active bonding pads (128a, 128b), and a plurality of spare bonding pads (130a, 130b) arranged at a spacing P. In various embodiments, the second bonding structure 116 is connected via... Figures 9 to 11 Formed by the processing steps shown and / or described. In yet another embodiment, the first joining structure ( Figure 14 The first 114) and the second joint structure 116 have a symmetrical layout.

[0104] like Figure 14 As shown in cross-sectional view 1400, a first IC chip 102 is flipped and bonded to a second IC chip 104, such that a bonding interface 105 is disposed between a first bonding structure 114 and a second bonding structure 116. In some embodiments, bonding the first IC chip 102 to the second IC chip 104 includes: aligning the first IC chip 102 and the second IC chip 104; contacting the first bonding structure 114 and the second bonding structure 116; and applying pressure to the first IC chip 102 and / or the second IC chip 104. In various embodiments, the temperature of the first bonding structure 114 and the second bonding structure 116 may be increased along with the applied pressure to form the bonding interface 105.

[0105] In various embodiments, when the first IC chip 102 is bonded to the second IC chip 104, a bonding defect region 136 is formed and / or present between the first IC chip 102 and the second IC chip 104. A void 146 may exist at the bonding defect region 136 between the first IC chip 102 and the second IC chip 104. The bonding defect region 136 may occur due to problems during the bonding of the first IC chip 102 and the second IC chip 104. In various embodiments, recesses in the active bonding pads (128a, 128b) of the first bonding structure 114 due to CMP processing may cause voids 146 in the bonding defect region 136. In other embodiments, the bonding defect region 136 may be caused by a relatively large total thickness variation (TTV) between the first bonding structure 114 and the second bonding structure 116, a large step height of the first or second IC chip (102, 104), complication during bonding, or similar problems. Aperture 146 may cause poor electrical coupling (e.g., open circuit) between the active bonding pads (128a, 128b) of the first bonding structure 114 and the second bonding structure 116, causing the first electrical connection provided by the active bonding pads (128a, 128b) between the first circuit 118 and the second circuit 120 to fail. However, the relatively large lateral distance 132 between the spare bonding pads (130a, 130b) and the active bonding pads (128a, 128b) helps to prevent the spare bonding pads (130a, 130b) from being adversely affected by the bonding defect region 136. Therefore, the second electrical connection provided by the spare bonding pads (130a, 130b) can achieve proper electrical coupling between the first circuit 118 and the second circuit 120. As a result, the performance, reliability, and yield of the first IC chip 102 and the second IC chip 104 are increased.

[0106] Figure 15 Some embodiments of a method 1500 for forming a stacked IC device having a bonding structure including active bonding pads and spare bonding pads are shown. Although method 1500 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the shown order or actions. Therefore, in some embodiments, actions may be performed in a different order than shown and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted and other actions or events not shown may be included.

[0107] At action 1502, the first circuit is formed on the first substrate of the first IC chip. Figure 8A cross-sectional view 800 corresponding to some embodiments of action 1502 is shown.

[0108] At action 1504, a first interconnect structure is formed on the first substrate. Figure 8 A cross-sectional view 800 corresponding to some embodiments of action 1504 is shown.

[0109] At action 1506, a first bonding structure is formed on the first interconnect structure. The first bonding structure includes a plurality of dummy bonding pads, a plurality of active bonding pads, and a plurality of spare bonding pads arranged at a distance. The active bonding pads are electrically coupled to their corresponding spare bonding pads, wherein the lateral distance between an individual active bonding pad and its corresponding spare bonding pad is greater than the distance between them. Figures 9 to 11 Cross-sectional views (900-1100) are shown for some embodiments corresponding to action 1506.

[0110] At action 1508, the second circuit is formed on the second substrate of the second IC chip. Figure 12 A cross-sectional view 1200 corresponding to some embodiments of action 1508 is shown.

[0111] At action 1510, a second interconnect structure is formed on the second substrate. Figure 12 Some embodiments of action 1510 are shown in the sectional view 1200.

[0112] At action 1512, a second bonding structure is formed on the second interconnect structure. The second bonding structure includes multiple dummy bonding pads, multiple active bonding pads, and multiple spare bonding pads, wherein the active bonding pads are electrically coupled to their respective spare bonding pads. Figure 13 A cross-sectional view 1300 corresponding to some embodiments of action 1512 is shown.

[0113] At action 1514, the first IC chip is bonded to the second IC chip, such that the first bonding structure intersects with the second bonding structure at the bonding interface. Figure 14 A cross-sectional view 1400 corresponding to some embodiments of action 1514 is shown.

[0114] Therefore, in some embodiments, this disclosure relates to a stacked IC device including a first IC chip and a second IC chip, wherein the first and second IC chips include bonding structures, the bonding structures respectively including a plurality of dummy bonding pads, a plurality of active bonding pads, and a plurality of spare bonding pads arranged at a distance. The active bonding pads are coupled to corresponding spare bonding pads, wherein the lateral distance between an individual active bonding pad and its corresponding spare bonding pad is greater than the distance between the two pads.

[0115] In some embodiments, this application provides an integrated circuit (IC) device comprising: a dielectric structure on a semiconductor substrate, a plurality of active bonding pads in the dielectric structure, and a plurality of auxiliary bonding pads in the dielectric structure and laterally offset from the plurality of active bonding pads by a first distance, the first distance being greater than the spacing between the plurality of active bonding pads, wherein the active bonding pads are electrically coupled to corresponding auxiliary bonding pads among the plurality of auxiliary bonding pads.

[0116] In some embodiments, the integrated circuit device further includes an interconnect structure between the semiconductor substrate and the dielectric structure, wherein the interconnect structure includes a plurality of conductive metal lines and a plurality of vias, wherein a first active bonding pad in the active bonding pad is directly electrically coupled to a first auxiliary bonding pad in the auxiliary bonding pad through a first subset of the conductive metal lines in the conductive metal lines and a first subset of the vias in the vias. In some embodiments, the integrated circuit device further includes a semiconductor device disposed on the semiconductor substrate, wherein both the first auxiliary bonding pad and the first active bonding pad are directly electrically coupled to the semiconductor device through the first subset of the conductive metal lines and vias of the semiconductor substrate. In some embodiments, the active bonding pads are arranged in an array, the array including one or more rows and one or more columns, wherein a first distance is greater than the column length of the array. In some embodiments, the integrated circuit device further includes a plurality of dummy bonding pads in the dielectric structure, wherein one or more of the dummy bonding pads are disposed between the active bonding pads and the auxiliary bonding pads. In some embodiments, a first number of active bonding pads is equal to a second number of auxiliary bonding pads, wherein a third number of dummy bonding pads is greater than the first number and the second number. In some embodiments, the integrated circuit device further includes a plurality of external auxiliary bonding pads in the dielectric structure and laterally offset from the active bonding pads by a second distance, the second distance being greater than the spacing of the active bonding pads, wherein each active bonding pad is directly electrically coupled to a corresponding external auxiliary bonding pad. In some embodiments, the second distance is greater than the first distance, and the auxiliary bonding pads are laterally spaced from the active bonding pads and the external auxiliary bonding pads.

[0117] In another embodiment, this application provides a stacked integrated circuit (IC) device comprising: a first IC chip including a first substrate, a first interconnect structure on the first substrate, and a first bonding structure on the first interconnect structure, wherein the first bonding structure includes a plurality of first active bonding pads, a plurality of first auxiliary bonding pads, and a plurality of dummy bonding pads, wherein at least one dummy bonding pad is laterally disposed between the plurality of first active bonding pads and the plurality of first auxiliary bonding pads; and a second IC chip including a second substrate, a second interconnect structure on the second substrate, a second bonding structure on the second interconnect structure, and a bonding interface disposed between the first bonding structure and the second bonding structure, wherein the plurality of first active bonding pads are configured to provide a first electrical connection between the first and second IC chips, and wherein the plurality of first auxiliary bonding pads are configured to provide a second electrical connection that repeats the first electrical connection between the first and second IC chips.

[0118] In some embodiments, individual active bonding pads of the first active bonding pad are coupled to individual auxiliary bonding pads of the first auxiliary bonding pad, wherein apertures are disposed between the individual active bonding pads and the second bonding structure, wherein the individual auxiliary bonding pads have ohmic contact with bonding pads of the second interconnect structure. In some embodiments, the first integrated circuit chip includes a plurality of photodetectors and a plurality of first transistors disposed in a device region of the first substrate, a peripheral region of the first substrate being configured to surround the device region, wherein the first active bonding pads and the first auxiliary bonding pads are disposed in the peripheral region. In some embodiments, the first active bonding pads are disposed on a first side of the peripheral region, and the first auxiliary bonding pads are disposed on a second side of the peripheral region opposite to the first side, wherein the first auxiliary bonding pads are laterally offset from the first active bonding pads by a lateral distance greater than the length of the device region. In some embodiments, the first bonding structure further includes a plurality of second active bonding pads disposed on a third side of the peripheral region and a plurality of second auxiliary bonding pads disposed on a fourth side of the peripheral region opposite to the third side, wherein the second active bonding pads are electrically coupled to corresponding auxiliary bonding pads in the second auxiliary bonding pads. In some embodiments, the integrated circuit device further includes an upper bonding assembly extending through the first substrate and across the first interconnect structure, wherein the upper bonding assembly is disposed in the peripheral region, and wherein the first active bonding pad and the first auxiliary bonding pad are disposed on opposite sides of the upper bonding assembly. In some embodiments, a dummy bonding pad is disposed around the first active bonding pad and the first auxiliary bonding pad, wherein the dummy bonding pad is electrically isolated from the conductive structures of the first interconnect structure and the second interconnect structure.

[0119] In various embodiments, this application provides a method for forming a stacked integrated circuit (IC) device, comprising: forming a plurality of semiconductor devices in a device region of a first substrate; forming a first interconnect structure on the first substrate; forming a first bonding structure on the first interconnect structure, wherein the first bonding structure includes a plurality of dummy bonding pads, a plurality of active bonding pads, and a plurality of auxiliary bonding pads arranged at a spacing, wherein the active bonding pads are electrically coupled to corresponding auxiliary bonding pads among the plurality of auxiliary bonding pads, wherein a first lateral distance between the active bonding pads and the auxiliary bonding pads is equal to or greater than twice the spacing, wherein the first substrate, the first interconnect structure, and the first bonding structure define a first IC chip; and a second bonding structure for bonding the first IC chip to a second IC chip, wherein a bonding interface is arranged between the first bonding structure and the second bonding structure.

[0120] In some embodiments, the first bonding structure further includes a plurality of external auxiliary bonding pads laterally offset from the active bonding pad by a second lateral distance, wherein the external auxiliary bonding pads are directly coupled to individual active bonding pads and individual auxiliary bonding pads among the auxiliary bonding pads. In some embodiments, the second lateral distance is greater than the first lateral distance. In some embodiments, in a top layout view, the sidewalls of each of the active bonding pads are arranged on the same plane as the sidewalls of the corresponding auxiliary bonding pads among the auxiliary bonding pads. In some embodiments, the active bonding pads and the auxiliary bonding pads are arranged along a first side of the device region.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. An integrated circuit device, characterized by include: Dielectric structure on a semiconductor substrate; Multiple active bonding pads are present in the dielectric structure; as well as Multiple auxiliary bonding pads are located in the dielectric structure and are laterally offset from the active bonding pads by a first distance, the first distance being greater than the spacing of the active bonding pads, wherein the active bonding pads are electrically coupled to corresponding auxiliary bonding pads in the auxiliary bonding pads.

2. The integrated circuit device of claim 1, wherein, Also includes: An interconnect structure is provided between the semiconductor substrate and the dielectric structure, wherein the interconnect structure includes a plurality of conductive metal lines and a plurality of vias, wherein a first active bonding pad in the active bonding pad is directly electrically coupled to a first auxiliary bonding pad in the auxiliary bonding pad through a first subset of the conductive metal lines in the conductive metal lines and a first subset of the vias in the vias.

3. The integrated circuit device of claim 1, wherein, The active bonding pads are arranged in an array, the array comprising one or more rows and one or more columns, wherein the first distance is greater than the column length of the array.

4. The integrated circuit device of claim 1, wherein, Also includes: Multiple dummy bonding pads are provided in the dielectric structure, wherein one or more of the dummy bonding pads are arranged between the active bonding pad and the auxiliary bonding pad.

5. The integrated circuit device according to claim 1, characterized in that, Also includes: Multiple external auxiliary bonding pads are located in the dielectric structure and are laterally offset from the active bonding pads by a second distance, the second distance being greater than the spacing of the active bonding pads, wherein each active bonding pad is directly electrically coupled to its corresponding external auxiliary bonding pad.

6. An integrated circuit device, characterized in that, include: A first integrated circuit chip includes a first substrate, a first interconnect structure on the first substrate, and a first bonding structure on the first interconnect structure, wherein the first bonding structure includes a plurality of first active bonding pads, a plurality of first auxiliary bonding pads, and a plurality of dummy bonding pads, wherein at least one of the dummy bonding pads is laterally disposed between the first active bonding pads and the first auxiliary bonding pads. The second integrated circuit chip includes a second substrate, a second interconnect structure on the second substrate, and a second bonding structure on the second interconnect structure; as well as A bonding interface is disposed between the first bonding structure and the second bonding structure, wherein the first active bonding pad is configured to provide a first electrical connection between the first integrated circuit chip and the second integrated circuit chip, and wherein the first auxiliary bonding pad is configured to provide a second electrical connection between the first integrated circuit chip and the second integrated circuit chip that repeats the first electrical connection.

7. The integrated circuit device according to claim 6, characterized in that, Individual active bonding pads of the first active bonding pad are coupled to individual auxiliary bonding pads of the first auxiliary bonding pad, wherein pores are arranged between the individual active bonding pads and the second bonding structure, wherein the individual auxiliary bonding pads have ohmic contact with the bonding pads of the second interconnect structure.

8. The integrated circuit device according to claim 6, characterized in that, The first integrated circuit chip includes a plurality of photodetectors and a plurality of first transistors disposed in a device region of the first substrate, and a peripheral region of the first substrate is configured to surround the device region, wherein the first active bonding pad and the first auxiliary bonding pad are disposed in the peripheral region.

9. The integrated circuit device according to claim 8, characterized in that, The first active bonding pad is disposed on a first side of the peripheral area, and the first auxiliary bonding pad is disposed on a second side of the peripheral area opposite to the first side, wherein the first auxiliary bonding pad is laterally offset from the first active bonding pad by a lateral distance greater than the length of the device area.

10. The integrated circuit device according to claim 6, characterized in that, The dummy bonding pad is arranged around the first active bonding pad and the first auxiliary bonding pad, wherein the dummy bonding pad is electrically isolated from the conductive structures of the first interconnect structure and the second interconnect structure.

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