An FPGA protection device
By designing a fast discharge circuit and load capacitor for the FPGA protection device, the problem of power-on loading failure caused by voltage drop after FPGA shutdown was solved, ensuring normal FPGA operation and reducing additional detection and power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 深圳山灵数码科技发展有限公司
- Filing Date
- 2025-06-10
- Publication Date
- 2026-05-29
AI Technical Summary
The FPGA remained at 0.7V for several minutes after being powered off. Immediately powering it on caused the power-on program to fail and prevented it from working properly.
Design an FPGA protection device, including a fast discharge circuit and a load capacitor. Utilize a circuit composed of PNP and NPN transistors, Schottky diodes, and resistors to achieve rapid discharge of the operating power supply and prevent energy accumulation when the voltage drops.
It enables rapid discharge of the operating power supply after power-off, avoiding the problem of FPGA power-on program loading failure, ensuring normal FPGA operation, and reducing additional detection and power consumption.
Smart Images
Figure CN224305657U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic technology, and in particular to an FPGA protection device. Background Technology
[0002] As FPGAs are increasingly used in desktop applications, the early manufacturing processes of FPGA chips were not perfect, and the power-on timing requirements were quite strict. The power supply voltage of an FPGA will remain at approximately 0.7V for a few minutes after it is powered off. If the power is turned on immediately, the FPGA will fail to load the program and will not be able to work properly. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide an FPGA protection device to solve the technical problem that the FPGA fails to work properly when the FPGA is powered on and loaded with the program immediately after being powered off.
[0004] To solve the above-mentioned technical problems, the purpose of this utility model is achieved through the following technical solution: An FPGA protection device is provided, connected to a power supply and an FPGA. The power supply is connected to the FPGA. The FPGA protection device includes a fast discharge circuit and a load capacitor. The fast discharge circuit includes a first diode, a second polarized capacitor, a first switching transistor, a second switching transistor, a first resistor, a second resistor, a third resistor, and a fifth resistor. The anode of the first diode is electrically connected between the power supply and the FPGA. The cathode of the first diode is connected to the positive terminal of the second polarized capacitor. The negative terminal of the second polarized capacitor is grounded. The control terminal of the first switching transistor is connected to the power supply through the first resistor. The first terminal of the first switching transistor is connected to the cathode of the first diode and the positive terminal of the second polarized capacitor. The second terminal of the first switching transistor is grounded through the second resistor. The second terminal of the first switching transistor is connected to the input terminal of the second switching transistor through the third resistor. The output terminal of the second switching transistor is electrically connected between the power supply and the FPGA through the fifth resistor. One end of the load capacitor is grounded, and the other end of the load capacitor is electrically connected between the power supply and the FPGA.
[0005] The further technical solution is as follows: the first switching transistor is a PNP transistor, the second switching transistor is an NPN transistor, the base of the first switching transistor is connected to the operating power supply through the first resistor, the emitter of the first switching transistor is connected to the cathode of the first diode and the positive terminal of the second polarized capacitor, the collector of the first switching transistor is connected to one end of the second resistor and one end of the third resistor respectively, the other end of the second resistor is grounded, the other end of the third resistor is connected to the base of the second switching transistor, the collector of the second switching transistor is connected to one end of the fifth resistor, the other end of the fifth resistor is electrically connected between the operating power supply and the FPGA, and the emitter of the second switching transistor is grounded.
[0006] The further technical solution is as follows: the load capacitor is a polarized capacitor, the negative terminal of the load capacitor is grounded, and the positive terminal of the load capacitor is connected to the power supply and the FPGA respectively.
[0007] The further technical solution is as follows: the first diode is a surface-mount Schottky diode of model SS34.
[0008] A further technical solution is that the resistance values of the first resistor and the third resistor are the same.
[0009] The further technical solution is as follows: the resistance values of the first resistor and the third resistor are both 1KΩ, and the resistance value of the second resistor is 10KΩ.
[0010] The further technical solution is as follows: the FPGA protection device further includes a first polarized capacitor, the positive terminal of the first polarized capacitor is connected to the working power supply, and the negative terminal of the first polarized capacitor is grounded.
[0011] The further technical solution is that the capacitance of the first polarized capacitor is the same as the capacitance of the second polarized capacitor.
[0012] The beneficial technical effects of this utility model are as follows: The FPGA protection device of this utility model is electrically connected between the interconnected power supply and the FPGA. The FPGA protection device includes a fast discharge circuit and a load capacitor. The fast discharge circuit includes a first diode, a second polarized capacitor, a first switching transistor, a second switching transistor, a first resistor, a second resistor, a third resistor, and a fifth resistor. When the power is on, the power supply provides stable power, and the power supply charges the second polarized capacitor through the first diode. The first switching transistor is turned off, and the second switching transistor is turned off, so that the power supply directly supplies power to the FPGA. When the power is off, the voltage of the power supply drops, the first diode is turned off, and the control of the first switching transistor... The control terminal is connected to the operating power supply through the first resistor. The first terminal of the first switching transistor is connected to the positive terminal of the second polarized capacitor. One end of the load capacitor is grounded, and the other end of the load capacitor is electrically connected between the operating power supply and the FPGA. When the voltage on the load capacitor drops, the first switching transistor turns on, thereby controlling the second switching transistor to turn on. The current in the second polarized capacitor is quickly released through the first switching transistor and the first, second, third, and second switching transistors. The current in the load capacitor is quickly released through the fifth resistor and the second switching transistor, realizing the rapid discharge of the operating power supply after power-off. This avoids the problem of the FPGA failing to load the program and thus not working properly when the power is turned on immediately after power-off. Attached Figure Description
[0013] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0014] Figure 1 The circuit diagram shows the specific application of the FPGA protection device provided in this embodiment of the utility model. Detailed Implementation
[0015] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.
[0016] Please see Figure 1 , Figure 1This is a circuit diagram illustrating the specific application of the FPGA protection device provided in this embodiment of the present invention. The FPGA protection device is connected to both the operating power supply and the FPGA 20. The operating power supply is connected to the FPGA 20. The FPGA protection device includes a fast discharge circuit 11 and a load capacitor C3. The fast discharge circuit 11 includes a first diode D1, a second polarized capacitor C2, a first switching transistor Q1, a second switching transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a fifth resistor R5. The anode of the first diode D1 is connected between the operating power supply and the FPGA 20, and the cathode of the first diode D1 is connected to the anode of the second polarized capacitor C2. The negative terminal of capacitor C2 is grounded. The control terminal of the first switching transistor Q1 is connected to the operating power supply through the first resistor R1. The first terminal of the first switching transistor Q1 is connected to the cathode of the first diode D1 and the positive terminal of the second polarized capacitor C2. The second terminal of the first switching transistor Q1 is grounded through the second resistor R2. The second terminal of the first switching transistor Q1 is connected to the input terminal of the second switching transistor Q2 through the third resistor R3. The output terminal of the second switching transistor Q2 is electrically connected between the operating power supply and the FPGA20 through the fifth resistor R5. One end of the load capacitor C3 is grounded, and the other end of the load capacitor C3 is electrically connected between the operating power supply and the FPGA20.
[0017] The operating power supply is used to power the FPGA20. This power supply can be provided by a power module. When powered on, the voltage of the operating power supply can be 3.3V. The FPGA protection device is electrically connected between the interconnected operating power supply and the FPGA20. The FPGA protection device includes a fast discharge circuit 11 and a load capacitor C3. The fast discharge circuit 11 includes a first diode D1, a second polarized capacitor C2, a first switch Q1, a second switch Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a fifth resistor R5. When powered on, the operating power supply provides stable power. The operating power supply charges the second polarized capacitor C2 through the first diode D1. The first switch Q1 and the second switch Q2 are both turned off, allowing the operating power supply to directly power the FPGA20. When powered off, the voltage of the operating power supply drops, the first diode D1 is turned off, and the control terminal of the first switch Q1 is connected to the operating power supply through the first resistor R1. The first terminal of capacitor C1 is connected to the positive terminal of the second polarity capacitor C2. One end of the load capacitor C3 is grounded, and the other end of the load capacitor C3 is electrically connected between the power supply and the FPGA20. When the voltage across the load capacitor C3 drops, the first switch turns on, thereby controlling the second switch Q2 to turn on. The current in the second polarity capacitor C2 is quickly released through the first switch Q1 and the first resistor R1, the second resistor R2, the third resistor R3 and the second switch Q2. The current in the load capacitor C3 is quickly released through the fifth resistor R5 and the second switch Q2, realizing the rapid discharge of the power supply after power-off. This allows the power supply to quickly stop supplying power to the FPGA after power-off, avoiding the problem that the FPGA20 fails to load the program and cannot work properly when powering on immediately after power-off. Furthermore, there is no need to set an additional power input for power-off detection, so as to avoid the additional power input affecting the power-on sequence of the power supply and thus affecting the normal operation of the FPGA20, and reducing power consumption.
[0018] Specifically, in this embodiment, the first switch Q1 is a PNP transistor, and the second switch Q2 is an NPN transistor. The base of the first switch Q1 is connected to the operating power supply through the first resistor R1. The emitter of the first switch Q1 is connected to the cathode of the first diode D1 and the anode of the second polarized capacitor C2. The collector of the first switch Q1 is connected to one end of the second resistor R2 and one end of the third resistor R3. The other end of the second resistor R2 is grounded. The other end of the third resistor R3 is connected to the base of the second switch Q2. The collector of the second switch Q2 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is electrically connected between the operating power supply and the FPGA 20. The emitter of the second switch Q2 is grounded.
[0019] Specifically, the load capacitor C3 is a polarized capacitor, with its negative terminal grounded and its positive terminal connected to both the power supply and the FPGA20.
[0020] Preferably, in this embodiment, the first diode D1 is a surface-mount Schottky diode of type SS34.
[0021] Specifically, in this embodiment, the first resistor R1 and the third resistor R3 have the same resistance value. Preferably, the first resistor R1 and the third resistor R3 both have a resistance value of 1KΩ, the second resistor R2 has a resistance value of 10KΩ, and the fifth resistor R5 has a resistance value of 100Ω.
[0022] Specifically, in this embodiment, the FPGA protection device further includes a first polarized capacitor C1, the positive terminal of which is connected to the operating power supply, and the negative terminal of which is grounded.
[0023] Specifically, the capacitance of the first polarized capacitor C1 is the same as that of the second polarized capacitor C2.
[0024] In summary, the FPGA protection device of this invention is electrically connected between the interconnected power supply and the FPGA. The FPGA protection device includes a fast discharge circuit and a load capacitor. The fast discharge circuit includes a first diode, a second polarized capacitor, a first switching transistor, a second switching transistor, a first resistor, a second resistor, a third resistor, and a fifth resistor. When the device is powered on, the power supply provides stable power, charging the second polarized capacitor through the first diode. The first and second switching transistors are off, allowing the power supply to directly power the FPGA. When the device is powered off, the voltage of the power supply drops, the first diode is off, and the control terminal of the first switching transistor is connected to the first diode via the second polarized capacitor. A resistor is connected to the operating power supply. The first terminal of the first switching transistor is connected to the positive terminal of the second polarized capacitor. One end of the load capacitor is grounded, and the other end of the load capacitor is electrically connected between the operating power supply and the FPGA. When the voltage across the load capacitor drops, the first switching transistor turns on, thereby controlling the second switching transistor to turn on. The current in the second polarized capacitor is quickly released through the first switching transistor and the first, second, third, and second switching transistors. The current in the load capacitor is quickly released through the fifth resistor and the second switching transistor, realizing the rapid discharge of the operating power supply after power-off. This avoids the problem of the FPGA failing to load the program and thus not working properly when the power is turned on immediately after power-off.
[0025] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.
Claims
1. An FPGA protection device, characterized in that, The circuit is connected to both the operating power supply and the FPGA. The operating power supply is connected to the FPGA. The FPGA protection device includes a fast discharge circuit and a load capacitor. The fast discharge circuit includes a first diode, a second polarized capacitor, a first switching transistor, a second switching transistor, a first resistor, a second resistor, a third resistor, and a fifth resistor. The anode of the first diode is connected between the operating power supply and the FPGA. The cathode of the first diode is connected to the positive terminal of the second polarized capacitor. The negative terminal of the second polarized capacitor is grounded. The control terminal of the first switching transistor is connected to the operating power supply through the first resistor. The first terminal of the first switching transistor is connected to the cathode of the first diode and the positive terminal of the second polarized capacitor. The second terminal of the first switching transistor is grounded through the second resistor. The second terminal of the first switching transistor is connected to the input terminal of the second switching transistor through the third resistor. The output terminal of the second switching transistor is electrically connected between the operating power supply and the FPGA through the fifth resistor. One end of the load capacitor is grounded, and the other end of the load capacitor is electrically connected between the operating power supply and the FPGA.
2. The FPGA protection device according to claim 1, characterized in that, The first switching transistor is a PNP transistor, and the second switching transistor is an NPN transistor. The base of the first switching transistor is connected to the operating power supply through the first resistor. The emitter of the first switching transistor is connected to the cathode of the first diode and the positive terminal of the second polarized capacitor. The collector of the first switching transistor is connected to one end of the second resistor and one end of the third resistor. The other end of the second resistor is grounded. The other end of the third resistor is connected to the base of the second switching transistor. The collector of the second switching transistor is connected to one end of the fifth resistor. The other end of the fifth resistor is electrically connected between the operating power supply and the FPGA. The emitter of the second switching transistor is grounded.
3. The FPGA protection device according to claim 1, characterized in that, The load capacitor is a polarized capacitor, with its negative terminal grounded and its positive terminal connected to both the power supply and the FPGA.
4. The FPGA protection device according to claim 1, characterized in that, The first diode is a surface-mount Schottky diode of model SS34.
5. The FPGA protection device according to claim 1, characterized in that, The first resistor and the third resistor have the same resistance value.
6. The FPGA protection device according to claim 5, characterized in that, The resistance values of the first resistor and the third resistor are both 1KΩ, and the resistance value of the second resistor is 10KΩ.
7. The FPGA protection device according to claim 1, characterized in that, The FPGA protection device also includes a first polarized capacitor, the positive terminal of which is connected to the operating power supply, and the negative terminal of which is grounded.
8. The FPGA protection device according to claim 7, characterized in that, The capacitance of the first polarity capacitor is the same as that of the second polarity capacitor.