An SRAM contact hole test verification structure
By designing an SRAM contact hole test verification structure and utilizing test ports and leakage current detection ports, the problems of gate connection open circuit and leakage current caused by conductive via misalignment were solved, enabling precise adjustment of the manufacturing process and improving the reliability of SRAM.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- MAXSCEND SEMICONDUCTOR LAKEVIEW CO LTD
- Filing Date
- 2025-05-16
- Publication Date
- 2026-05-29
Smart Images
Figure CN224306185U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor processing technology, specifically to an SRAM contact hole test and verification structure. Background Technology
[0002] In integrated circuit manufacturing, contact vias (CTs) are crucial process modules used to connect the source / drain, gate, and back-to-office (BEOL) interconnects of devices. As chip integration density increases and design specifications shrink, contact via photolithography alignment errors have become one of the main technical challenges in through-hole etching. In the highest-density static random access memory (SRAM) region, besides square contact vias connecting the source / drain, there is also a type of contact via (Shared CT) that connects both the source / drain and gate. Figure 1 Here is a schematic diagram of its cross-sectional structure.
[0003] When the photolithographic overlay accuracy of the gate in Shared CT deviates significantly, such as Figure 2 As shown, the first direction X offset will cause the connection between the gate contact via and the gate to be broken. Figure 2 At point A in the middle, for the other side gate ( Figure 1 Figure 2 Increased leakage current in the Poly signal on the right side of ShareCT (ShareCT) Figure 2 (At point B in the middle), this will increase the power consumption of SRAM, or even cause it to malfunction.
[0004] In existing manufacturing processes, the positional offset of conductive vias is used to determine whether leakage or open circuit has occurred. However, when the density of the metal layers connected by the conductive vias is high, the spacing between adjacent metal lines is very small, making it difficult to directly connect two adjacent metal lines to determine whether the above situations have occurred. Therefore, a solution is needed to verify whether the offset of SRAM conductive vias leads to an open circuit in the gate connection and leakage on the other side when the metal layer structure of the conductive vias is relatively dense. Utility Model Content
[0005] In view of this, this application provides an SRAM contact hole test verification structure to solve the problem of how to verify whether the offset of the conductive via leads to an open circuit in the gate connection and leakage on the other side when the metal layer structure of the SRAM conductive via connection is relatively dense.
[0006] In one aspect of this application, an SRAM contact via test verification structure is provided for testing and verifying whether the offset of the gate contact via leads to an open circuit in the gate connection and leakage on the other side when the metal layer structure of the SRAM gate contact via connection is relatively dense. The structure includes: a simulation module and a test module connected thereto; the simulation module includes: a single-crystal silicon layer; a gate polysilicon layer located on the single-crystal silicon layer; a gate contact via layer including a plurality of gate contact vias connecting the top of the gate polysilicon layer and the single-crystal silicon layer exposed on the side of the gate polysilicon layer; and a detection polysilicon layer disposed parallel to the gate polysilicon layer, with the gate contact via layer located on the detection polysilicon layer. Between the silicon layer and the gate polysilicon layer; a metal layer, located above the gate contact via layer and connected to the gate contact via; the test module includes: a first test port extending from the metal layer to the outside of the analog module, and a second test port positioned opposite the first test port; the connection path between the first test port and the second test port passes through the entire monocrystalline silicon layer, the gate polysilicon layer, and the gate contact via layer; a leakage current test port extending from the detection polysilicon layer to the outside of the analog module; one of the first test port and the second test port is adapted to power on the analog module, and the other is adapted to test whether it is conductive; the leakage current test port is adapted to test whether there is leakage.
[0007] The SRAM contact via test and verification structure provided in this application simulates the designed SRAM layout using a simulation module. A first test port extending from the metal layer to the outside of the simulation module, and a second test port positioned opposite the first test port, allow power to be supplied to the simulation module via one of these ports. A connected test instrument then tests whether there is continuity between the first and second test ports. Since the connection path includes the entire monocrystalline silicon layer, the gate polycrystalline silicon layer, and the gate contact via layer, the continuity between the first and second test ports verifies whether an open circuit occurs between the gate contact via and the gate monocrystalline silicon layer. A leakage current test port led out from the detection polycrystalline silicon layer on the side of the gate contact via can test whether leakage current occurs between the side of the gate contact via and the corresponding detection polycrystalline silicon layer. Therefore, by designing the gate connection via with an offset size using the SRAM contact via test and verification structure provided in this application, it is possible to verify whether the gate connection via is open-circuited and whether leakage occurs at that offset size. Furthermore, by providing multiple SRAM contact holes to test and verify the structure, and setting them to different offset sizes, it is possible to verify whether there is an open circuit and whether leakage occurs under multiple offset sizes. Ultimately, the limit size that the design can be offset can be obtained, thereby assisting in adjusting the design size.
[0008] Optionally, in some embodiments of this application, the SRAM contact hole test verification structure includes multiple simulation modules and corresponding test modules; the simulation modules are connected end-to-end through a first test port and a second test port; the unused first test port is used as the first test port of the overall structure, and the unused second test port is used as the second test port of the overall structure; each test module shares the same leakage current test port.
[0009] Optionally, in some embodiments of this application, the test module includes two sets of structures arranged in a mirror image; each set of structures includes several strip-shaped single-crystal silicon structures extending along a first direction and arranged parallel to each other along a second direction, with the strip-shaped single-crystal silicon structures in the two sets of structures corresponding one-to-one, wherein the strip-shaped single-crystal silicon structures at one end along the second direction in the two sets of structures are connected as one unit; the second direction is perpendicular to the first direction; each set of structures includes several strip-shaped gate polysilicon structures spaced apart along the second direction, wherein each strip-shaped gate polysilicon structure has its two ends along the second direction located on a strip-shaped single-crystal silicon structure; adjacent strip-shaped gate polysilicon structures in the second direction are spaced apart by the distance between adjacent strip-shaped single-crystal silicon structures in the second direction; each set of structures includes several gate contacts. The gate contact via includes a first portion located on the strip-shaped monocrystalline silicon and on the side of the gate polycrystalline silicon, and a second portion spanning the top of the gate polycrystalline silicon and the top of the first portion; the second portion is integrally connected to the first portion and is connected to the strip-shaped gate polycrystalline silicon structure, and the first portion is connected to the strip-shaped monocrystalline silicon structure; each group of structures includes a strip-shaped detection polycrystalline silicon structure parallel to the strip-shaped gate polycrystalline silicon structure, the strip-shaped detection polycrystalline silicon structure extending through all the strip-shaped monocrystalline silicon structures in the group, and the gate contact via is located between the strip-shaped gate polycrystalline silicon structure and the strip-shaped detection polycrystalline silicon structure; each group of structures includes a plurality of strip-shaped metal structures spaced apart along a second direction, wherein each strip-shaped metal structure is connected to a second portion of the gate contact via layer at both ends along the second direction.
[0010] Optionally, in some embodiments of this application, the test module further includes: a test metal layer, comprising: a first test metal layer, connected to a gate contact via at one end of a second direction in one of the two sets of structures, wherein the connected gate contact via is the gate contact via furthest from the strip-shaped single-crystal silicon structure integrally connected in the two sets of structures; the first test metal layer extends outward from the connected gate contact via along a first direction towards the outside of the simulation module; a second test metal layer, connected to a gate contact via at one end of a second direction in the other of the two sets of structures, wherein the connected gate contact via is the gate contact via furthest from the strip-shaped single-crystal silicon structure integrally connected in the two sets of structures; the second test metal layer extends outward from the connected gate contact via along a direction opposite to that of the first test metal layer towards the outside of the simulation module; the end of the first test metal layer furthest from the simulation module serves as a first test port; the end of the second test metal layer furthest from the simulation module serves as a second test port.
[0011] Optionally, in some embodiments of this application, the test module further includes: a test extension portion extending from the self-detecting polysilicon layer outward along the second direction; the test metal layer further includes: a leakage current test metal layer extending along the first direction, the leakage current test metal layer being connected to the test extension portion; the end of the leakage current test metal layer away from the test extension portion is used as a leakage current test port.
[0012] Optionally, in some embodiments of this application, the test extension portions of the detection polysilicon layer in the two sets of structures extending outward along the second direction to the outside of the analog module extend in opposite directions; the test metal layer further includes a third test metal layer and a fourth test metal layer; the leakage current test port includes a third test port and a fourth test port; the third test metal layer and the fourth test metal layer extend along the first direction and are connected to the test extension portions extending in opposite directions in the two sets of structures at opposite positions in the second direction, with the end of the third test metal layer away from the test extension portion serving as the third test port, and the end of the fourth test metal layer away from the test extension portion serving as the fourth test port.
[0013] Optionally, in some embodiments of this application, when the SRAM contact hole test verification structure has multiple simulation modules and test modules, the simulation modules are connected end-to-end through a first test metal layer and a second test metal layer; the unoccupied end of the first test metal layer away from the simulation module is used as the first test port of the overall structure, and the unoccupied end of the second test metal layer away from the simulation module is used as the second test port of the overall structure; the test extension of the strip-shaped polysilicon layer of each test module extending along the second direction is connected to the same third test metal layer or the same fourth test metal layer.
[0014] Optionally, in some embodiments of this application, the SRAM contact hole test verification structure further includes: a first oxide layer, which covers the gate polysilicon layer and the detection polysilicon layer, making it insulated from the single-crystal silicon layer; a gate contact via is located on the side and top of the first oxide layer; the portion covering the gate polysilicon layer has a first opening at the top of the gate polysilicon layer, and the gate contact via fills the first opening and connects to the gate polysilicon layer to form electrical conduction; the first oxide layer has a second opening on the portion of the single-crystal silicon layer between the gate polysilicon layer and the detection polysilicon layer, and the gate contact via fills the second opening and connects to the single-crystal silicon layer to form electrical conduction.
[0015] Optionally, in some embodiments of this application, the SRAM contact hole test verification structure further includes: a passivation protection layer, the passivation protection layer covering the first oxide layer, the passivation protection layer having a third opening at the position corresponding to the first opening, and the gate contact via filling the third opening.
[0016] Optionally, in some embodiments of this application, the SRAM contact hole test verification structure further includes: a second oxide layer, a passivation protection layer, and a space surrounding the filling gate contact via layer and the metal layer. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 A schematic diagram of the gate contact via structure in an SRAM design layout;
[0019] Figure 2 for Figure 1 A schematic diagram of the gate contact via offset in the first direction in an SRAM design layout;
[0020] Figure 3 This is a top view schematic diagram of an SRAM contact hole test verification structure according to an embodiment of this application;
[0021] Figure 4a for Figure 3 A schematic diagram showing the state where the gate contact via at the center circle has no offset;
[0022] Figure 4b for Figure 3 A schematic diagram showing the state in which the gate contact via at the center circle generates a positive offset in the first direction;
[0023] Figure 4c for Figure 3 A schematic diagram showing the state of negative offset in the first direction generated by the gate contact via at the middle circle;
[0024] Figure 5 This is a top view of a test verification structure for an SRAM contact hole according to another embodiment of this application. Detailed Implementation
[0025] This application provides an SRAM contact hole test verification structure to address the issue of how to verify whether the offset of the conductive via leads to an open circuit in the gate connection and leakage on the other side when the metal layer structure of the SRAM conductive via connection is relatively dense.
[0026] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the description of this application, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0027] Example
[0028] This embodiment provides an SRAM contact hole test and verification structure for testing and verifying whether the offset of the gate contact via leads to an open circuit in the gate connection and leakage on the other side when the metal layer structure of the SRAM gate contact via connection is relatively dense; Reference Figure 3 ,include:
[0029] Simulation module and test module integrated with it;
[0030] The simulation module includes:
[0031] Single-crystal silicon layer AA;
[0032] Gate polysilicon layer Poly1 (corresponding) Figure 1 Figure 2 The Poly layer (near the edge of the Share CT) is located on the monocrystalline silicon layer AA.
[0033] The gate contact via layer includes several gate contact vias CT, which connect the top of the gate polysilicon layer Poly1 and the monocrystalline silicon layer AA exposed on the side of the gate polysilicon layer Poly1.
[0034] Detection of polysilicon layer Poly2 (corresponding) Figure 1 Figure 2The Poly layer next to the central region of the Share CT is arranged parallel to the gate polysilicon layer Poly1, and the gate contact via layer is located between the detection polysilicon layer Poly2 and the gate polysilicon layer Poly1.
[0035] Metal layer M0 is located above the gate contact via layer and is connected to the gate contact via CT.
[0036] The test module includes: a first test port a extending from the metal layer M0 to the outside of the simulation module, and a second test port b positioned opposite to the first test port a;
[0037] The connection path between the first test port a and the second test port b passes through the entire monocrystalline silicon layer AA, the gate polycrystalline silicon layer Poly1, and the gate contact via layer.
[0038] Leakage current test port extending from the self-detecting polysilicon layer Poly2 to the outside of the analog module;
[0039] One of the first test port a and the second test port b is suitable for energizing the analog module, and the other is suitable for testing whether it is conducting; the leakage current test port is suitable for testing whether there is leakage.
[0040] It should be noted that, Figure 3 The area corresponding to the dashed box in the middle Figure 1 , Figure 2 The structure. Figure 3 This is a top view schematic diagram of an SRAM contact hole test verification structure according to an embodiment of this application. The statement above that the gate polysilicon layer Poly1 is located on the single-crystal silicon layer AA refers to the stacked arrangement of the structures, with the gate polysilicon layer Poly1 located vertically above the single-crystal silicon layer AA, not... Figure 3 The phrase "above" in this context refers to the metal layer being located above the gate contact via layer. Similarly, "the metal layer is located above the gate contact via layer" also refers to the stacked arrangement of the structures; the metal layer M0 is located vertically above the gate contact via layer, not... Figure 3 "Above" in the text.
[0041] The SRAM contact hole test and verification structure provided in this embodiment simulates the designed SRAM layout structure using a simulation module. A first test port a extending from the metal layer M0 to the outside of the simulation module, and a second test port b positioned opposite to the first test port a, allow power to be supplied to the simulation module via one of these ports. A connected test instrument then tests whether there is continuity between the first test port a and the second test port b. Since the connection path includes the entire monocrystalline silicon layer AA, the gate polycrystalline silicon layer Poly1, and the gate contact via layer, the continuity between the first test port a and the second test port b verifies whether an open circuit occurs between the gate contact via CT and the gate monocrystalline silicon layer AA. A leakage current test port led out from the detection polycrystalline silicon layer Poly2 on the side of the gate contact via CT can test whether leakage current occurs between the side of the gate contact via CT and the corresponding detection polycrystalline silicon layer Poly2. Therefore, using the SRAM contact hole test and verification structure provided in this application, by designing the gate connection via with an offset size, it is possible to verify whether the gate connection via is open-circuited and whether leakage occurs under this offset size. Furthermore, by providing multiple SRAM contact holes to test and verify the structure, and setting them to different offset sizes, it is possible to verify whether there is an open circuit and whether leakage occurs under multiple offset sizes. Ultimately, the limit size that the design can be offset can be obtained, thereby assisting in adjusting the design size.
[0042] For example, multiple SRAM contact hole test and verification structures are provided in this embodiment, and the displacement of the gate contact via CT in the first direction X is set according to different dimensions as follows: Figure 4a No offset in Figure 4b Positive offsets and negative offsets such as 4c (in the text) Figure 4a , Figure 4b , Figure 4c For the corresponding Figure 3 The schematic diagram at the center circle shows the positional relationship between the metal layer M0, the gate contact via CT, and the gate polysilicon layer Poly1. Furthermore, different sizes can be set in different offset directions to verify all SRAM contact hole test and verification structures. This reveals the limits within which offset can cause open circuits and leakage, thus aiding in adjusting the design dimensions. It is important to note that multiple SRAM contact hole test and verification structures are set to different sizes, while all gate contact vias CT in each of these SRAM contact hole test and verification structures have the same size.
[0043] Furthermore, in some embodiments of this application, the SRAM contact hole test verification structure includes multiple simulation modules and corresponding test modules; the simulation modules are connected end-to-end via a first test port and a second test port; the unused first test port is used as the first test port of the overall structure, and the unused second test port is used as the second test port of the overall structure; all test modules share the same leakage current test port. For example, as... Figure 5 As shown, it can be configured with two simulation modules and two corresponding test modules. By setting up multiple simulation and test modules, the leakage current signal can be amplified, thereby obtaining more refined verification test results.
[0044] Furthermore, in some embodiments of this application, the test module includes two sets of structures with mirrored configurations;
[0045] Each group of structures includes several strip-shaped single-crystal silicon structures that extend along the first direction X and are arranged in parallel along the second direction Y. The strip-shaped single-crystal silicon structures in the two groups of structures are arranged in a one-to-one correspondence. The strip-shaped single-crystal silicon structures at the end of one side along the second direction Y in the two groups of structures are connected into one unit.
[0046] The second direction Y is perpendicular to the first direction X;
[0047] Each group of structures includes several strip gate polysilicon structures spaced apart along the second direction Y, wherein each strip gate polysilicon structure has its two ends located on a strip monocrystalline silicon structure along the second direction Y; the distance between adjacent strip gate polysilicon structures in the second direction Y is the distance between adjacent strip monocrystalline silicon structures in the second direction Y.
[0048] Each structure includes several gate contact vias (CTs). Each gate contact via (CT) includes a first part located on the strip-shaped monocrystalline silicon and on the side of the gate polycrystalline silicon, and a second part spanning the top of the gate polycrystalline silicon and the top of the first part. The second part is connected to the first part as a whole, the second part is connected to the strip-shaped gate polycrystalline silicon structure, and the first part is connected to the strip-shaped monocrystalline silicon structure.
[0049] Each group of structures includes a strip detection polysilicon structure parallel to the strip gate polysilicon structure. The strip detection polysilicon structure extends through all the strip monocrystalline silicon structures in the group. The gate contact via (CT) is located between the strip gate polysilicon structure and the strip detection polysilicon structure.
[0050] Each group of structures includes several strip metal structures spaced apart along the second direction Y, wherein each strip metal structure is connected to a second part of a gate contact via layer at both ends along the second direction Y.
[0051] In conventional SRAM device design, the portion of the detection polysilicon structure located on the strip-shaped single-crystal silicon structure is arranged side-by-side with the gate polysilicon on the same strip-shaped single-crystal silicon structure, serving as the first gate structure, to form the second gate structure. Due to precision issues, significant misalignment can occur in the photolithographic overlay of the gate contact via (CT), causing the CT to easily slip in the second gate structure (i.e.,...). Figure 2 Leakage occurs at position B in the middle. Therefore, in the simulation module of this embodiment, each second gate structure is connected and brought out as a detection polysilicon structure for leakage detection. This facilitates leakage current detection and allows for a direct understanding of leakage defects caused by the design.
[0052] Specifically, in some embodiments of this application, the testing module further includes: testing the metal layer, including:
[0053] The first test metal layer M1 is connected to the gate contact via CT at one end of the second direction Y of one of the two sets of structures, and the connected gate contact via CT is the gate contact via CT farthest from the strip-shaped single crystal silicon structure that is connected as a whole in the two sets of structures; the first test metal layer M1 extends from the connected gate contact via CT along the first direction X towards the outside of the analog module.
[0054] The second test metal layer M2 is connected to the gate contact via CT at the end of one side of the second direction Y of the other group of the two structures, and the connected gate contact via CT is the gate contact via CT farthest from the strip-shaped single crystal silicon structure that is connected as a whole in the two groups of structures; the second test metal layer M2 extends from the connected gate contact via CT in the opposite direction to the first test metal layer M1 to simulate the outside of the module.
[0055] The end of the first test metal layer M1 furthest from the analog module is designated as the first test port a; the end of the second test metal layer M2 furthest from the analog module is designated as the second test port b.
[0056] Furthermore, in some embodiments of this application, the test module further includes: a test extension portion extending from the self-detecting polysilicon layer Poly2 along the second direction Y to the outside of the simulation module; the test metal layer further includes: a leakage current test metal layer extending along the first direction X, the leakage current test metal layer being connected to the test extension portion; the end of the leakage current test metal layer away from the test extension portion serves as a leakage current test port.
[0057] Specifically, in some embodiments of this application, the test extension portions of the detection polysilicon layer Poly2 in the two sets of structures that extend outward along the second direction Y toward the outside of the simulation module extend in opposite directions;
[0058] The test metal layer also includes a third test metal layer M3 and a fourth test metal layer M4; the leakage current test port includes a third test port c and a fourth test port d;
[0059] The third test metal layer M3 and the fourth test metal layer M4 extend along the first direction X and are connected to the test extensions extending in opposite directions in the two sets of structures at opposite positions in the second direction Y. The end of the third test metal layer M3 away from the test extension is the third test port c, and the end of the fourth test metal layer M4 away from the test extension is the fourth test port d.
[0060] Because the gate contact via CT has positive and negative biases in the first direction X ( Figure 3 The system has two detection ports (left and right) for detecting leakage current. The third test port (c) and the fourth test port (d) can detect leakage current to the right and left respectively. For example, as the rightward offset increases, the leakage current at the third test port (c) increases while the leakage current at the fourth test port (d) decreases. Normal leakage current is very small, so two detection ports are used to make it easier to detect increases in leakage current.
[0061] Furthermore, in some embodiments of this application, when the SRAM contact hole test verification structure has multiple simulation modules and test modules, the simulation modules are connected end-to-end through the first test metal layer M1 and the second test metal layer M2; the unoccupied end of the first test metal layer M1 away from the simulation module is used as the first test port of the overall structure, and the unoccupied end of the second test metal layer M2 away from the simulation module is used as the second test port of the overall structure; the test extension of the strip detection polysilicon structure layer Poly2 extending along the second direction Y of each test module is connected to the same third test metal layer M3 or the same fourth test metal layer M4.
[0062] Furthermore, in some embodiments of this application, the SRAM contact hole test verification structure further includes: a first oxide layer, which covers the gate polysilicon layer Poly1 and the detection polysilicon layer Poly2, making them insulated from the single-crystal silicon layer AA; a gate contact via CT located on the side and top of the first oxide layer; a portion covering the gate polysilicon layer Poly1 having a first opening at the top of the gate polysilicon layer Poly1, the gate contact via CT filling the first opening and connecting with the gate polysilicon layer Poly1 to form electrical conduction; and a second opening provided in the portion of the first oxide layer between the gate polysilicon layer Poly1 and the detection polysilicon layer Poly2 located on the surface of the single-crystal silicon layer AA, the gate contact via CT filling the second opening and connecting with the single-crystal silicon layer AA to form electrical conduction.
[0063] Furthermore, in some embodiments of this application, the SRAM contact hole test verification structure further includes: a passivation protection layer, the passivation protection layer covering the first oxide layer, the passivation protection layer having a third opening at the position corresponding to the first opening, and the gate contact via CT filling the third opening.
[0064] Furthermore, in some embodiments of this application, the SRAM contact hole test verification structure further includes: a second oxide layer, a passivation protection layer, and a space surrounding the gate contact via layer and the metal layer.
[0065] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A test and verification structure for SRAM contact holes, characterized in that, include: Simulation module and test module integrated with it; The simulation module includes: Single-crystal silicon layer; A gate polysilicon layer is located on the monocrystalline silicon layer; A gate contact via layer includes a plurality of gate contact vias connecting the top of the gate polysilicon and the monocrystalline silicon layer exposed on the side of the gate polysilicon layer; A detection polysilicon layer is disposed parallel to the gate polysilicon layer, and the gate contact via layer is located between the detection polysilicon layer and the gate polysilicon layer; A metal layer is located above the gate contact via layer and is connected to the gate contact via. The testing module includes: A first test port extends from the metal layer to the outside of the simulation module, and a second test port is located opposite to the first test port; the connection path between the first test port and the second test port passes through the entire single-crystal silicon layer, the gate polysilicon layer and the gate contact via layer; Leakage current test port extending from the detected polysilicon layer to the outside of the analog module; One of the first test port and the second test port is adapted to power on the analog module, and the other is adapted to test whether it is conducting; the leakage current test port is adapted to test whether there is leakage.
2. The SRAM contact hole test and verification structure according to claim 1, characterized in that, The SRAM contact hole test and verification structure includes multiple simulation modules and corresponding test modules; Each of the simulation modules is connected end to end through the first test port and the second test port; the unused first test port is used as the first test port of the overall structure, and the unused second test port is used as the second test port of the overall structure. All the test modules share the same leakage current test port.
3. The SRAM contact hole test and verification structure according to claim 1 or 2, characterized in that, The test module includes two sets of structures with mirror settings; Each group of structures includes several strip-shaped single-crystal silicon structures that extend along a first direction and are arranged in parallel along a second direction. The strip-shaped single-crystal silicon structures in the two groups of structures are arranged in a one-to-one correspondence. The strip-shaped single-crystal silicon structures at the end of one side along the second direction in the two groups of structures are connected into one piece. The second direction is perpendicular to the first direction. Each group of structures includes several strip gate polysilicon structures spaced apart along a second direction, wherein each strip gate polysilicon structure has its two ends located on a strip monocrystalline silicon structure along the second direction; the distance between adjacent strip gate polysilicon structures in the second direction is the distance between adjacent strip monocrystalline silicon structures in the second direction. Each structure includes several gate contact vias, each gate contact via including a first portion located on the strip-shaped monocrystalline silicon and on the side of the gate polycrystalline silicon, and a second portion spanning the top of the gate polycrystalline silicon and the top of the first portion; the second portion is integrated with the first portion, the second portion is connected to the strip-shaped gate polycrystalline silicon structure, and the first portion is connected to the strip-shaped monocrystalline silicon structure; Each group of structures includes a strip detection polysilicon structure parallel to the strip gate polysilicon structure, the strip detection polysilicon structure extending through all the strip monocrystalline silicon structures in the group, and the gate contact via located between the strip gate polysilicon structure and the strip detection polysilicon structure. Each group of structures includes several strip metal structures spaced apart along the second direction, wherein each strip metal structure is connected to a second portion of the gate contact via layer at both ends along the second direction.
4. The SRAM contact hole test and verification structure according to claim 3, characterized in that, The testing module also includes: Test the metal layer, including: The first test metal layer is connected to the gate contact via at one end of the second direction of one of the two sets of structures, and the connected gate contact via is the gate contact via farthest from the strip-shaped single-crystal silicon structure that is connected as a whole in the two sets of structures; the first test metal layer extends from the connected gate contact via along the first direction to the outside of the simulation module. The second test metal layer is connected to the gate contact via at one end of the second direction of the other of the two sets of structures, and the connected gate contact via is the gate contact via furthest from the strip-shaped single-crystal silicon structure that is connected as a whole in the two sets of structures; the second test metal layer extends from the connected gate contact via to the outside of the analog module in the opposite direction to the first test metal layer. The end of the first test metal layer furthest from the simulation module serves as the first test port; The end of the second test metal layer furthest from the simulation module serves as the second test port.
5. The SRAM contact hole test and verification structure according to claim 4, characterized in that, The testing module also includes: A test extension portion extending from the detected polysilicon layer along the second direction to the outside of the simulation module; The test metal layer also includes: A leakage current test metal layer extends along a first direction, and the leakage current test metal layer is connected to the test extension; the end of the leakage current test metal layer away from the test extension serves as the leakage current test port.
6. The SRAM contact hole test and verification structure according to claim 5, characterized in that, The test extension portions of the detection polysilicon layer in the two sets of structures that extend outward from the simulation module along the second direction extend in opposite directions. The test metal layer also includes a third test metal layer and a fourth test metal layer; The leakage current test port includes a third test port and a fourth test port; The third test metal layer and the fourth test metal layer extend along the first direction and are connected to the test extensions extending in opposite directions in the two sets of structures at opposite positions in the second direction. The end of the third test metal layer away from the test extension is the third test port, and the end of the fourth test metal layer away from the test extension is the fourth test port.
7. The SRAM contact hole test and verification structure according to claim 6, characterized in that, When the SRAM contact hole test verification structure has multiple simulation modules and test modules, Each of the simulation modules is connected end to end through the first test metal layer and the second test metal layer; the unused end of the first test metal layer away from the simulation module is used as the first test port of the overall structure, and the unused end of the second test metal layer away from the simulation module is used as the second test port of the overall structure. The test extensions of the strip-shaped detection polycrystalline silicon structure layers of each test module extending along the second direction are connected to the same third test metal layer or the same fourth test metal layer.
8. The SRAM contact hole test and verification structure according to claim 1, characterized in that, Also includes: A first oxide layer covers the gate polysilicon layer and the detection polysilicon layer, making them insulated from the single-crystal silicon layer; The gate contact via is located on the side and top of the first oxide layer; the portion covering the gate polysilicon layer has a first opening on the top of the gate polysilicon layer, and the gate contact via fills the first opening and connects to the gate polysilicon layer to form electrical conduction; the first oxide layer has a second opening on the portion of the single crystal silicon layer between the gate polysilicon layer and the detection polysilicon layer, and the gate contact via fills the second opening and connects to the single crystal silicon layer to form electrical conduction.
9. The SRAM contact hole test and verification structure according to claim 8, characterized in that, Also includes: A passivation protection layer is provided, which covers the first oxide layer. The passivation protection layer has a third opening at the position corresponding to the first opening, and the gate contact via fills the third opening.
10. The SRAM contact hole test and verification structure according to claim 9, characterized in that, Also includes: The second oxide layer covers the passivation protection layer and surrounds the space outside the gate contact via layer and the metal layer.