Package structure and flash memory chip
By using 2.5D or 3D packaging technology, the bare crystal of flash memory and the bare crystal of memory controller are electrically connected to the packaging substrate through through silicon vias, which solves the problems of large packaging size and signal delay of traditional flash memory chips, and achieves high-density integration and performance improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- YEESTOR MICROELECTRONICS CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional flash memory chips have large package sizes and significant signal delays, which limit miniaturization design and overall performance improvement.
Using 2.5D or 3D packaging technology, the flash memory bare crystal and the memory controller bare crystal are electrically connected to the packaging substrate through through silicon vias, reducing signal path length and achieving high-density integration.
It reduces signal latency, supports high-density integration, and shrinks the size of the package structure, making it suitable for high-performance applications such as artificial intelligence and edge computing.
Smart Images
Figure CN224306187U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of packaging structure technology, and in particular to a packaging structure and a flash memory chip. Background Technology
[0002] With the development of semiconductor technology and storage systems, flash memory chips are playing an increasingly important role in high-performance applications such as artificial intelligence, edge computing, and embedded devices. Traditional flash memory chips typically use a 2D packaging method, in which the flash memory crystal and the memory controller crystal are respectively laid flat on a packaging substrate and electrically connected to external circuits through long bonding leads.
[0003] However, this traditional packaging method has the following problems: First, the package size is relatively large: multiple bare crystals are arranged side by side on the packaging substrate, occupying a large planar space, which is not conducive to miniaturization design. Moreover, the signal transmission between the bare crystal and the packaging substrate usually relies on bonding wires, and the metal wire paths can be several millimeters or even longer. Furthermore, these metal wires are located outside the bare crystal, occupying a large space. Second, the signal path is relatively long: the interconnection lines between chips need to be routed through the packaging substrate, which leads to increased signal delay and limits the improvement of overall performance. Utility Model Content
[0004] The main purpose of this invention is to propose a packaging structure and a flash memory chip, which aims to solve the technical problems of large package size and significant signal delay in existing flash memory chips.
[0005] To achieve the above objectives, this utility model proposes a packaging structure, comprising:
[0006] Encapsulation substrate;
[0007] Flash memory bare crystal;
[0008] The storage controller bare crystal and the flash memory bare crystal are integrated on the package substrate through 2.5D packaging or 3D packaging;
[0009] The flash memory bare crystal and the memory controller bare crystal are electrically connected to the package substrate through through-silicon vias.
[0010] In one embodiment, where the memory controller bare crystal and the flash memory bare crystal are integrated on the package substrate via 2.5D packaging, the package structure further includes:
[0011] A silicon interposer layer, on which the memory controller bare crystal and the flash memory bare crystal are horizontally arranged;
[0012] The silicon interposer has a redistribution layer, and the memory controller bare crystal and the flash memory bare crystal are electrically connected to the redistribution layer.
[0013] The silicon interposer has a plurality of through-silicon vias (TSVs), the redistribution layer is electrically connected to one end of the plurality of TSVs in the silicon interposer, and the encapsulation substrate is electrically connected to the other end of the plurality of TSVs in the silicon interposer.
[0014] In one embodiment, when the memory controller bare crystal and the flash memory bare crystal are integrated on the package substrate by 3D packaging, the flash memory bare crystal and the memory controller bare crystal are stacked.
[0015] The memory controller bare crystal and the flash memory bare crystal, which are attached to the packaging substrate, have a plurality of through-silicon vias (TSVs). One end of the TSV is electrically connected to the other of the memory controller bare crystal and the flash memory bare crystal, and the other end of the TSV is electrically connected to the packaging substrate.
[0016] In one embodiment, the packaging structure further includes:
[0017] The SOC bare crystal, the memory controller bare crystal, and the flash memory bare crystal are integrated on the package substrate through 2.5D packaging or 3D packaging;
[0018] The SOC bare crystal is electrically connected to the packaging substrate through a through-silicon via.
[0019] In one embodiment, when the memory controller bare crystal and the flash memory bare crystal are integrated on the package substrate by 2.5D packaging, the SOC bare crystal, the memory controller bare crystal and the flash memory bare crystal are horizontally arranged on the silicon interposer.
[0020] When the storage controller bare crystal and the flash memory bare crystal are integrated on the package substrate through 3D packaging, the SOC bare crystal, the flash memory bare crystal and the storage controller bare crystal are stacked.
[0021] In one embodiment, the number of flash memory bare crystals is multiple, and the multiple flash memory bare crystals are stacked.
[0022] The flash memory bare crystal has multiple through-silicon vias (TSVs), and the multiple TSVs of the flash memory bare crystal are electrically connected to the multiple TSVs of another adjacent flash memory bare crystal in a one-to-one correspondence.
[0023] In one embodiment, the packaging structure further includes:
[0024] A base bare crystal, wherein the base bare crystal is disposed between a plurality of vertically stacked flash memory bare crystals and the package substrate;
[0025] The base bare crystal integrates multiple through-silicon vias (TSVs) and physical layer interface circuits. One end of the multiple TSVs of the base bare crystal is electrically connected to multiple TSVs of one of the vertically stacked flash memory bare crystals located at the bottom layer. One end of the multiple TSVs of the base bare crystal is connected to one end of the physical layer interface circuit, and the other end of the physical layer interface circuit is electrically connected to the packaging substrate.
[0026] This utility model also proposes a flash memory chip, including a circuit board and the packaging structure described in any of the above claims; wherein the packaging structure is soldered onto the circuit board.
[0027] This utility model's packaging structure includes a packaging substrate; a flash memory bare crystal; and a memory controller bare crystal. The memory controller bare crystal and the flash memory bare crystal are integrated on the packaging substrate through 2.5D packaging or 3D packaging. The flash memory bare crystal and the memory controller bare crystal are electrically connected to the packaging substrate through through-silicon vias (TSVs). With this configuration, the TSVs are used to transmit signals or power to the bottom packaging substrate for connection to external circuitry. Compared to bonding wires, TSVs not only have shorter signal paths to reduce signal delay between the flash memory bare crystal and the memory controller bare crystal and external circuitry, but also support high-density integration of the flash memory bare crystal and the memory controller bare crystal. Compared to 2D packaging, which lays the chip flat on the substrate, this reduces the space required for packaging and the complexity of wiring. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of the structure of an embodiment of the present utility model;
[0030] Figure 2 This is a schematic diagram of another embodiment of the present invention;
[0031] Figure 3 This is a schematic diagram of another embodiment of the present invention;
[0032] Figure 4 This is a schematic diagram of the structure of another embodiment of the present utility model;
[0033] Figure 5 This is a schematic diagram of another embodiment of the present invention;
[0034] Figure 6This is a schematic diagram of another embodiment of the present invention;
[0035] Figure 7 This is a schematic diagram of another embodiment of the present invention.
[0036] Explanation of icon numbers:
[0037] 10. Packaging substrate; 20. Flash memory bare crystal; 30. Memory controller bare crystal; 40. Through-silicon via (TSV); 50. Silicon interposer; 60. Microbump; 70. Circuit board; 80. System-on-a-Chip (SoC) bare crystal; 90. Base bare crystal; 100. Physical layer interface circuit.
[0038] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0039] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present utility model.
[0040] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.
[0041] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.
[0042] With the development of semiconductor technology and storage systems, flash memory chips are playing an increasingly important role in high-performance applications such as artificial intelligence, edge computing, and embedded devices. Traditional flash memory chips typically use a 2D packaging method, in which the flash memory crystal and the memory controller crystal are respectively laid flat on a packaging substrate and electrically connected by long bonding wires.
[0043] However, this traditional packaging method has the following problems: First, the package size is large: multiple bare crystals are arranged side by side on the packaging substrate, which occupies a large planar space and is not conducive to miniaturization design; Second, the signal path is long: the interconnection lines between chips need to be routed through the packaging substrate, which leads to increased signal delay and limits the improvement of overall performance.
[0044] Therefore, the main objective of this invention is to propose a packaging structure and a flash memory chip, aiming to solve the technical problems of large package size and significant signal delay in existing flash memory chips. In one embodiment of this invention, the packaging structure includes:
[0045] Encapsulation substrate 10;
[0046] Flash memory bare crystal 20;
[0047] Storage controller bare crystal 30, the storage controller bare crystal 30 and the flash memory bare crystal 20 are integrated on the packaging substrate 10 through 2.5D packaging or 3D packaging;
[0048] The flash memory bare crystal 20 and the storage controller bare crystal 30 are electrically connected to the package substrate 10 through a through-silicon via 40.
[0049] In this embodiment, the package substrate 10 is a key structure for carrying the flash memory bare crystal 20 and the memory controller bare crystal 30 and realizing their electrical connection with external circuits. The package substrate 10 is soldered to the pads on the circuit board 70 by solder balls, so that the flash memory bare crystal 20 and the memory controller bare crystal 30 can establish communication connections with other circuits on the circuit board 70. The flash memory bare crystal 20 is the physical unit for storing data, and the memory controller bare crystal 30 is used to perform flash memory read and write, error correction, wear leveling and other functions on the flash memory bare crystal 20.
[0050] In one embodiment, reference Figure 1 When the storage controller bare crystal 30 and the flash memory bare crystal 20 are integrated on the package substrate 10 via 2.5D packaging, the package structure further includes:
[0051] A silicon interposer 50 is provided, on which the memory controller bare crystal 30 and the flash memory bare crystal 20 are horizontally arranged;
[0052] The silicon interposer 50 has a redistribution layer (not shown in the figure), and the memory controller bare crystal 30 and the flash memory bare crystal 20 are electrically connected to the redistribution layer;
[0053] The silicon interposer 50 has a plurality of through-silicon vias 40. The redistribution layer is electrically connected to one end of the plurality of through-silicon vias 40 of the silicon interposer 50, and the encapsulation substrate 10 is electrically connected to the other end of the plurality of through-silicon vias 40 of the silicon interposer 50.
[0054] In this embodiment, the silicon interposer 50 is a silicon substrate having a redistribution layer (RDL) and multiple through-silicon vias (TSVs) 40. The redistribution layer is a multilayer metal circuit deposited and patterned on the surface of the silicon interposer 50. It is electrically connected not only to the memory bare crystal and the flash memory bare crystal 20 to enable electrical interconnection between the memory controller bare crystal 30 and the flash memory bare crystal 20, but also to the through-silicon vias 40 of the silicon interposer 50 to enable the memory controller bare crystal 30 and the flash memory bare crystal 20 to transmit signals to the package substrate 10. The memory controller bare crystal 30 and the flash memory bare crystal 20 are electrically connected to the redistribution layer through microbumps 60.
[0055] Multiple through-silicon vias 40 vertically penetrate the silicon interposer 50. The redistribution layer is electrically connected to one end of the through-silicon via 40 in the silicon interposer 50, and the other end of the through-silicon via 40 in the silicon interposer 50 is electrically connected to the package substrate 10 through the microbumps 60. The through-silicon vias 40 in the silicon interposer 50 are used to provide communication connections between the flash memory bare crystal 20 and the memory controller bare crystal 30 and other circuits on the circuit board 70. That is, the access commands, addresses, data and other signals of the flash memory bare crystal 20 / memory controller bare crystal 30 are transmitted to the through-silicon via 40 through the redistribution layer of the silicon interposer 50, and then transmitted from the top of the package to the bottom of the package substrate 10 through the through-silicon via 40. Finally, they are connected to other circuits on the circuit board 70 through the solder ball array on the package substrate 10.
[0056] This configuration, compared to the metal wires of bonding leads, results in a through-silicon via (TSV) 40 with a path of only tens to hundreds of micrometers, which helps reduce signal delay. Furthermore, in 2.5D packaging, the TSV 40 is embedded within the silicon interposer 50 as a vertical conductive channel, rather than an external trace like a bonding lead, facilitating a high-density integrated packaging structure and reducing overall size. In addition, multiple TSVs 40 can be densely arranged on the silicon wafer of the silicon interposer 50, forming hundreds or thousands of vertical channels to support multi-channel parallel communication. Compared to 2D packaging structures, this is more suitable for performing data-intensive tasks such as HBM (High Bandwidth Memory) and AI model loading.
[0057] In another embodiment, reference Figure 2When the storage controller bare crystal 30 and the flash memory bare crystal 20 are integrated on the packaging substrate 10 through 3D packaging, the flash memory bare crystal 20 and the storage controller bare crystal 30 are stacked.
[0058] The storage controller bare crystal 30 and the flash memory bare crystal 20, which are attached to the packaging substrate 10, have a plurality of through silicon vias 40. One end of the through silicon via 40 is electrically connected to the other of the storage controller bare crystal 30 and the flash memory bare crystal 20, and the other end of the through silicon via 40 is electrically connected to the packaging substrate 10.
[0059] In this embodiment, a through-silicon via 40 vertically penetrates one of the memory controller bare crystal 30 or the flash memory bare crystal 20 closest to the package substrate 10, allowing the other to be stacked on top of it. This achieves vertical stacking of the memory controller bare crystal 30 and the flash memory bare crystal 20, reducing the overall volume of the package structure compared to multiple bare crystals laid flat on the package substrate in 2D packaging. One of the memory controller bare crystal 30 or the flash memory bare crystal 20 is electrically connected to the other's through-silicon via 40 via a microbump 60.
[0060] In 3D packaging, through-silicon vias (TSVs) 40 not only provide electrical connections between the memory controller bare crystal 30 and the flash memory bare crystal 20 and the package substrate 10 to establish communication connections with external circuits, but also facilitate communication between the memory controller bare crystal 30 and the flash memory bare crystal 20. Compared to the metal wires of bonding leads, the path of the TSV 40 is only tens to hundreds of micrometers, which helps reduce signal latency. Furthermore, in 3D packaging, the TSV 40 is embedded inside the bare crystal instead of being an external trace like a bonding lead, which is beneficial for achieving a high-density integrated package structure and reducing the overall size. In addition, multiple TSVs 40 can be densely arranged inside the bare crystal to form hundreds or thousands of vertical channels to support multi-channel parallel communication. Compared to 2D packaging structures, this is more suitable for performing data-intensive tasks such as HBM (High Bandwidth Memory) and AI model loading.
[0061] This utility model's packaging structure includes a packaging substrate 10; a flash memory bare crystal 20; and a memory controller bare crystal 30. The memory controller bare crystal 30 and the flash memory bare crystal 20 are integrated on the packaging substrate 10 through 2.5D packaging or 3D packaging. The flash memory bare crystal 20 and the memory controller bare crystal 30 are electrically connected to the packaging substrate 10 through through-silicon vias (TSVs) 40. With this configuration, the TSVs 40 are used to transmit signals or power to the bottom packaging substrate for connection to external circuits. Compared to bonding wires, the TSVs 40 not only have shorter signal paths to reduce signal delay between the flash memory bare crystal 20 and the memory controller bare crystal 30 and external circuits, but also support high-density integration of the flash memory bare crystal 20 and the memory controller bare crystal 30. Compared to 2D packaging, which lays the chip flat on the substrate, this reduces the space required for packaging and the complexity of wiring.
[0062] In one embodiment of this utility model, reference is made to Figure 3-4 The packaging structure further includes:
[0063] SOC bare crystal 80, the storage controller bare crystal 30 and the flash memory bare crystal 20 are integrated on the package substrate 10 through 2.5D packaging or 3D packaging;
[0064] The SOC bare crystal 80 is electrically connected to the packaging substrate 10 through a through-silicon via 40.
[0065] In this embodiment, the SOC bare crystal 80 is used to send control commands and data streams to the storage master bare crystal 30 to control the storage master bare crystal 30 to perform flash memory read / write, error correction, and management operations on the flash memory bare crystal 20. This invention integrates the SOC bare crystal 80, the storage master bare crystal 30, and the flash memory bare crystal 20 into the same package structure to form an independently operating local processing unit. This unit can be directly used as a processor in electronic devices, such as an image recognition module in a smart camera, a voice recognition engine in a wearable device, and a model execution unit in an industrial vision inspection system, thereby reducing dependence on external hardware and improving deployment flexibility.
[0066] refer to Figure 3 When the memory controller bare crystal 30 and the flash memory bare crystal 20 are integrated on the package substrate 10 through 2.5D packaging, the package structure includes a silicon interposer 50, and the SOC bare crystal 80, the memory controller bare crystal 30, and the flash memory bare crystal 20 are horizontally arranged on the silicon interposer 50. The SOC bare crystal 80, the memory controller bare crystal 30, and the flash memory bare crystal 20 are electrically connected to the redistribution layer on the silicon interposer 50 through microbumps 60, enabling communication between them.
[0067] refer to Figure 4 When the memory controller bare crystal 30 and the flash memory bare crystal 20 are integrated onto the packaging substrate 10 via 3D packaging, the SOC bare crystal 80, the flash memory bare crystal 20, and the memory controller bare crystal 30 are stacked. Specifically, the SOC bare crystal 80, the memory controller bare crystal 30, and the flash memory bare crystal 20 are stacked sequentially on the packaging substrate 10, with multiple through-silicon vias 40 penetrating within the memory controller bare crystal 30 and the flash memory bare crystal 20, and electrically interconnected via microbumps 60, enabling communication between the SOC bare crystal 80, the memory controller bare crystal 30, and the flash memory bare crystal 20, as well as communication with external circuits.
[0068] In one embodiment of this utility model, reference is made to Figure 5The number of the flash memory bare crystals 20 is multiple, and the multiple flash memory bare crystals 20 are stacked.
[0069] The flash memory bare crystal 20 has a plurality of through silicon vias 40, and the plurality of through silicon vias 40 of the flash memory bare crystal 20 are electrically connected to the plurality of through silicon vias 40 of another adjacent flash memory bare crystal 20 in a one-to-one correspondence.
[0070] In this embodiment, except for the top-mounted flash memory bare crystal 20, each of the remaining flash memory bare crystals 20 has multiple through-silicon vias (TSVs) 40. One TSV 40 of a flash memory bare crystal 20 is electrically connected to the TSV 40 of an adjacent flash memory bare crystal 20 via a microbump 60. The TSVs 40 of the multiple flash memory bare crystals 20 form a "vertical channel array," supporting parallel access. This allows the storage controller bare crystal 30 to simultaneously read data from different flash memory bare crystals 20, thereby improving the overall execution speed. Compared to the traditional 2D tiling method, the vertically stacked structure can integrate a larger capacity per unit area, which is beneficial for miniaturizing the package structure.
[0071] Furthermore, considering that when the flash memory bare crystals 20 are vertically stacked through the through-silicon vias 40, the signal needs to be transmitted over a long distance to the memory controller bare crystal 30 or the package substrate 10. Therefore, in one embodiment, reference is made to... Figure 6-7 The packaging structure further includes:
[0072] A base bare crystal 90 is disposed between a plurality of vertically stacked flash memory bare crystals 20 and the package substrate 10;
[0073] The base bare crystal 90 integrates multiple through-silicon vias 40 and a physical layer interface circuit 100. One end of the multiple through-silicon vias 40 of the base bare crystal 90 is electrically connected to multiple through-silicon vias 40 of one of the multiple vertically stacked flash memory bare crystals 20 located at the bottom layer. One end of the multiple through-silicon vias 40 of the base bare crystal 90 is connected to one end of the physical layer interface circuit 100, and the other end of the physical layer interface circuit 100 is electrically connected to the package substrate 10.
[0074] In this embodiment, the base bare crystal 90 is not only used to provide physical support for the stack of upper multilayer flash bare crystals 20 and alleviate packaging stress, but also to serve as a carrier for the physical layer interface circuit 100 to electrically connect with the flash bare crystal 20 located at the bottom layer, so that the physical layer interface circuit 100 can redrive or restore the clock of uplink and downlink signals to compensate for the signal attenuation of the through silicon via 40 and long-distance interconnect.
[0075] It should be noted that the flash memory bare crystal 20 and the memory controller bare crystal 30 are integrated on the package substrate 10 through 2.5D packaging. The basic bare crystal 90 is disposed between the multiple vertically stacked flash memory bare crystals 20 and the silicon interposer 50, so as to be electrically connected to the package substrate 10 through the silicon interposer 50.
[0076] This invention also proposes a flash memory chip, including a circuit board 70 and a packaging structure as described above.
[0077] It is worth noting that since the flash memory chip of this utility model is based on the above-described packaging structure, the embodiments of the flash memory chip of this utility model include all the technical solutions of all embodiments of the above-described packaging structure, and the technical effects achieved are exactly the same, so they will not be repeated here.
[0078] The above description is merely an exemplary embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural transformations made based on the technical concept of the present utility model and the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.
Claims
1. A packaging structure, characterized in that, include: Encapsulation substrate; Flash memory bare crystal; The storage controller bare crystal and the flash memory bare crystal are integrated on the package substrate through 2.5D packaging or 3D packaging; The flash memory bare crystal and the memory controller bare crystal are electrically connected to the package substrate through through-silicon vias.
2. The packaging structure as described in claim 1, characterized in that, When the memory controller bare crystal and the flash memory bare crystal are integrated on the package substrate via 2.5D packaging, the package structure further includes: A silicon interposer layer, on which the memory controller bare crystal and the flash memory bare crystal are horizontally arranged; The silicon interposer has a redistribution layer, and the memory controller bare crystal and the flash memory bare crystal are electrically connected to the redistribution layer. The silicon interposer has a plurality of through-silicon vias (TSVs), the redistribution layer is electrically connected to one end of the plurality of TSVs in the silicon interposer, and the encapsulation substrate is electrically connected to the other end of the plurality of TSVs in the silicon interposer.
3. The packaging structure as described in claim 1, characterized in that, When the memory controller bare crystal and the flash memory bare crystal are integrated on the packaging substrate through 3D packaging, the flash memory bare crystal and the memory controller bare crystal are stacked. The memory controller bare crystal and the flash memory bare crystal, which are attached to the packaging substrate, have a plurality of through-silicon vias (TSVs). One end of the TSV is electrically connected to the other of the memory controller bare crystal and the flash memory bare crystal, and the other end of the TSV is electrically connected to the packaging substrate.
4. The packaging structure according to any one of claims 1 to 3, characterized in that, The packaging structure further includes: The SOC bare crystal, the memory controller bare crystal, and the flash memory bare crystal are integrated on the package substrate through 2.5D packaging or 3D packaging; The SOC bare crystal is electrically connected to the packaging substrate through a through-silicon via.
5. The packaging structure as described in claim 4, characterized in that, When the memory controller bare crystal and the flash memory bare crystal are integrated on the package substrate via 2.5D packaging, the package structure further includes: A silicon interposer layer, on which the memory controller bare crystal and the flash memory bare crystal are horizontally arranged; The silicon interposer has a redistribution layer, and the memory controller bare crystal and the flash memory bare crystal are electrically connected to the redistribution layer. The silicon interposer has a plurality of through-silicon vias, the redistribution layer is electrically connected to one end of the plurality of through-silicon vias of the silicon interposer, and the encapsulation substrate is electrically connected to the other end of the plurality of through-silicon vias of the silicon interposer; The SOC bare crystal, the memory controller bare crystal, and the flash memory bare crystal are horizontally arranged on the silicon interposer; When the storage controller bare crystal and the flash memory bare crystal are integrated on the package substrate through 3D packaging, the SOC bare crystal, the flash memory bare crystal and the storage controller bare crystal are stacked.
6. The packaging structure as described in any one of claims 1 to 3, characterized in that, The number of bare flash memory crystals is multiple, and the multiple bare flash memory crystals are stacked together. The flash memory bare crystal has multiple through-silicon vias (TSVs), and the multiple TSVs of the flash memory bare crystal are electrically connected to the multiple TSVs of another adjacent flash memory bare crystal in a one-to-one correspondence.
7. The packaging structure as described in claim 6, characterized in that, The packaging structure further includes: A base bare crystal, wherein the base bare crystal is disposed between a plurality of vertically stacked flash memory bare crystals and the package substrate; The base bare crystal integrates multiple through-silicon vias (TSVs) and physical layer interface circuits. One end of the multiple TSVs of the base bare crystal is electrically connected to multiple TSVs of one of the vertically stacked flash memory bare crystals located at the bottom layer. One end of the multiple TSVs of the base bare crystal is connected to one end of the physical layer interface circuit, and the other end of the physical layer interface circuit is electrically connected to the packaging substrate.
8. A flash memory chip, characterized in that, It includes a circuit board and a packaging structure as described in any one of claims 1 to 7; wherein the packaging structure is soldered onto the circuit board.