A watchdog-based system online upgrade circuit

Abstract

The utility model relates to a kind of system online upgrading circuit based on watchdog, including watchdog control module, latch and system module, the first GPIO port and the second GPIO port of the system module connect the first input end and the second input end of the latch, the output end of the latch connects the watchdog control module, for controlling the working condition of watchdog control module;The output end of the watchdog control module connects the reset signal input end of system module, the system module resets operation when receiving the reset signal of the watchdog output end.It is avoided that the system reset problem caused by failing to feed dog in time by controlling the output signal of watchdog, ensure the smooth completion of software upgrade;By latch and logic gate circuit design, whether watchdog has enable end or not, or how is the level state of system module reset signal effective, can effectively realize the online upgrade of system.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, specifically to a system online upgrade circuit based on a watchdog timer. Background Technology

[0002] Watchdog circuits are widely used in modern electronic systems. Their main function is to restart the system chip by sending a reset signal when the system software malfunctions or crashes, thereby restoring normal system operation. However, this protection mechanism can also present challenges in certain situations, especially during online software upgrades. During online software upgrades, the periodic "watchdog feeding" may be temporarily suspended due to the need to update software components in the system. If the watchdog is not properly fed during this period, it will trigger a reset signal, causing the system to reset and interrupting the ongoing software upgrade process, resulting in upgrade failure. Utility Model Content

[0003] To address the aforementioned problems, this utility model provides a watchdog-based online system upgrade circuit, comprising a watchdog control module, a latch, and a system module. The first GPIO port and the second GPIO port of the system module are connected to the first input terminal and the second input terminal of the latch. The output terminal of the latch is connected to the watchdog control module for controlling the working state of the watchdog control module. The output terminal of the watchdog control module is connected to the reset signal input terminal of the system module, and the system module performs a reset operation when it receives the reset signal from the watchdog output terminal.

[0004] Based on the above scheme, the watchdog control module includes a watchdog, the watchdog includes an enable terminal, the output terminal of the latch is connected to the enable terminal of the watchdog, and the output terminal of the watchdog is connected to the reset signal input terminal of the system module.

[0005] Based on the above scheme, a shorting pin is also included, with one end of the shorting pin connected to VCC and the other end connected to the enable pin of the watchdog timer.

[0006] Preferably, the watchdog control module includes a watchdog timer and a logic gate. The output of the watchdog timer is connected to the first input of the logic gate, the output of the latch is connected to the second input of the logic gate, and the output of the logic gate is connected to the reset signal input of the system module.

[0007] Based on the above scheme, the logic gate is a logic OR gate, the output terminal of the watchdog is connected to the first input terminal of the logic OR gate, the output terminal of the logic OR gate is connected to the reset signal input terminal of the system module, and the system module is reset when the reset signal input of the system module is low.

[0008] Based on the above scheme, a shorting pin is also included. One end of the shorting pin is connected to VCC, and the other end has two paths: one is connected to GND, and the other is connected to the second input terminal of the logic OR gate.

[0009] Preferably, the logic gate is an AND gate, the output of the watchdog timer is connected to the first input of the AND gate, the output of the AND gate is connected to the reset signal input of the system module, and the system module is reset when the reset signal input of the system module is high.

[0010] Based on the above scheme, a shorting pin is also included. One end of the shorting pin is connected to GND, and the other end has two paths: one is connected to VCC, and the other is connected to the second input terminal of the logic AND gate.

[0011] Based on the above scheme, the output terminal of the latch is connected to the second input terminal of the logic gate via a first resistor, and the second input terminal of the logic gate is also connected to GND or VCC via a second resistor.

[0012] Compared with the prior art, the beneficial effects of this utility model are as follows: by controlling the output signal of the watchdog, the system reset problem caused by failure to feed the watchdog in time is avoided, ensuring the smooth completion of software upgrade; through the design of latch and logic gate circuit, the online upgrade of the system can be effectively realized regardless of whether the watchdog has an enable terminal or the effective level state of the system module reset signal. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the circuit module of this application;

[0014] Figure 2 A schematic diagram of a watchdog timer circuit with an enable pin.

[0015] Figure 3 A circuit diagram showing the watchdog timer with no enable pin (system low-level reset);

[0016] Figure 4 A circuit diagram showing the watchdog timer with no enable pin (system high-level reset). Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings:

[0018] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0019] This application provides a watchdog-based online upgrade circuit to solve the problem in the prior art where the watchdog is falsely triggered and reset due to the inability to send a "feed" signal during software upgrades. Figure 1 As shown, the system module periodically sends a signal to the watchdog control module input to indicate that the system is operating normally. If the system module fails to send a signal within a specified time, the watchdog control module will trigger a system reset. To avoid unnecessary resets, the watchdog control module receives signals from the latch or shorting pins to control the status of the signal output to the system reset terminal.

[0020] The latch receives GPIO signals from the system module and adjusts the output level to the watchdog control module based on these inputs, allowing the system to temporarily disable the watchdog function.

[0021] The shorting pin provides a hardware method to directly control the state of the watchdog timer. When the shorting cap is inserted, the signal received by the watchdog control module can be changed directly, thereby temporarily disabling the watchdog function.

[0022] Example 1:

[0023] like Figure 2 As shown, this embodiment provides a system online upgrade circuit for use when the watchdog has an enable terminal, including a latch U1, a watchdog control module and a system module S1, wherein the watchdog control module includes a watchdog U2.

[0024] The third GPIO port of the system module is connected to the watchdog timer's input terminal WDI, and the watchdog timer's output terminal WDO is connected to the system module's reset signal input terminal RST. The third GPIO port outputs a signal to WDI. When the watchdog timer does not receive the WDI signal within a certain period of time, WDO outputs a reset signal to the system module's RST.

[0025] The first GPIO port GPIO1 and the second GPIO port GPIO2 of the system module are respectively connected to the first input terminal U1_D and the second input terminal U1_LE of the latch. The system module controls the state of the output terminal U1_Q of the latch by controlling the two GPIO ports GPIO1 and GPIO2. The output terminal U1_Q of the latch is connected to the enable terminal U2_EN of the watchdog U2. The output terminal U1_Q of the latch controls the enable of the watchdog U2. A low level indicates that the watchdog is enabled and outputs a low level to reset the system. A high level indicates that the watchdog is disabled and outputs a high level.

[0026] Specifically, the output terminal U1_Q of the latch is connected to the enable terminal of the watchdog timer through the first resistor R1. The enable terminal of the watchdog timer is also connected to GND through the second resistor R2. By configuring R1 and R2, when U1_Q is high, U2_EN is also high. U2_EN is connected to GND through R2, which can keep U2_EN low when U1_Q is in a high impedance state, thus enabling U2.

[0027] One path of the latch's VCC terminal is connected to VCC, and the other path is connected to GND via the first capacitor C1. The watchdog's VCC terminal is connected to GND via the second capacitor C2. C1 and C2 are IC decoupling capacitors used to reduce noise and voltage fluctuations on the power lines.

[0028] The watchdog's output terminal WDO is connected to the system module's reset terminal RST via the third resistor R3. In addition, RST is also connected to VCC via the fourth resistor R4 and to GND via the fourth capacitor C4. R4 and C4 are commonly used power-on reset circuits.

[0029] In addition to being connected to GPIO2, U1_LE is also connected to the fifth resistor R5. R5 can keep U1_LE at a low level when GPIO2 is in a high impedance state, so that the output of latch Q is locked and is not affected by changes in D.

[0030] The watchdog's enable pin U2_EN is also connected to the first end of the shorting pin JP1, and the second end of JP1 is connected to VCC. By using a pluggable shorting cap to short the first and second ends of JP1, U2_EN becomes high, thus disabling the watchdog and preventing the system module from being reset.

[0031] Using the circuit in Example 1, the watchdog timer can be disabled by shorting the pins and the GPIO signals of the system module, respectively. The working principle is as follows:

[0032] When JP1 is shorted, the U2_EN pin is connected to a high level, and the watchdog timer is disabled. This way, when the system software is upgraded, the watchdog timer will not output a reset signal, and the system module S1 can be upgraded smoothly.

[0033] By controlling the output signals of GPIO1 and GPIO2 to be both high, U1_Q, being a D-type latch, outputs a high level. At this point, the software upgrade begins. During the upgrade process, the system's GPIOs are either low or in a high-impedance state, so U1_LE will be low, while U1_Q will remain high. The watchdog timer remains disabled, thus not affecting the software upgrade. After the upgrade is complete, the software switches U1_Q back to a low output, and the watchdog timer is restored.

[0034] Example 2:

[0035] like Figure 3 As shown, this embodiment provides a system online upgrade circuit for use when the watchdog has no enable pin and the reset pin of the system module is active low. The circuit includes a watchdog U2, a latch U1, an OR gate U3, a shorting pin JP1, and a system module S1.

[0036] The latch's first input U1_D and second input U1_LE are connected to GPIO1 and GPIO2 of the system module, respectively. The output U1_Q is connected to the first resistor R1, and the other end of R1 is connected to the second input U3_B of the OR gate U3. U3_B is connected to GND via the second resistor R2. The resistance values ​​of R1 and R2 are configured so that when U1_Q is high, U3_B is also high. U3_B is connected to GND through R2, which allows U3_B to remain low when U1_Q is in a high-impedance state, making the level of U3_Y the same as that of U3_A. This serves as a watchdog signal to control the system module's reset.

[0037] The first input terminal U3_A of the OR gate is connected to the output terminal WDO of the watchdog timer, and the output terminal U3_Y of the OR gate is connected to the reset terminal of the system module via the third resistor R3. The second input terminal U3_B of the OR gate is also connected to the first terminal of the shorting pin JP1, and the second terminal of JP1 is connected to VCC. The first and second terminals of JP1 are shorted by a shorting cap.

[0038] The VCC terminal of the latch is connected to GND via the first capacitor C1, the VCC terminal of the watchdog is connected to GND via the second capacitor C2, and the VCC terminal of the OR gate is connected to GND via the third capacitor C3. C1, C2, and C3 are IC decoupling capacitors used to reduce noise and voltage fluctuations on the power lines.

[0039] The output terminal U3_Y of the OR gate is connected to the reset terminal RST of the system module via the third resistor R3. In addition, RST is also connected to VCC via the fourth resistor R4 and to GND via the fourth capacitor C4. R4 and C4 are commonly used power-on reset circuits.

[0040] In addition to being connected to GPIO2, U1_LE is also connected to the fifth resistor R5. R5 can keep U1_LE at a low level when GPIO2 is in a high impedance state, so that the output of latch Q is locked and is not affected by changes in D.

[0041] The watchdog timer can be disabled by shorting the pins and the GPIO signals of the system module, respectively, using the circuit in Example 2. The working principle is as follows:

[0042] When JP1 is shorted, the U2_EN pin is connected to a high level, making the OR gate U3_Y always high. This way, the system software upgrade will not be affected by the watchdog signal, and S1 can upgrade the software smoothly.

[0043] By controlling the output signals of GPIO1 and GPIO2 to be both high, and since U1 is a D-type latch, U1_Q outputs a high level. At this point, the software upgrade begins. During the software upgrade process, the system's GPIOs are either low or in a high-impedance state, so U1_LE will be low, while U1_Q will remain high. U3 is an OR gate, so U3_Y will remain high. The watchdog timer remains disabled, thus not affecting the software upgrade. After the upgrade is complete, the software controls U1_Q to output a low level, and the watchdog timer is restored.

[0044] Example 3:

[0045] like Figure 4 As shown, this embodiment provides a system online upgrade circuit for use when the watchdog has no enable pin and the reset pin of the system module is active high. The circuit includes a watchdog U2, a latch U1, an AND gate U3, a shorting pin JP1, and a system module S1.

[0046] The latch's first input U1_D and second input U1_LE are connected to GPIO1 and GPIO2 of the system module, respectively. The output U1_Q is connected to the first resistor R1, and the other end of R1 is connected to the second input U3_B of the AND gate. U3_B is connected to VCC via the second resistor R2. The resistance values ​​of R1 and R2 are configured so that when U1_Q is low, U3_B is also low. R2 connected to VCC allows U3_B to remain high when U1_Q is in a high-impedance state, making the level of U3_Y the same as U3_A, thus providing a watchdog signal to control the system module's reset.

[0047] The first input terminal U3_A of the AND gate is connected to the output terminal WDO of the watchdog timer, and the output terminal U3_Y of the AND gate is connected to the reset terminal of the system module via the third resistor R3. The second input terminal U3_B of the AND gate is also connected to the first terminal of the shorting pin JP1, and the second terminal of JP1 is connected to GND. The first and second terminals of JP1 are shorted by a shorting cap.

[0048] The VCC terminal of the latch is connected to GND via the first capacitor C1, the VCC terminal of the watchdog is connected to GND via the second capacitor C2, and the VCC terminal of the AND gate is connected to GND via the third capacitor C3. C1, C2, and C3 are IC decoupling capacitors used to reduce noise and voltage fluctuations on the power lines.

[0049] The output terminal U3_Y of the AND gate is connected to the reset terminal RST of the system module via the third resistor R3. In addition, RST is also connected to GND via the fourth resistor R4 and to VCC via the fourth capacitor C4. R4 and C4 are commonly used power-on reset circuits.

[0050] In addition to being connected to GPIO2, U1_LE is also connected to the fifth resistor R5. R5 can keep U1_LE at a low level when GPIO2 is in a high impedance state, so that the output of latch Q is locked and is not affected by changes in D.

[0051] The watchdog timer can be disabled by shorting the pins and the GPIO signals of the system module, respectively, using the circuit in Example 3. The working principle is as follows:

[0052] When JP1 is shorted, pin U3_B is connected to a low level, making AND gate U3_Y always low. This way, the system software upgrade will not be affected by the watchdog signal (system module high-level reset), and S1 can upgrade the software smoothly.

[0053] By controlling the output signal of GPIO2 to a high level and GPIO1 to a low level, and since U1 is a D-type latch, when a high-level trigger signal is input to the U1_LE pin, the Q pin outputs the same level as the D pin, and U1_Q outputs a low level. At this time, the software upgrade begins. During the software upgrade process, the system's GPIOs are either low or in a high-impedance state, so U1_LE will be at a low level, and U1_Q will remain low. U3 is an AND gate, and U3_Y will remain low. The watchdog timer remains disabled and does not affect the software upgrade. After the upgrade is complete, the software controls U1_Q to output a high level, and the watchdog timer is restored.

[0054] According to the embodiments of this application, when the device casing is inconvenient to open and hardware methods cannot be used, software upgrades can be performed by externally triggering the GPIO interface to disable the watchdog timer.

[0055] The foregoing has shown and described the basic principles and main features of this utility model. It is obvious to those skilled in the art that this utility model is not limited to the details of the above exemplary embodiments. Therefore, the embodiments should be regarded as exemplary and non-limiting. The scope of this utility model is defined by the appended claims rather than the foregoing description. Therefore, it is intended to include all changes that fall within the meaning and scope of the equivalents of the claims within this utility model.

[0056] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A watchdog-based online upgrade circuit for a system, characterized in that, The system includes a watchdog control module, a latch, and a system module. The first GPIO port and the second GPIO port of the system module are connected to the first input terminal and the second input terminal of the latch. The output terminal of the latch is connected to the watchdog control module to control the working state of the watchdog control module. The output terminal of the watchdog control module is connected to the reset signal input terminal of the system module. When the system module receives the reset signal from the watchdog output terminal, it performs a reset operation.

2. The system online upgrade circuit based on a watchdog timer according to claim 1, characterized in that, The watchdog control module includes a watchdog, which has an enable terminal. The output terminal of the latch is connected to the enable terminal of the watchdog, and the output terminal of the watchdog is connected to the reset signal input terminal of the system module.

3. The system online upgrade circuit based on a watchdog timer according to claim 2, characterized in that, It also includes a shorting pin, one end of which is connected to VCC and the other end is connected to the enable pin of the watchdog timer.

4. The system online upgrade circuit based on a watchdog timer according to claim 1, characterized in that, The watchdog control module includes a watchdog timer and a logic gate. The output of the watchdog timer is connected to the first input of the logic gate, the output of the latch is connected to the second input of the logic gate, and the output of the logic gate is connected to the reset signal input of the system module.

5. The online upgrade circuit for a watchdog-based system according to claim 4, characterized in that, The logic gate is an OR gate. The output of the watchdog timer is connected to the first input of the OR gate. The output of the OR gate is connected to the reset signal input of the system module. The system module is reset when the reset signal input is low.

6. The online upgrade circuit for a watchdog-based system according to claim 5, characterized in that, It also includes a shorting pin, one end of which is connected to VCC, and the other end has two paths, one of which is connected to GND, and the other is connected to the second input of the logic OR gate.

7. The online upgrade circuit for a watchdog-based system according to claim 4, characterized in that, The logic gate is an AND gate. The output of the watchdog timer is connected to the first input of the AND gate. The output of the AND gate is connected to the reset signal input of the system module. The system module is reset when the reset signal input of the system module is high.

8. The online upgrade circuit for a watchdog-based system according to claim 7, characterized in that, It also includes a shorting pin, one end of which is connected to GND, and the other end has two paths, one of which is connected to VCC, and the other is connected to the second input terminal of the logic AND gate.

9. A watchdog-based online upgrade circuit according to claim 4, characterized in that, The output of the latch is connected to the second input of the logic gate via a first resistor, and the second input of the logic gate is also connected to GND or VCC via a second resistor.

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