A charging circuit supporting dual charging interface charging and data communication

Abstract

The utility model provides a kind of charging circuit that supports double charging interface charging and data communication, belong to charging circuit field.The utility model charging circuit that supports double charging interface charging and data communication includes first switching circuit, second switching circuit and priority control circuit, wherein, the input of the first switching circuit is connected with first charging interface, the input of the second switching circuit is connected with second charging interface, the output of the first switching circuit and second switching circuit is connected, for providing charging voltage, the priority control circuit is connected with the first switching circuit and second switching circuit respectively, for selecting first switching circuit or second switching circuit output charging voltage.The utility model has the beneficial effect that: effectively avoid the product damage caused by current conflict caused by simultaneously inserting multiple charging ports with power supply.

Description

Technical Field

[0001] This utility model relates to the field of charging circuits, specifically to a charging circuit that supports dual charging interfaces for charging and data communication. Background Technology

[0002] With the widespread adoption of Type-C interfaces, more and more electronic devices are using this universal interface for charging, data transfer, and other functions. However, in electronic devices with multiple Type-C interfaces, connecting multiple charging devices simultaneously can cause power surges, and even high currents can damage the devices. Therefore, how to rationally allocate charging priorities and prevent power conflicts has become an urgent problem to be solved. In existing technologies, some devices only allow a single interface for charging or do not effectively manage multiple power inputs, which may lead to a poor user experience or even hardware damage. Utility Model Content

[0003] To address the problems in the prior art, this utility model provides a charging circuit that supports dual charging interfaces for charging and data communication.

[0004] This utility model relates to a charging circuit that supports dual charging interfaces and data communication, comprising a first switching circuit, a second switching circuit, and a priority control circuit. The input terminal of the first switching circuit is connected to the first charging interface, and the input terminal of the second switching circuit is connected to the second charging interface. The output terminals of the first and second switching circuits are connected together to provide a charging voltage. The priority control circuit is connected to both the first and second switching circuits to select which switching circuit outputs the charging voltage.

[0005] Furthermore, the first switching circuit includes a first switching module and a first voltage divider module connected to the control terminal of the first switching transistor module, wherein the input terminal of the first voltage divider module is connected to the power output terminal of the first charging interface.

[0006] Furthermore, the first switching circuit also includes an energy storage module, which is disposed between the output terminal of the voltage divider module and the control terminal of the first switching transistor module.

[0007] Furthermore, the first switching circuit also includes a first soft-start module, which is disposed at the voltage input terminal and / or voltage output terminal of the first switching transistor module.

[0008] Furthermore, the first switching module includes a bidirectional turn-off switching circuit composed of the NMOS transistor Q26 and the PMOS transistor Q25, and an NMOS transistor Q27 that controls the NMOS transistor Q26 and an NMOS transistor Q28 that controls the PMOS transistor Q25. The sources of the NMOS transistors Q28 and Q27 are grounded, and their gates are connected to the power output terminal of the first charging interface.

[0009] Furthermore, the first soft-start module includes polarized capacitors C65 and C66. The drain of the NMOS transistor Q28 is connected to the gate of the PMOS transistor Q25, one end of the resistor R89, and the positive terminal of the polarized capacitor C65 via resistor R92. The negative terminal of the polarized capacitor C65 and the other end of the resistor R89 ​​are connected to the power output terminal of the first charging interface. The drain of the NMOS transistor Q27 is connected to the gate of the NMOS transistor Q26, one end of the resistor R90, and the positive terminal of the polarized capacitor C66 via resistor R91. The negative terminal of the polarized capacitor C66 and the other end of the resistor R90 are connected to the power output terminal of the switching circuit.

[0010] Furthermore, the priority control circuit includes a switching transistor Q29, the source of which is grounded and the drain of which is connected to the control terminal of the second switching circuit. The gate of the switching transistor Q29 is connected to the power output terminal of the first charging interface through a third voltage divider module.

[0011] Furthermore, the second switching circuit includes a second switching module and a second voltage divider module connected to the control terminal of the second switching transistor module. The input terminal of the second voltage divider module is connected to the power output terminal of the second charging interface, and the drain of the switching transistor Q29 is connected to the output terminal of the second voltage divider module.

[0012] Furthermore, the second switching circuit also includes a second soft-start module, which is disposed at the voltage input terminal and / or voltage output terminal of the second switching transistor module.

[0013] Compared with the prior art, the beneficial effects of this utility model are: both charging interfaces support charging and data communication functions, and users can flexibly choose either interface to connect to an external power source or peripheral device. By setting a priority control circuit, even if power is plugged into TYPEC0 and TYPEC1 ports at the same time, the internal hardware circuit of the device can coordinate the two power inputs to ensure that the product will not be damaged due to current conflict. Attached Figure Description

[0014] To more clearly illustrate the solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a structural block diagram of the present utility model;

[0016] Figure 2 A circuit schematic diagram of an embodiment of the first charging interface and the second charging interface;

[0017] Figure 3 This is a circuit schematic diagram of an embodiment of the first switching circuit of this utility model;

[0018] Figure 4 This is a circuit schematic diagram of an embodiment of the priority control circuit of this utility model;

[0019] Figure 5 This is a circuit diagram of an embodiment of the second switching circuit of this utility model. Detailed Implementation

[0020] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, and accompanying drawings are used to distinguish different objects, not to describe a particular order.

[0021] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment to other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0022] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0023] like Figure 1As shown, the present invention provides a charging circuit that supports dual charging interfaces and data communication, including a first switching circuit, a second switching circuit, and a priority control circuit. The input terminal of the first switching circuit is connected to the first charging interface, and the input terminal of the second switching circuit is connected to the second charging interface. The output terminals of the first and second switching circuits are connected to provide a charging voltage. The priority control circuit is connected to both the first and second switching circuits and is used to select which switching circuit outputs the charging voltage.

[0024] This invention also includes a first power detection circuit and a second power detection circuit. The output terminals of the first power detection circuit and the second detection circuit are respectively connected to the power management unit of the electronic device, so that the power management unit of the electronic device can obtain the charging status in real time.

[0025] like Figure 2 As shown, the charging interface in this example preferably uses the currently mainstream Type-C interface. Of course, a USB interface or other similar interface can also be used, enabling simultaneous charging and data transfer. The main features of this utility model are as follows:

[0026] 1. Dual Type-C interface function: Both Type-C interfaces (TYPEC0 and TYPEC1) support charging and data communication functions, and users can flexibly choose either interface to connect to an external power source or peripheral device;

[0027] 2. Charging Priority Management: In this example, the charging priority of TYPEC0 port is set higher than that of TYPEC1 port. When TYPEC1 port is charging, if TYPEC0 port detects power input, the system will automatically switch to TYPEC0 port for charging and stop the charging operation of TYPEC1 port.

[0028] 3. Power conflict protection: Even if the power is plugged into TYPEC0 and TYPEC1 ports at the same time, the internal hardware circuit of the device can coordinate the two power inputs to ensure that the product will not be damaged due to current conflict.

[0029] 4. Dynamic switching logic: When the TYPEC0 port takes over charging, the TYPEC1 port will revert to a state that only supports data communication until the TYPEC0 port disconnects from the power supply.

[0030] like Figure 3 As shown in the figure, as an embodiment of the present invention, the first switching circuit includes a first switching module and a first voltage divider module connected to the control terminal of the first switching transistor module. The input terminal of the first voltage divider module is connected to the power output terminal of the first charging interface.

[0031] Preferably, the first switching circuit further includes an energy storage module, which is disposed between the output terminal of the voltage divider module and the control terminal of the first switching transistor module. In this example, the energy storage module is capacitor C68. By setting capacitor C68, it can be ensured that when the first switching circuit is in a completely off state, the energy of capacitor C68 is discharged to a certain extent before the second switching circuit is turned on, thereby improving the safety of the electronic device.

[0032] Preferably, the first switching circuit in this example further includes a first soft-start module, which is disposed at the voltage input terminal and / or voltage output terminal of the first switching transistor module.

[0033] Specifically, in this circuit example, the first switching module includes a bidirectional turn-off switching circuit composed of the NMOS transistor Q26 and the PMOS transistor Q25, and an NMOS transistor Q27 that controls the NMOS transistor Q26, and an NMOS transistor Q28 that controls the PMOS transistor Q25. The sources of the NMOS transistors Q28 and Q27 are grounded, and their gates are connected to the power output terminals of the first charging interface. Of course, the first switching module in this example can also be configured as a single electronic switch to realize the on / off switching of the charging circuit.

[0034] In this example, the first soft-start module includes polarized capacitors C65 and C66. The drain of the NMOS transistor Q28 is connected to the gate of the PMOS transistor Q25, one end of the resistor R89, and the positive terminal of the polarized capacitor C65 via resistor R92. The negative terminal of the polarized capacitor C65 and the other end of the resistor R89 ​​are connected to the power output terminal of the first charging interface. The drain of the NMOS transistor Q27 is connected to the gate of the NMOS transistor Q26, one end of the resistor R90, and the positive terminal of the polarized capacitor C66 via resistor R91. The negative terminal of the polarized capacitor C66 and the other end of the resistor R90 are connected to the power output terminal of the switching circuit.

[0035] like Figure 4 As shown, the priority control circuit in this example includes a switching transistor Q29. The source of the switching transistor Q29 is grounded, the drain is connected to the control terminal of the second switching circuit, and the gate of the switching transistor Q29 is connected to the power output terminal of the first charging interface through a third voltage divider module.

[0036] like Figure 5As shown, the second switching circuit in this example is basically the same as the first switching circuit. The second switching circuit in this example includes a second switching module and a second voltage divider module connected to the control terminal of the second switching transistor module. The input terminal of the second voltage divider module is connected to the power output terminal of the second charging interface. The structurally similar parts will not be described again. The difference between the second switching circuit and the first switching circuit is that the drain of the switching transistor Q29 in this example is connected to the output terminal of the second voltage divider module. When the first switching circuit is powered, the switching transistor Q29 is turned on, giving the second switching module a disconnect signal, controlling the charging line of the second switching circuit to be disconnected, and the electronic device cannot be charged through the Type-C1 interface.

[0037] Preferably, the second switching circuit in this example includes a second soft-start module, which is disposed at the voltage input terminal and / or voltage output terminal of the second switching transistor module. The second soft-start module consists of capacitor C69 and capacitor C70.

[0038] In this example, the first, second, and third voltage divider modules all use voltage divider resistors. There are two voltage divider resistors, which are connected in series and in parallel to the corresponding control terminals, respectively.

[0039] The working principle of this utility model is as follows:

[0040] Detection Module: Each Type-C interface is equipped with an independent Power Detection Unit (PWU) to identify whether a compliant charging device is connected. Through the CC signal communication of Type-C, the PWU reports the current interface status (such as voltage, current, etc.) to the power management unit in real time. In this example, the PWU can be a sampling resistor or similar component.

[0041] Priority control, conflict handling, and recovery mechanisms: This function is entirely implemented through hardware circuit design. The charging priority is defined by the hardware circuitry; by default, the TYPEC0 port has a higher priority than the TYPEC1 port. If the TYPEC0 port detects a valid power input, the system will switch to the TYPEC0 port as the main charging channel, regardless of the current state of the TYPEC1 port. When two power sources are connected simultaneously, the hardware-designed switching circuit cuts off the charging path to the TYPEC1 port, ensuring that only the higher-priority TYPEC0 port participates in the charging process. Once the TYPEC0 port is disconnected from the power supply, if the TYPEC1 port is still in a valid power input state, the system automatically switches back to the TYPEC1 port to continue charging.

[0042] The specific circuit implementation principle is as follows:

[0043] 1. Taking the first switching circuit as an example, when the first power detection circuit (PMU0) detects that a standard charging device is connected, the VBUS_TYPE_C0 voltage is 20V. At this time, the gs voltage of NMOS transistors Q27 and Q28 is divided into 2.143V by resistors R93 and R94. This voltage is greater than the Vgs(th) voltage of the NMOS transistors, so NMOS transistors Q27 and Q28 are turned on. When the two NMOS transistors are turned on, the GS voltage of PMOS transistor Q25 changes from 0V to -10V obtained by the voltage division of resistors R89 and R92. At this time, PMOS transistor Q25 is turned on. At the same time, the voltage is turned on to the VIN_CHARGE terminal through the body diode of Q26. The GS voltage of Q26 is -10V through R90 and R91, so Q26 is also turned on. Capacitors C65 and C66 are soft-start capacitors. The charging paths of TYPEC0 and TYPEC1 can be cut off through this switching circuit.

[0044] 2. The priority determination circuit is mainly controlled by NMOS transistor Q29. Designed so that TYPEC0 has a higher priority than TYPEC1, the 20V VBUS_TYPE_C0 power supply is divided by resistors R95 and R96 to obtain a voltage of 2.701V. At this time, NMOS transistor Q29 conducts, which pulls the gate-source voltage (GS) of Q32 and Q33 down to 0, thus turning off the second switching circuit. This achieves priority control, conflict handling, and a recovery mechanism.

[0045] 3. When the Type-C interface is used as a data port, the battery management unit controls the 5V output. Because of the presence of the voltage divider resistor, the 5V voltage cannot turn on the NMOS transistor, so the data transmission of the Type-C port will not be affected.

[0046] As can be seen from the above, the present invention has the following advantages:

[0047] 1. Improved user experience: Users no longer need to worry about not being able to charge their devices by plugging them into the wrong port; any Type-C port can meet their daily needs.

[0048] 2. Enhanced security: Through priority management and conflict protection mechanisms, the risk of hardware damage caused by multiple power inputs is effectively avoided;

[0049] 3. Enhanced flexibility: Supports simultaneous charging and data communication to meet diverse usage scenarios.

[0050] The specific embodiments described above are preferred embodiments of this utility model, and are not intended to limit the specific scope of this utility model. The scope of this utility model includes but is not limited to the specific embodiments described above. All equivalent changes made in accordance with this utility model are within the protection scope of this utility model.

Claims

1. A charging circuit supporting dual charging interfaces and data communication, characterized in that: The device includes a first switching circuit, a second switching circuit, and a priority control circuit. The input terminal of the first switching circuit is connected to a first charging interface, and the input terminal of the second switching circuit is connected to a second charging interface. The output terminals of the first and second switching circuits are connected together to provide a charging voltage. The priority control circuit is connected to both the first and second switching circuits to select which switching circuit outputs the charging voltage. The priority control circuit includes a switching transistor Q29, the source of which is grounded and the drain of which is connected to the control terminal of the second switching circuit. The gate of the switching transistor Q29 is connected to the power output terminal of the first charging interface through a third voltage divider module.

2. The charging circuit supporting dual charging interfaces and data communication according to claim 1, characterized in that: It also includes a first power detection circuit and a second power detection circuit, the outputs of which are respectively connected to the power management unit of the electronic device.

3. The charging circuit supporting dual charging interfaces and data communication according to claim 1 or 2, characterized in that: The first switching circuit includes a first switching module and a first voltage divider module connected to the control terminal of the first switching transistor module. The input terminal of the first voltage divider module is connected to the power output terminal of the first charging interface.

4. The charging circuit supporting dual charging interfaces and data communication according to claim 3, characterized in that: The first switching circuit further includes an energy storage module, which is disposed between the output terminal of the voltage divider module and the control terminal of the first switching transistor module.

5. The charging circuit supporting dual charging interfaces and data communication according to claim 3, characterized in that: The first switching circuit further includes a first soft-start module, which is disposed at the voltage input terminal and / or voltage output terminal of the first switching transistor module.

6. The charging circuit supporting dual charging interfaces and data communication according to claim 5, characterized in that: The first switching module includes a bidirectional turn-off switching circuit composed of an NMOS transistor Q26 and a PMOS transistor Q25, an NMOS transistor Q27 that controls the NMOS transistor Q26, and an NMOS transistor Q28 that controls the PMOS transistor Q25. The sources of the NMOS transistors Q28 and Q27 are grounded, and their gates are connected to the power output terminal of the first charging interface.

7. The charging circuit supporting dual charging interfaces and data communication according to claim 6, characterized in that: The first soft-start module includes polarized capacitors C65 and C66. The drain of the NMOS transistor Q28 is connected to the gate of the PMOS transistor Q25, one end of the resistor R89, and the positive terminal of the polarized capacitor C65 via resistor R92. The negative terminal of the polarized capacitor C65 and the other end of the resistor R89 ​​are connected to the power output terminal of the first charging interface. The drain of the NMOS transistor Q27 is connected to the gate of the NMOS transistor Q26, one end of the resistor R90, and the positive terminal of the polarized capacitor C66 via resistor R91. The negative terminal of the polarized capacitor C66 and the other end of the resistor R90 are connected to the power output terminal of the switching circuit.

8. The charging circuit supporting dual charging interfaces and data communication according to claim 1 or 2, characterized in that: The second switching circuit includes a second switching module and a second voltage divider module connected to the control terminal of the second switching transistor module. The input terminal of the second voltage divider module is connected to the power output terminal of the second charging interface, and the drain of the switching transistor Q29 is connected to the output terminal of the second voltage divider module.

9. The charging circuit supporting dual charging interfaces and data communication according to claim 8, characterized in that: The second switching circuit also includes a second soft-start module, which is disposed at the voltage input terminal and / or voltage output terminal of the second switching transistor module.

Images