Low-power consumption SSR secondary feedback sampling circuit

Abstract

The application discloses a low-power-consumption SSR secondary feedback sampling circuit, which comprises an optocoupler secondary side unit, which is used for receiving an optical signal from an optocoupler and outputting an optocoupling current Iop; a current mirror module, which is connected with the optocoupler secondary side unit and is used for receiving the optocoupling current Iop and generating a first current I1, a second current I2 and a third current I3 according to a preset ratio; a voltage stabilizing module, which is connected with the current mirror module and is used for stabilizing a control voltage of the first current I1; a power supply module, which is connected with the current mirror module and is used for supplying power for an internal power supply VDD; a feedback module, which is connected with the current mirror module and is used for forming a feedback voltage VFB and a limiting voltage V1; and a current limiting module, which is connected with the optocoupler secondary side unit at an input end, is connected with the feedback module at a first end and is connected with the voltage stabilizing module at a second end; the current limiting module is configured to gradually reduce the voltage of the voltage stabilizing module, limit the first current I1, and thus limit the optocoupling current Iop and the feedback voltage VFB when the limiting voltage V1 exceeds a preset threshold.

Description

Technical Field

[0001] This application relates to the field of circuit design, and more specifically to a low-power SSR secondary feedback sampling circuit. Background Technology

[0002] In existing isolated switching power supplies, to achieve effective control of input and output power, it is typically necessary to feed back the output power information from the secondary side to the primary side. Due to the electrical isolation between the primary and secondary sides, the transmission of the feedback signal is generally accomplished through an optocoupler to simultaneously meet the requirements of signal transmission and safety isolation. In a typical structure, the secondary circuit adjusts the optocoupler current based on the output voltage. This current transmits the feedback information and is used to control the switching state of the power devices, achieving precise adjustment of the output power. However, under light load or no-load conditions, to ensure stable conduction of the feedback path, the optocoupler current still needs to maintain a certain amplitude, resulting in the feedback loop continuously consuming a large current. This design still consumes a significant amount of current under light load or no-load conditions, increasing unnecessary energy consumption and reducing the overall efficiency of the power supply system, especially performing poorly in low-power applications.

[0003] Furthermore, in existing technologies, the optocoupler current usually directly supplies current to the internal low-voltage power supply circuit (VDD). However, when the system load changes, the optocoupler current is prone to fluctuation, which leads to unstable feedback sampling signals and causes system oscillations or malfunctions. This not only affects the stability of the system but also reduces the overall performance. Utility Model Content

[0004] The purpose of this application is to provide a low-power SSR secondary feedback sampling circuit, which addresses the problems of unstable feedback sampling signals, high energy consumption, and easy oscillation and malfunction in the prior art, thereby improving the stability and energy efficiency of the system.

[0005] To achieve the above objectives, this application discloses the following technical solution:

[0006] This application provides a low-power SSR secondary feedback sampling circuit, including:

[0007] The secondary side unit of the optocoupler is connected to the high voltage VCC and is used to receive optical signals from the optocoupler and output optocoupler current Iop;

[0008] The current mirror module is connected to the secondary side unit of the optocoupler and is used to receive the optocoupler current Iop and generate a first current I1, a second current I2 and a third current I3 according to a preset ratio.

[0009] A voltage regulator module, connected to the current mirror module, is used to receive the first current I1 and stabilize the control voltage of the first current I1;

[0010] The power supply module, connected to the current mirror module, is used to receive the second current I2 and supply power to the internal power supply VDD;

[0011] The feedback module, connected to the current mirror module, is used to receive the third current I3 and form a feedback voltage VFB and a limiting voltage V1;

[0012] The current limiting module has its input terminal connected to the secondary side unit of the optocoupler, its first terminal connected to the feedback module, and its second terminal connected to the voltage regulator module. The current limiting module is configured to gradually reduce the voltage of the voltage regulator module when the limiting voltage V1 exceeds a preset threshold, thereby limiting the first current I1, and thus limiting the optocoupler current Iop and the feedback voltage VFB.

[0013] Optionally, the secondary side unit of the optocoupler includes a phototransistor, whose collector is connected to the high voltage VCC, and whose emitter outputs the optocoupler current Iop.

[0014] Optionally, the current mirror module includes a first switch M1, a second switch M2, and a third switch M3;

[0015] The current input terminals of the first switch M1, the second switch M2, and the third switch M3 are all connected to the emitter of the phototransistor. The control terminals of the second switch M2 and the third switch M3 are all connected to the control terminal of the first switch M1. The control terminal of the first switch M1 is connected to the current output terminal of the first switch M1.

[0016] The first current I1 flows through the first switch M1, the second current I2 flows through the second switch M2, and the third current I3 flows through the third switch M3.

[0017] Optionally, the first switch M1, the second switch M2, and the third switch M3 are all PMOS transistors, and the first switch M1, the second switch M2, and the third switch M3 are mirror images of each other and have a certain proportional relationship.

[0018] Optionally, the voltage regulator module includes a fourth switching transistor M4 and a first voltage regulator transistor Z1;

[0019] The current input terminal of the fourth switch M4 is connected to the current output terminal of the first switch M1, and the current output terminal of the fourth switch M4 is grounded through the first Zener diode Z1. The control terminal is connected to the first node A of the current limiting module.

[0020] Optionally, the power supply module includes a first diode D1, a capacitor C, and a second Zener diode Z2;

[0021] The positive terminal of the first diode D1 is connected to the current output terminal of the second switching transistor M2, and the negative terminal is grounded through the capacitor C; the connection node between the first diode D1 and the capacitor C is connected to the internal power supply VDD.

[0022] The negative terminal of the second Zener diode Z2 is connected to the negative terminal of the first diode D1, and the positive terminal is grounded.

[0023] Optionally, the feedback module includes a first resistor R1, a second resistor R2, and a third resistor R3;

[0024] One end of the first resistor R1 is connected to the current output terminal of the third switch M3, and the other end is grounded through the second resistor R2 and the third resistor R3 connected in sequence;

[0025] The voltage at the second node B between the first resistor R1 and the second resistor R2 is set to the feedback voltage VFB, and the voltage at the third node C between the second resistor R2 and the third resistor R3 is set to the limiting voltage V1.

[0026] Optionally, the current limiting module includes:

[0027] The fifth switch M5 has its current input terminal connected to the emitter of the phototransistor and its current output terminal connected to the control terminal of the fifth switch M5.

[0028] The sixth switch M6 has its current input terminal connected to the emitter of the phototransistor and its control terminal connected to the control terminal of the fifth switch M5.

[0029] The seventh switch M7 has its current input terminal connected to the current output terminal of the fifth switch M5, and its control terminal is connected to an external voltage Vref.

[0030] The eighth switch M8 has its current input terminal connected to the current output terminal of the sixth switch M6, and its control terminal connected to the third node C.

[0031] The connection point between the sixth switch M6 and the eighth switch M8 is the first node A.

[0032] Optionally, the current limiting module further includes:

[0033] The constant current source I0 has its input terminal connected to the current output terminal of the seventh switch M7 and the current output terminal of the eighth switch M8, and its output terminal is grounded.

[0034] Optionally, both the fifth switch M5 and the sixth switch M6 are PMOS transistors, and the fifth switch M5 and the sixth switch M6 are mirror images of each other and have a certain proportional relationship.

[0035] Both the seventh switch M7 and the eighth switch M8 are NMOS transistors, and the parameters of the seventh switch M7 and the eighth switch M8 are the same.

[0036] The low-power SSR secondary feedback sampling circuit provided in this application embodiment achieves multi-path current splitting of the optocoupler current Iop by setting a current mirror module on the secondary side of the optocoupler. The current mirror structure effectively isolates the influence of the VDD node on the main current path, avoiding gate voltage fluctuations caused by VDD voltage jitter, thereby preventing false feedback and loop oscillations and improving system stability. Simultaneously, the feedback module combined with the current limiting module forms a closed-loop negative feedback structure. When the output voltage increases or the system enters light-load or no-load mode, it can effectively suppress the excessive rise of the optocoupler current Iop by limiting the maximum value of the feedback voltage VFB, thus reducing overall power consumption. This application's structure not only ensures feedback accuracy and system stability but also significantly improves energy efficiency under light-load and no-load conditions, effectively enhancing overall system efficiency.

[0037] Furthermore, by introducing a current mirror module, the optocoupler current Iop, which was originally entirely dissipated by the switching power supply chip, is used to power the internal power supply VDD. This effectively reduces system losses and improves energy efficiency, especially under light load or no-load conditions. Simultaneously, the current limiting module limits the maximum values ​​of the feedback voltage VFB, optocoupler current Iop, and charging current I2, preventing system instability caused by excessive optocoupler current Iop and effectively improving the reliability and energy efficiency of the power supply circuit. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the principles of this application.

[0039] Figure 1 A structural block diagram of a low-power SSR secondary feedback sampling circuit according to an embodiment of this application is shown;

[0040] Figure 2 A topology diagram of a low-power SSR secondary feedback sampling circuit according to an embodiment of this application is shown. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0042] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics; however, not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0043] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0044] Figure 1 A structural block diagram of a low-power SSR secondary feedback sampling circuit according to an embodiment of this application is shown. Figure 1 As shown, this low-power SSR secondary feedback sampling circuit includes an optocoupler secondary-side unit, a current mirror module, a voltage regulator module, a power supply module, a feedback module, and a current limiting module. The optocoupler secondary-side unit is connected to the high voltage VCC and is used to receive the optical signal from the optocoupler and output the optocoupler current Iop. The current mirror module is connected to the optocoupler secondary-side unit and is used to receive the optocoupler current Iop and generate a first current I1, a second current I2, and a third current I3 according to a preset ratio. The voltage regulator module is connected to the current mirror module and is used to receive the first current I1 and stabilize the control voltage of the first current I1. The power supply module is connected to the current mirror module and is used to receive the second current I2 and supply power to the internal power supply VDD. The feedback module is connected to the current mirror module and is used to receive the third current I3 and form a feedback voltage VFB and a limiting voltage V1. The input terminal of the current limiting module is connected to the secondary side unit of the optocoupler, the first terminal is connected to the feedback module, and the second terminal is connected to the voltage regulator module. The current limiting module is configured to gradually reduce the voltage of the voltage regulator module when the limiting voltage V1 exceeds a preset threshold, thereby limiting the first current I1, and thus limiting the optocoupler current Iop and the feedback voltage VFB.

[0045] According to the above embodiments, by setting a current mirror module on the secondary side of the optocoupler, the optocoupler current Iop is multi-path shunting is realized, and the influence of the VDD node on the main current path is effectively isolated by the current mirror structure, avoiding gate voltage fluctuations caused by VDD voltage jitter, thereby preventing false feedback and loop oscillation, and improving the stability of system operation. At the same time, the feedback module combined with the current limiting module forms a closed-loop negative feedback structure. When the output voltage increases or the system enters a light load or no-load mode, the maximum value of the feedback voltage VFB can be limited to effectively suppress the excessive rise of the optocoupler current Iop, thereby reducing the overall power consumption. The structure of this application not only ensures feedback accuracy and system stability, but also significantly improves the energy efficiency performance under light load and no-load conditions, and the overall system efficiency is effectively improved.

[0046] Figure 2 A topology diagram of a low-power SSR secondary feedback sampling circuit according to an embodiment of this application is shown. Figure 2 As shown, the secondary side unit of the optocoupler includes a phototransistor. The collector of the phototransistor is connected to the high voltage VCC, and the emitter outputs the optocoupler current Iop.

[0047] In this embodiment, the secondary-side unit of the optocoupler uses a phototransistor as the receiving device, which converts the optical signal driven by the primary-side optocoupler into a proportional current signal Iop. The aforementioned high-voltage VCC is the primary power supply voltage of the switching power supply chip, typically output from a high-voltage startup circuit or provided by the auxiliary coil of a transformer. As the main power supply, VCC provides energy support for the entire secondary-side circuit. Its voltage level is usually higher than the chip's internal low-voltage operating power supply VDD, playing a crucial role in the circuit's startup and maintenance processes.

[0048] In one embodiment, reference Figure 2 The current mirror module includes a first switch M1, a second switch M2, and a third switch M3. The current input terminals of all three switches are connected to the emitters of a phototransistor. The control terminals of the second and third switches are connected to the control terminal of the first switch M1. The control terminal of the first switch M1 is connected to its current output terminal. A first current I1 flows through the first switch M1, a second current I2 flows through the second switch M2, and a third current I3 flows through the third switch M3.

[0049] In one embodiment, the first switch M1, the second switch M2, and the third switch M3 are all PMOS transistors, and the first switch M1, the second switch M2, and the third switch M3 are mirror images of each other and have a certain proportional relationship. In one embodiment, the ratio of the first switch M1, the second switch M2, and the third switch M3 can be 1:40:1.

[0050] In this embodiment, the current mirror module uses a three-transistor structure to proportionally shunt the optocoupler current Iop. The first switch M1 serves as the reference transistor, and its drain current I1 is controlled by the voltage regulator module. The second and third switches M2 and M3 mirror I1, respectively, outputting the charging current I2 and the sampling current I3. By appropriately setting the size ratio among the three switches, for example, using a 1:40:1 configuration, the regulation capability of the power supply and feedback signals can be significantly enhanced while ensuring the stability of the main current. This design achieves effective utilization of the optocoupler current and improves the sensitivity of feedback control and the overall response characteristics of the system.

[0051] In one embodiment, reference Figure 2 The voltage regulator module includes a fourth switching transistor M4 and a first Zener diode Z1. The current input terminal of the fourth switching transistor M4 is connected to the current output terminal of the first switching transistor M1, and the current output terminal of the fourth switching transistor M4 is grounded through the first Zener diode Z1. The control terminal is connected to the first node A of the current limiting module.

[0052] In this embodiment, the voltage regulation module introduces a first Zener diode Z1 into the output path of the first switch M1, which effectively increases the emitter potential of the phototransistor, ensuring that the second switch M2 in the current mirror operates stably in the saturation region. The second switch M2 effectively isolates the gate voltage of the first switch M1, thus the first current I1 is unaffected by VDD voltage fluctuations, and the mirrored second current I2 and third current I3 also remain stable, avoiding sampling signal jitter and mis-driving phenomena, and improving the stability and reliability of the system. At the same time, the conduction state of the fourth switch M4 is adjusted by the current limiting module, further endowing this path with negative feedback capability, realizing dynamic control of the first current I1, and helping to optimize the consistency of the current mirror output.

[0053] In one embodiment, reference Figure 2 The power supply module includes a first diode D1, a capacitor C, and a second Zener diode Z2. The anode of the first diode D1 is connected to the current output terminal of the second switching transistor M2, and the cathode is grounded through the capacitor C. The connection point between the first diode D1 and the capacitor C is connected to the internal power supply VDD. The cathode of the second Zener diode Z2 is connected to the cathode of the first diode D1, and the anode is grounded.

[0054] In this embodiment, the first diode D1 enables unidirectional conduction, preventing the internal power supply VDD from flowing back into the current mirror. Capacitor C stores and filters the internal power supply VDD, ensuring power supply stability. The second Zener diode Z2 acts as an overvoltage protection element, limiting the upper limit of the internal power supply VDD voltage and ensuring reliable operation of the internal circuitry. Furthermore, the aforementioned internal low-voltage VDD is converted from the internal high-voltage VCC, providing a stable operating voltage for each module within the switching power supply chip. This embodiment achieves efficient energy transfer and enhances the system's energy efficiency under light load or no-load conditions.

[0055] In one embodiment, reference Figure 2 The feedback module includes a first resistor R1, a second resistor R2, and a third resistor R3. One end of the first resistor R1 is connected to the current output terminal of the third switch M3, and the other end is grounded through the second resistor R2 and the third resistor R3 connected in sequence. The voltage at the second node B between the first resistor R1 and the second resistor R2 is set as the feedback voltage VFB, and the voltage at the third node C between the second resistor R2 and the third resistor R3 is set as the limiting voltage V1.

[0056] In this embodiment, the feedback module uses a voltage divider network composed of resistors R1, R2, and R3 to sample and regulate the voltage of the third current I3 output by the third switch M3. The feedback voltage VFB formed at the second node B serves as the main feedback signal of the system, reflecting the output state and transmitting it to the primary circuit for adjusting the operating state of the power loop. The limiting voltage V1 at the third node C monitors the maximum allowable value of the third current I3. By comparing it with a preset threshold, it limits the sampled current, thereby ensuring the stability and safety of the system operation.

[0057] In one embodiment, reference Figure 2 The current limiting module includes a fifth switch M5, a sixth switch M6, a seventh switch M7, and an eighth switch M8. The current input terminal of the fifth switch M5 is connected to the emitter of the phototransistor, and its current output terminal is connected to the control terminal of the fifth switch M5. The current input terminal of the sixth switch M6 is connected to the emitter of the phototransistor, and its control terminal is connected to the control terminal of the fifth switch M5. The current input terminal of the seventh switch M7 is connected to the current output terminal of the fifth switch M5, and its control terminal is connected to an external voltage Vref. The current input terminal of the eighth switch M8 is connected to the current output terminal of the sixth switch M6, and its control terminal is connected to the third node C. The connection point between the sixth switch M6 and the eighth switch M8 is the first node A.

[0058] In one embodiment, reference Figure 2The current limiting module also includes a constant current source I0, whose input terminal is connected to the current output terminal of the seventh switch M7 and the current output terminal of the eighth switch M8, and whose output terminal is grounded.

[0059] In the above embodiments, the current input terminals of the fifth switch M5 and the sixth switch M6 are both connected to the emitter of the phototransistor, and are controlled by the same control terminal to achieve synchronous current management. The seventh switch M7 sets the current limiting threshold through an external reference voltage Vref, while the eighth switch M8 adjusts its operating state according to the limiting voltage V1 of the third node C of the feedback module. The constant current source I0 is connected to the current output terminals of the seventh switch M7 and the eighth switch M8 to form a stable reference current loop, ensuring the accuracy and response speed of the current limiting control, thereby effectively maintaining the safe and stable operation of the system.

[0060] In one embodiment, the fifth switch M5 and the sixth switch M6 are both PMOS transistors, and the fifth switch M5 and the sixth switch M6 are mirror images of each other and have the same parameters. The seventh switch M7 and the eighth switch M8 are both NMOS transistors, and the seventh switch M7 and the eighth switch M8 have the same parameters.

[0061] In one embodiment, the ratio of the fifth switch M5 to the sixth switch M6 can be 1:1.

[0062] It should be noted that the ratio of the MOSFETs and resistors mentioned above can be adjusted according to the specific circuit design requirements, and there is no fixed limit here.

[0063] According to the above embodiments, the working principle of the low-power SSR secondary feedback sampling circuit provided in this application is as follows: When the switching power supply is first powered on, the output voltage VOUT begins to build up rapidly and rises quickly. At this time, the system is in a heavy load state. The light-emitting diode inside the optocoupler transmits the information of the output voltage VOUT to the phototransistor, causing the emitter current Iop of the phototransistor to rise synchronously. As Iop increases, the fifth switch M5 and the seventh switch M7 in the current limiting module are turned on, while the limiting voltage V1 has not yet reached the conduction threshold of the eighth switch M8, so the eighth switch M8 remains off. At this time, since the sixth switch M6 is a mirror image of the fifth switch M5, the sixth switch M6 is turned on, causing the voltage of the first node A to rise, thereby increasing the control terminal voltage of the fourth switch M4, and thus turning on the fourth switch M4.

[0064] Simultaneously, a first current I1 flows through the first switch M1. The second and third switches M2 and M3 replicate the first current I1 according to a preset ratio, forming the second current I2 and the third current I3, respectively, to charge the VDD energy storage capacitor C. The second current I2 provides stable charging for the VDD energy storage capacitor C, ensuring stable power supply to the internal power source and effectively reducing the power consumption of feedback sampling. The third current I3 flows through a voltage divider network composed of resistors R1, R2, and R3. The feedback voltage VFB is determined by the product of the third current I3 and the total resistance of resistors R2 and R3, i.e., VFB = I3 × (R2 + R3). This feedback voltage VFB transmits the change in the optocoupler current Iop to the primary circuit, used to adjust the operating state of the power loop. It is worth noting that the feedback voltage VFB is directly proportional to the optocoupler current Iop and inversely proportional to the output load. Furthermore, the limiting voltage V1 is the voltage across R3, and its maximum value corresponds to the current limiting threshold of the third current I3. When the third current I3 rises to the point that the voltage across R3 reaches the limiting voltage V1, the increase of the third current I3 will be suppressed. Since the current from the constant current source I0 is very small and negligible, the optocoupler current Iop is approximately equal to the sum of the currents reflected in each resistor, i.e., Iop ≈ i1 + i2 + i3. As the optocoupler current Iop and the third current I3 increase, the limiting voltage V1 across the third resistor R3 gradually rises. When the limiting voltage V1 rises to Vref, the fourth switch M4 begins to limit the current, and the optocoupler current Iop can no longer increase. The system continues to utilize the optocoupler current to store energy for the VDD capacitor, effectively reducing energy loss.

[0065] After the power supply starts up, if the system is under light load or no load, the primary current of the switching power supply chip increases, causing the output voltage VOUT to rise. At this time, the optocoupler current Iop increases, and the first current I1 in the first switch M1 increases synchronously. The second current I2 and the third current I3, mirrored by the second switch M2 and the third switch M3, also increase proportionally, and the feedback voltage VFB rises accordingly. Since the limiting voltage V1 is the voltage across R3, i.e., V1 = I3 × R3, the limiting voltage V1 also rises accordingly. When the limiting voltage V1 exceeds the preset reference voltage VREF, the eighth switch M8 starts to conduct, causing the voltage at the first node A to gradually decrease. This causes the control terminal voltage of the fourth switch M4 to gradually decrease, thereby limiting the first current I1 in the first switch M1. Therefore, the third current I3 stops rising, the system reaches a balanced state, and the limiting voltage V1 is stably controlled at the VREF level. At the same time, the feedback voltage VFB also stops rising, thereby suppressing the further increase of the optocoupler current Iop, realizing automatic current limiting and closed-loop regulation of the system, and ensuring the stability and high efficiency of the circuit under light load or no-load conditions.

[0066] In addition, to ensure the stability of the control process, the seventh switch M7 and the eighth switch M8 are of the same specifications and models in the design.

[0067] In summary, this application achieves the limitation of the maximum value of the feedback voltage VFB through the coordinated operation of the circuit structure, while controlling the maximum supply current of the charging current I2 to the internal power supply VDD, thus ensuring the voltage stability and energy efficiency of the system during operation.

[0068] According to the above embodiments, by improving the optocoupler connection structure and introducing a current mirror shunting mechanism, the optocoupler current can provide auxiliary power to the internal power supply VDD under light load or no-load conditions, significantly improving energy utilization efficiency. Specifically, after the optocoupler current Iop is turned on through the main current branch (the branch where the first switching transistor M1 is located), it is replicated by the mirror circuit to generate the second current I2 and the third current I3. Among them, the second current I2 charges the VDD energy storage capacitor through the unidirectional conduction circuit, replacing part of the traditional power supply path, effectively reducing the energy waste that would have been caused by the complete dissipation of the optocoupler current under light load or no-load conditions.

[0069] Furthermore, this application introduces a current-limiting module to detect and limit the voltage V1 of the third resistor R3, thereby indirectly limiting the maximum value of the feedback voltage VFB and the upper limit of the second current I2, preventing system over-response and improving stability and reliability. Under heavy system load, because the optocoupler current Iop is small, the solution in this application will not interfere with the main power supply path, and the traditional VDD power supply circuit still ensures normal system operation. Under light load or no-load conditions, the circuit can fully utilize the auxiliary power supply function of the second current I2, improving overall efficiency.

[0070] The technical solution of this application will be further described below with reference to specific embodiments.

[0071] In one specific embodiment, if the maximum value of the optocoupler current Iop is set to 200uA, considering the design margin, the current limiting threshold is set to 180uA. The constant current value of the constant current source I0 is set to 10uA, and its shunt effect can be ignored in the calculation. The voltage regulation value of the first Zener diode Z1 is 6V, and the voltage regulation value of the second Zener diode Z2 is 5V. The ratio of the three switching transistors in the current mirror is M1:M2:M3 = 1:38:1, and the resistance in the feedback module is R1 = R2 = R3 = 500kΩ. At the current limiting trigger moment, since the shunt of the constant current source is negligible, I1 + I2 + I3 ≈ Iop = 180uA. According to the current mirror ratio, I3 = Iop × (1 / 40) = 4.5uA. Therefore, the reference voltage of the current limiting point Vref=V1=I3×R3=4.5uA×500kΩ=2.25V; the maximum feedback voltage VFB=I3×(R2+R3)=4.5uA×1MΩ=4.5V; the maximum charging current I2=(180uA / 40)×38=171uA.

[0072] The above parameter configuration ensures that the system triggers current limiting action before the optocoupler current reaches its maximum value, thereby effectively limiting the feedback voltage and VDD charging current and improving the stability and reliability of the system.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A low-power SSR secondary feedback sampling circuit, characterized in that, include: The secondary side unit of the optocoupler is connected to the high voltage VCC and is used to receive optical signals from the optocoupler and output optocoupler current Iop; The current mirror module is connected to the secondary side unit of the optocoupler and is used to receive the optocoupler current Iop and generate a first current I1, a second current I2 and a third current I3 according to a preset ratio. A voltage regulator module, connected to the current mirror module, is used to receive the first current I1 and stabilize the control voltage of the first current I1; The power supply module, connected to the current mirror module, is used to receive the second current I2 and supply power to the internal power supply VDD; The feedback module, connected to the current mirror module, is used to receive the third current I3 and form a feedback voltage VFB and a limiting voltage V1; The current limiting module has its input terminal connected to the secondary side unit of the optocoupler, its first terminal connected to the feedback module, and its second terminal connected to the voltage regulator module. The current limiting module is configured to gradually reduce the voltage of the voltage regulator module when the limiting voltage V1 exceeds a preset threshold, thereby limiting the first current I1, and thus limiting the optocoupler current Iop and the feedback voltage VFB.

2. The low-power SSR secondary feedback sampling circuit according to claim 1, characterized in that, The secondary unit of the optocoupler includes a phototransistor, whose collector is connected to the high voltage VCC, and whose emitter outputs the optocoupler current Iop.

3. The low-power SSR secondary feedback sampling circuit according to claim 2, characterized in that, The current mirror module includes a first switch M1, a second switch M2, and a third switch M3; The current input terminals of the first switch M1, the second switch M2, and the third switch M3 are all connected to the emitter of the phototransistor. The control terminals of the second switch M2 and the third switch M3 are all connected to the control terminal of the first switch M1. The control terminal of the first switch M1 is connected to the current output terminal of the first switch M1. The first current I1 flows through the first switch M1, the second current I2 flows through the second switch M2, and the third current I3 flows through the third switch M3.

4. The low-power SSR secondary feedback sampling circuit according to claim 3, characterized in that, The first switch M1, the second switch M2, and the third switch M3 are all PMOS transistors, and the first switch M1, the second switch M2, and the third switch M3 are mirror images of each other and are in a certain proportional relationship.

5. The low-power SSR secondary feedback sampling circuit according to claim 3, characterized in that, The voltage regulator module includes a fourth switching transistor M4 and a first voltage regulator transistor Z1; The current input terminal of the fourth switch M4 is connected to the current output terminal of the first switch M1, and the current output terminal of the fourth switch M4 is grounded through the first Zener diode Z1. The control terminal is connected to the first node A of the current limiting module.

6. The low-power SSR secondary feedback sampling circuit according to claim 5, characterized in that, The power supply module includes a first diode D1, a capacitor C, and a second Zener diode Z2; The positive terminal of the first diode D1 is connected to the current output terminal of the second switching transistor M2, and the negative terminal is grounded through the capacitor C; the connection node between the first diode D1 and the capacitor C is connected to the internal power supply VDD. The negative terminal of the second Zener diode Z2 is connected to the negative terminal of the first diode D1, and the positive terminal is grounded.

7. The low-power SSR secondary feedback sampling circuit according to claim 6, characterized in that, The feedback module includes a first resistor R1, a second resistor R2, and a third resistor R3; One end of the first resistor R1 is connected to the current output terminal of the third switch M3, and the other end is grounded through the second resistor R2 and the third resistor R3 connected in sequence; The voltage at the second node B between the first resistor R1 and the second resistor R2 is set to the feedback voltage VFB, and the voltage at the third node C between the second resistor R2 and the third resistor R3 is set to the limiting voltage V1.

8. The low-power SSR secondary feedback sampling circuit according to claim 7, characterized in that, The current limiting module includes: The fifth switch M5 has its current input terminal connected to the emitter of the phototransistor and its current output terminal connected to the control terminal of the fifth switch M5. The sixth switch M6 has its current input terminal connected to the emitter of the phototransistor and its control terminal connected to the control terminal of the fifth switch M5. The seventh switch M7 has its current input terminal connected to the current output terminal of the fifth switch M5, and its control terminal is connected to an external voltage Vref. The eighth switch M8 has its current input terminal connected to the current output terminal of the sixth switch M6, and its control terminal connected to the third node C. The connection point between the sixth switch M6 and the eighth switch M8 is the first node A.

9. The low-power SSR secondary feedback sampling circuit according to claim 8, characterized in that, The current limiting module also includes: The constant current source I0 has its input terminal connected to the current output terminal of the seventh switch M7 and the current output terminal of the eighth switch M8, and its output terminal grounded.

10. The low-power SSR secondary feedback sampling circuit according to claim 8, characterized in that, The fifth switch M5 and the sixth switch M6 are both PMOS transistors, and the fifth switch M5 and the sixth switch M6 are mirror images of each other and have a certain proportional relationship. Both the seventh switch M7 and the eighth switch M8 are NMOS transistors, and the parameters of the seventh switch M7 and the eighth switch M8 are the same.

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