Acid-resistant palladium-gold ic package bump structure

Abstract

The utility model discloses an acid -proof palladium gold IC encapsulation bump structure relates to chip packaging technical field, including the silicon wafer carrier, aluminum pad conductive layer, insulating layer, sputtering UBM titanium tungsten layer, sputtering UBM gold layer, electroplating palladium layer, electroplating gold layer and chemical plating gold layer that set up from below to above, wherein, aluminum pad conductive layer is deposited to the silicon wafer carrier surface through metal sputtering technology, and the surface of silicon wafer carrier is provided with insulating layer at aluminum pad conductive layer both sides, sputtering UBM titanium tungsten layer is located the outside of insulating layer, and sputtering UBM titanium tungsten layer is located the inside of sputtering UBM gold layer, in palladium gold bump plus chemical plating a layer of gold as the protective layer, prevent palladium metal layer and reagent water contact and take place the reaction, thereby effectively avoided the increase of bump circuit resistance, short circuit or open circuit, the maintenance market can continue to use after IC is pickled and recovered.

Description

Technical Field

[0001] This utility model specifically relates to the field of chip packaging technology, and more specifically to an acid-resistant palladium gold IC packaging bump structure. Background Technology

[0002] In the DDIC packaging field, there are currently pure gold bumps and palladium bumps. In consumer electronics products, in terms of material cost, pure gold bumps are 2-3 times more expensive than palladium bumps. However, the performance of palladium bumps is no less than that of pure gold bumps. Therefore, many mass-produced and cost-sensitive products choose palladium as the bump material.

[0003] When palladium is selected as the bump material, some products are returned to the repair market. The repair market needs to acid-wash and recycle the ICs. During the acid washing process, the palladium metal layer reacts with the solution and is slowly corroded, causing bump circuit problems in the product during the acid washing process. Utility Model Content

[0004] The purpose of this invention is to provide an acid-resistant palladium-gold IC package bump structure. In this device, a gold plating layer is added to the outside of the palladium-gold bump as a protective layer to prevent the palladium metal layer from reacting with the chemical solution. After the IC is acid-washed and recycled in the repair market, it can be reused, thus solving the problems mentioned in the background technology.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] A palladium-gold IC package bump structure resistant to acid washing includes, from bottom to top, a silicon wafer carrier, an aluminum pad conductive layer, an insulating layer, a sputtered UBM titanium-tungsten layer, a sputtered UBM gold layer, an electroplated palladium layer, an electroplated gold layer, and an electroless gold plating layer; wherein, the aluminum pad conductive layer is deposited on the surface of the silicon wafer carrier by metal sputtering technology, and insulating layers are disposed on both sides of the aluminum pad conductive layer on the surface of the silicon wafer carrier, the sputtered UBM titanium-tungsten layer is located outside the insulating layer, and the sputtered UBM titanium-tungsten layer is located inside the sputtered UBM gold layer;

[0007] As a further technical solution of this utility model, the electroplated palladium layer is located outside the sputtered UBM gold layer, and there is an electroplated gold layer outside the electroplated palladium layer. The electroplated gold layer wraps around the outer edges of the sputtered UBM titanium-tungsten layer, the sputtered UBM gold layer, the electroplated palladium layer, and the electroplated gold layer.

[0008] As a further technical solution of this utility model, the insulating layer is silicon dioxide;

[0009] As a further technical solution of this utility model, the preparation of the palladium-gold bump gold-plated protective layer encapsulation structure mainly includes the following steps:

[0010] Wafer pretreatment: The incoming wafers are cleaned by two-fluid cleaning to ensure that the surfaces of the insulating layer and the aluminum pad conductive layer are clean and free of dust. The surfaces of the insulating layer and the aluminum pad conductive layer are then subjected to high-frequency etching to remove oxides.

[0011] Sputtered UBM layer: A dense and strongly adherent titanium-tungsten film is formed on the AL pad window using physical vapor deposition technology, forming a sputtered UBM titanium-tungsten layer; a gold film layer is then sputtered onto the titanium-tungsten layer using this technology.

[0012] Coating: Using a coating machine with high-precision spin coating technology, liquid photoresist is evenly coated onto the Au film on the wafer surface;

[0013] Exposure: The light source of the exposure machine passes through the photomask and projects the pattern onto the photoresist surface;

[0014] Development: The exposed photoresist surface of the wafer is sprayed with developing solution to reveal the exposed photoresist pattern. The photoresist in the exposed area is dissolved or retained to form the desired pattern.

[0015] Remove slag: Remove residual photolithography slag after development by plasma treatment to improve the uniformity and quality of subsequent processes;

[0016] Curing: Baking and curing the photoresist that has been developed on the wafer;

[0017] Electroplating: Different base electroplating solutions are selected to carry out the electroplating process, forming palladium and gold layers in succession;

[0018] Photoresist stripping: Wet stripping is used, which mainly uses chemical solvents to remove the photoresist through chemical reactions. The chemical solvents include a mixture of sulfuric acid and hydrogen peroxide, alkaline solutions and organic solvents (acetone).

[0019] Au etching: a chemical etching method that uses I2 and KI in combination to dissolve gold through a chemical reaction, forming a soluble gold-iodine complex.

[0020] Ti / W etching: Chemical etching, using H2O2 solution to form soluble complexes of metal ions through oxidation and complexation reaction of complexing agents, thereby removing the metal from the surface;

[0021] Cleaning: Scrubber cleaning uses two-fluid nozzle technology to efficiently remove fine particulate contaminants adhering to the wafer surface;

[0022] Repeat the above process of applying adhesive, exposure, and development;

[0023] Chemical plating: First, gold ions, reducing agents, complexing agents, and stabilizers are mixed in a certain proportion to prepare a gold plating solution. Then, the activated substrate is immersed in the gold plating solution. Under the masking of the photoresist pattern, the metal ions in the chemical plating solution will only undergo chemical reactions in the areas not covered by the photoresist. By controlling the temperature and time, the gold ions are reduced and deposited on the surface of the substrate, eventually forming a metal layer.

[0024] Annealing: a heat treatment process that improves the microstructure and properties of materials, reduces the hardness of metals, and meets the processing requirements of subsequent processes.

[0025] Compared with the prior art, the beneficial effects of this utility model are:

[0026] This invention adds a layer of gold plating as a protective layer to the palladium bump to prevent the palladium metal layer from reacting with the chemical solution, thereby effectively avoiding increased resistance, short circuits, or open circuits in the bump circuit. The IC can be reused after being acid-washed and recycled in the repair market. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the overall structure of this utility model.

[0028] Figure 2 This is a schematic diagram of the process flow in this utility model.

[0029] In the diagram: 1-Silicon wafer carrier, 2-Aluminum pad conductive layer, 3-Insulating layer, 4-Sputtered UBM titanium tungsten layer, 5-Sputtered UBM gold layer, 6-Electroplated palladium layer, 7-Electroplated gold layer, 8-Chemical gold plating layer. Detailed Implementation

[0030] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0031] Please see Figure 1-2 In this embodiment of the present invention, an acid-resistant palladium-gold IC package bump structure includes, from bottom to top, a silicon wafer carrier 1, an aluminum pad conductive layer 2, an insulating layer 3, a sputtered UBM titanium-tungsten layer 4, a sputtered UBM gold layer 5, an electroplated palladium layer 6, an electroplated gold layer 7, and an electroless gold plating layer 8; wherein, the aluminum pad conductive layer 2 is deposited on the surface of the silicon wafer carrier 1 by metal sputtering technology, and insulating layers 3 are disposed on both sides of the aluminum pad conductive layer 2 on the surface of the silicon wafer carrier 1, the sputtered UBM titanium-tungsten layer 4 is located outside the insulating layer 3, and the sputtered UBM titanium-tungsten layer 4 is located inside the sputtered UBM gold layer 5.

[0032] In this embodiment, the electroplated palladium layer 6 is located outside the sputtered UBM gold layer 5, and there is an electroplated gold layer 7 outside the electroplated palladium layer 6. The electroplated gold layer 8 wraps around the outer edges of the sputtered UBM titanium-tungsten layer 4, the sputtered UBM gold layer 5, the electroplated palladium layer 6 and the electroplated gold layer 7.

[0033] In this embodiment, the insulating layer 3 is silicon dioxide;

[0034] The working principle of this invention is as follows: First, the incoming wafer is pre-treated: the incoming wafer is cleaned by two-fluid cleaning to ensure that the surfaces of the insulating layer 3 and the aluminum pad conductive layer 2 are clean and free of dust. Then, a high-frequency etching process is performed on the surfaces of the insulating layer 3 and the aluminum pad conductive layer 2 to remove oxides. Next, a dense and strongly adherent titanium-tungsten film is formed on the AL pad using physical vapor deposition (PVD) technology, forming a sputtered UBM titanium-tungsten layer 4. A gold film layer is then sputtered onto the titanium-tungsten layer using the same technology, forming a sputtered UBM gold layer 5. Then, a high-precision spin-coating technique is used to uniformly coat the liquid photoresist onto the Au film on the wafer surface using a coating machine. The light source of the exposure machine projects the pattern onto the photoresist surface through a mask. A developing solution is sprayed onto the exposed photoresist surface to reveal the exposed photoresist pattern. The photoresist in the exposed area is dissolved or retained to form the desired pattern. Then, plasma treatment is used to remove residual photoresist dross after development, improving the uniformity and quality of subsequent processes. Finally, the developed photoresist on the wafer is baked and cured.

[0035] Next, different base plating solutions were selected for the electroplating process, forming a palladium layer 6 and a gold layer 7 sequentially. Then, a wet stripping method was used, primarily utilizing chemical solvents to remove the photoresist through a chemical reaction. These chemical solvents included a mixture of sulfuric acid and hydrogen peroxide, alkaline solutions, and organic solvents (acetone). Subsequently, a chemical etching method was used, employing I₂ and KI in combination to dissolve the gold through a chemical reaction, forming a soluble gold-iodine complex.

[0036] Next, chemical etching is used, employing H2O2 solution to form soluble complexes of metal ions through oxidation and complexing reactions with complexing agents, thereby removing the metal from the surface; then, a scrubber cleaning process using two-fluid nozzle technology is used to efficiently remove fine particulate contaminants adhering to the wafer surface; then, the above-mentioned processes of coating, exposure, and development are repeated.

[0037] After completion, gold ions, reducing agents, complexing agents, and stabilizers are mixed in a certain proportion to prepare a gold plating solution. Then, the activated substrate is immersed in the gold plating solution. Under the masking of the photoresist pattern, the metal ions in the plating solution will only undergo chemical reactions in the areas not covered by the photoresist. By controlling the temperature and time, the gold ions are reduced and deposited on the surface of the substrate, ultimately forming a metal layer.

[0038] Finally, heat treatment technology is used to improve the microstructure and properties of the material, thereby reducing the hardness of the metal and meeting the processing requirements of subsequent processes.

[0039] The above processing involves adding a layer of gold plating as a protective layer to the palladium bumps to prevent the palladium metal layer from reacting with the chemicals. This effectively avoids increased resistance, short circuits, or open circuits in the bump circuitry. The ICs can then be recycled and reused in the repair market after acid cleaning.

[0040] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0041] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A palladium-gold IC package bump structure resistant to acid washing, characterized in that: The structure includes, from bottom to top, a silicon wafer carrier (1), an aluminum pad conductive layer (2), an insulating layer (3), a sputtered UBM titanium tungsten layer (4), a sputtered UBM gold layer (5), an electroplated palladium layer (6), an electroplated gold layer (7), and an electroplated gold layer (8); wherein, the aluminum pad conductive layer (2) is deposited on the surface of the silicon wafer carrier (1) by metal sputtering technology, and the insulating layer (3) is disposed on both sides of the aluminum pad conductive layer (2) on the surface of the silicon wafer carrier (1), the sputtered UBM titanium tungsten layer (4) is located outside the insulating layer (3), and the sputtered UBM titanium tungsten layer (4) is located inside the sputtered UBM gold layer (5).

2. The acid-resistant palladium-gold IC package bump structure according to claim 1, characterized in that: The electroplated palladium layer (6) is located outside the sputtered UBM gold layer (5), and there is an electroplated gold layer (7) outside the electroplated palladium layer (6). The electroplated gold layer (8) wraps around the outer edges of the sputtered UBM titanium tungsten layer (4), the sputtered UBM gold layer (5), the electroplated palladium layer (6), and the electroplated gold layer (7).

3. The acid-resistant palladium-gold IC package bump structure according to claim 1, characterized in that: The insulating layer (3) is silicon dioxide.

Images