An electromagnetic shielding chip stack package structure

Abstract

The application relates to the field of semiconductor technology and discloses an electromagnetic shielding chip stack packaging structure, which comprises a frame, a base island and a pin; a first chip is attached to the upper surface of the base island; a first plastic packaging layer covers the frame and the first chip and exposes the lower surface of the frame; a second chip is attached to the upper surface of the first plastic packaging layer; a second plastic packaging layer is arranged on the upper surface of the first plastic packaging layer in a stacked mode and covers the second chip; a vertical interconnection structure is located in the first plastic packaging layer and is electrically connected to the pin and the second chip at two ends; an electromagnetic shielding layer is located on the side wall surface of the first plastic packaging layer and the second plastic packaging layer; an electromagnetic shielding wire is located in the first plastic packaging layer and is electrically connected to the electromagnetic shielding layer; and a grounding wire is located in the first plastic packaging layer and is electrically connected to the grounding pin and the electromagnetic shielding layer at two ends. The structure can be applied to an existing lead frame and realizes electromagnetic shielding of multiple chips in the vertical direction.

Description

Technical Field

[0001] This utility model belongs to the technical field of semiconductors, and in particular relates to an electromagnetic shielding chip stacking and packaging structure. Background Technology

[0002] With the rapid development of packaging technology, packaged products are gradually moving towards miniaturization, high density, and high integration. High-frequency chips generate strong electromagnetic waves during transportation and transmission, which often interfere with or cause noise to other chips inside the package or to electronic components outside the package. Moreover, as the integration of electronic components becomes increasingly high, the distance between signal transmission lines between these components also becomes shorter, leading to increasingly serious electromagnetic interference problems between chips, both inside and outside the package.

[0003] Existing electromagnetic shielding technology using electromagnetic shielding wires can only be used in substrate-based packages. Because the substrate contains internal wiring, the bonding wires spanning the chip surface can be connected to a single ground signal through these internal circuitry, thus achieving electromagnetic shielding. However, for leadframe-based packages, the leadframe only has pins. These pins are used to transmit various signals between the chip and external circuits, and each pin transmits a different electrical signal. Since the electromagnetic shielding wire only transmits a single ground signal, it is impossible to achieve electromagnetic shielding by creating a cross-chip electromagnetic shielding line by bonding wires to the pins. Utility Model Content

[0004] The purpose of this invention is to solve at least one problem of the prior art and to propose an electromagnetic shielding chip stacking packaging structure.

[0005] To achieve the above objectives, this utility model proposes an electromagnetic shielding chip stacked packaging structure, comprising:

[0006] A frame, the frame including a base island and pins spaced apart from the base island, the pins including grounded pins and non-grounded pins;

[0007] The first chip is mounted on the surface of the base island;

[0008] A first molding layer covers the frame and the first chip, and exposes the lower surface of the frame;

[0009] The second chip is mounted on the upper surface of the first molding layer;

[0010] A second molding compound layer is stacked on the upper surface of the first molding compound layer and covers the second chip;

[0011] A vertical interconnect structure is located within the first molding compound layer, with one end of the vertical interconnect structure electrically connected to a pin and the other end of the vertical interconnect structure exposed on the upper surface of the first molding compound layer and electrically connected to the second chip.

[0012] An electromagnetic shielding layer is located on the sidewall surface of the first molding layer and the second molding layer, and the electromagnetic shielding layer is isolated from the pins;

[0013] An electromagnetic shielding wire is located within the first molding layer and spans across the side of the first chip away from the frame, and the end of the electromagnetic shielding wire is electrically connected to the electromagnetic shielding layer.

[0014] The grounding wire is located inside the first plastic encapsulation layer, and its two ends are electrically connected to the grounding pin and the electromagnetic shielding layer, respectively.

[0015] As an optional implementation, the vertical interconnect structure is a vertical bonding wire, which is vertically disposed on the upper surface of the ground pin and the non-ground pin. The end of the vertical bonding wire away from the pin is exposed on the upper surface of the first molding compound and is electrically connected to the second chip.

[0016] As an optional implementation, the first end of the vertical interconnect structure is electrically connected to a grounded pin or a non-grounded pin, and the second end of the vertical interconnect structure is directly electrically connected to the second chip.

[0017] As an optional implementation, the first end of the vertical interconnect structure is electrically connected to a grounded pin or a non-grounded pin, and the second end of the vertical interconnect structure is electrically connected to the second chip via a lead, the lead being located above the electromagnetic shielding line.

[0018] As an optional implementation, the vertical interconnect structure is a conductive post, which is vertically disposed on the upper surface of the grounded pin and the ungrounded pin, with the end of the conductive post away from the pin exposed on the upper surface of the first molding layer.

[0019] As an optional implementation, the electromagnetic shielding layer on the side of the first molding layer and the electromagnetic shielding line constitute a five-sided electromagnetic shielding structure of the first chip.

[0020] As an optional implementation, the plane containing the lowest point of the electromagnetic shielding layer located on the sidewall of the first molding layer is higher than the plane containing the upper surface of the pin.

[0021] As an optional implementation, the top plane of the electromagnetic shielding layer located on the sidewall of the second molding layer is positioned higher than the top surface of the second chip, and the plane containing the lowest point of the electromagnetic shielding layer located on the sidewall of the first molding layer is lower than the plane containing the upper surface of the first chip.

[0022] As an optional implementation, the first chip is electrically connected to the grounded pin and the non-grounded pin via leads, and the electromagnetic shielding wire is located above the leads and the first chip.

[0023] As an optional implementation, the electromagnetic shielding wires are arranged in a grid pattern within the first molding layer.

[0024] As an optional implementation, the electromagnetic shielding wire is unidirectionally disposed within the first encapsulation layer.

[0025] As an optional implementation, the grounding pins and ungrounding pins are arranged symmetrically around the base island.

[0026] As an optional implementation, the grounding pin and the non-grounding pin are respectively located on both sides of the base island.

[0027] As an optional implementation, the sidewall surfaces of the first and second molding layers are provided with stepped grooves from bottom to top, the depth of the stepped grooves being greater than the height of the first molding layer, and the electromagnetic shielding layer being disposed on the surface of the stepped grooves of the first and second molding layers.

[0028] As an optional implementation, the electromagnetic shielding layer covers the sidewall surfaces of the first molding layer and the second molding layer. The lower surface of the electromagnetic shielding layer is lower than the lower surface of the first chip and higher than the upper surface of the pin. The upper surface of the electromagnetic shielding layer is higher than the upper surface of the second chip.

[0029] As an optional implementation, the first molding layer has a stepped opening on the surface edge near the frame side, so that the electromagnetic shielding layer is isolated from the pin.

[0030] As an optional implementation, a gap is provided between the outer wall surface of the pin near the first molding layer and the inner wall surface of the electromagnetic shielding layer, or a gap is provided between the lower surface of the electromagnetic shielding layer and the upper surface of the pin.

[0031] The beneficial effects of this utility model are as follows: By setting an electromagnetic shielding line across the top of the first chip within the first molding compound, and setting an electromagnetic shielding layer on the side surfaces of the first and second molding compounds, the electromagnetic shielding layer is electrically connected to the grounding wire and the electromagnetic shielding line. The second chip is positioned above the first chip, enabling the chip stacking structure to achieve electromagnetic shielding using existing lead frames. Through the combined action of the electromagnetic shielding layer and the electromagnetic shielding line, electromagnetic shielding of multiple chips in the vertical direction is achieved, and the first chip can achieve electromagnetic shielding on five sides. By electrically connecting the electromagnetic shielding layer to the grounding wire and the electromagnetic shielding line, all electromagnetic shielding lines are interconnected and grounded, without the need for direct contact between the electromagnetic shielding line and the grounding wire or grounding pin to achieve conductivity, which can significantly reduce the difficulty of wiring the electromagnetic shielding lines.

[0032] The features and advantages of this utility model will be described in detail through embodiments and accompanying drawings. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of an electromagnetic shielding chip stacking structure according to an embodiment of the present invention.

[0034] Figure 2 This is a schematic diagram of another electromagnetic shielding chip stacking structure according to an embodiment of the present invention.

[0035] Figure 3 This is a schematic diagram of the arrangement of multiple chip stacking structures according to an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of step S20 of the chip stacking structure packaging method according to an embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of step S30 of the chip stacking structure packaging method according to an embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of step S40 of the chip stacking structure packaging method according to an embodiment of the present invention.

[0039] Figure 7 This is a schematic diagram of step S50 of the chip stacking structure packaging method according to an embodiment of the present invention.

[0040] Figure 8 This is a schematic diagram of step S60 of the chip stacking structure packaging method according to an embodiment of the present invention.

[0041] Figure 9 This is a schematic diagram of step S70 of the chip stacking structure packaging method according to an embodiment of the present invention.

[0042] Figure 10This is a schematic diagram of step S80 of the chip stacking structure packaging method according to an embodiment of the present invention.

[0043] Figure 11 This is a schematic diagram of another electromagnetic shielding chip stacking structure according to an embodiment of the present invention.

[0044] Figure 12 This is a schematic diagram of another electromagnetic shielding chip stacking structure according to an embodiment of the present invention.

[0045] In the diagram: 1. Base island; 2. Non-grounded pin; 3. Grounded pin; 4. First molding compound; 5. Second molding compound; 6. First chip; 7. Second chip; 8. Electromagnetic shielding wire; 9. Vertical interconnect structure; 10. Electromagnetic shielding layer; 11. Lead wire; 12. Groove; 13. Grounding wire. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. In the description of this application, it should be noted that the terms "inner," "outer," etc., indicating orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships commonly used when the product of this application is in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0047] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0048] The present invention will now be described in detail with reference to the accompanying drawings.

[0049] See Figures 1 to 9 This embodiment provides an electromagnetic shielding chip stacked packaging structure, including:

[0050] The frame includes a base island 1 and pins spaced apart from the base island, including a grounded pin 3 and a non-grounded pin 2;

[0051] The first chip 6 is mounted on the upper surface of the base island 1;

[0052] A first molding layer 4 covers the frame and the first chip 6, and exposes the lower surface of the frame;

[0053] The second chip 7 is mounted on the upper surface of the first molding layer 4;

[0054] The second molding layer 5 is stacked on the upper surface of the first molding layer 4 and covers the second chip 7;

[0055] A vertical interconnect structure 9 is located within the first molding compound 4, with one end of the vertical interconnect structure 9 electrically connected to a pin and the other end of the vertical interconnect structure 9 exposed on the upper surface of the first molding compound 4 and electrically connected to the second chip 7.

[0056] Electromagnetic shielding layer 10 is located on the sidewall surface of the first molding layer 4 and the second molding layer 5, and is isolated from the pins.

[0057] The electromagnetic shielding wire 8 is located inside the first molding layer 4 and spans across the side of the first chip 6 away from the frame 1, and the end of the electromagnetic shielding wire 8 is electrically connected to the electromagnetic shielding layer 10.

[0058] Grounding wire 13 is located inside the first plastic sealing layer 4, and its two ends are electrically connected to the grounding pin and the electromagnetic shielding layer, respectively.

[0059] The upper surface of each component in this electromagnetic shielding chip stacked packaging structure is the top surface along the thickness direction, with... Figure 1 Taking the electromagnetic shielding chip stacked packaging structure as an example, the vertical direction perpendicular to the horizontal direction of the base island 1 is the thickness direction of the cavity electromagnetic shielding chip stacked packaging structure. The upper surface of the base island 1 is the top horizontal surface perpendicular to the thickness direction of the base island 1, and the lower surface of the base island 1 is the bottom horizontal surface perpendicular to the thickness direction of the base island 1. The upper surfaces of the first chip 6, the second chip 7, the electromagnetic shielding layer 10, the first molding layer 4, and the second molding layer 5 are the surfaces away from the frame.

[0060] The pins can be placed on one or both sides of the base island 1 according to the packaging requirements, or the pins can be placed around the base island 1.

[0061] The grounding pin 3 can be located on one side of the base island 1, and grounding pins can be set on multiple sides of the base island to facilitate the grounding pin to be electrically connected to the adjacent electromagnetic shielding layer 10 through a grounding wire.

[0062] To facilitate the mounting of the first chip 6, the size of the base island 1 is not smaller than the size of the first chip 6. Specifically, in this embodiment, the size of the base island 1 is larger than the size of the first chip 6.

[0063] In other embodiments, the number of base islands 1 is one, and multiple first chips 6 are disposed on the base island 1.

[0064] In other embodiments, the number of base islands 1 may also be multiple, corresponding to multiple first chips 6.

[0065] The number of pins on the four sides of the base island 1 can be set to one, two, three, four or more, depending on the packaging requirements. The number of pins on the outer sides of each side of the base island 1 can be set to the same or different.

[0066] The electrical connection terminal of the first chip 6 is located on the top surface of the chip, or it can be located on the bottom surface of the chip; the electrical connection terminal of the second chip 7 is located on the top surface or the bottom surface of the chip.

[0067] Specifically, in this embodiment, the electrical connection terminal of the first chip 6 is located on the top surface of the chip and is electrically connected to other structures through a lead wire method. The electrical connection terminal of the second chip 7 is located on the bottom surface of the chip and is electrically connected to other structures in a flip-chip manner.

[0068] In other embodiments, the electrical connection terminals of the first chip 6 and the second chip 7 are located on the top surface of the chip, and both the first chip 6 and the second chip 7 are electrically connected to other structures by means of leads.

[0069] In other embodiments, when the electrical connection terminals of the first chip 6 and the second chip 7 are located on the bottom surface of the chip, the first chip 6 and the second chip 7 are packaged using a flip-chip method.

[0070] The first chip 6 and the second chip 7 can be of the type of high-frequency chip, power chip, logic chip, or memory chip, etc. The first chip 6 and the second chip 7 can be of the same type or different types. In some embodiments, the logic chip can include gate arrays, cell substrate arrays, embedded arrays, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), central processing units (CPUs), microprocessor units (MPUs), microcontroller units (MCUs), logic integrated circuits (ICs), application processors (APs), display driver ICs (DDIs), radio frequency (RF) chips, power supply chips, or complementary metal-oxide-semiconductor (CMOS) image sensors. In some embodiments, the memory chip can include volatile memory chips (such as dynamic random access memory (DRAM) or static RAM (SRAM)) or non-volatile memory chips (such as flash memory (Flash), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (ReRAM)). In a specific embodiment, the memory chip can include high-bandwidth memory (HBM) of a DRAM chip.

[0071] The electromagnetic shielding layer 10 is formed of a metallic material through sputtering or electroplating processes. The metallic material includes copper, aluminum, stainless steel, etc.

[0072] The frame can be a conventional lead frame. The frame has good thermal and electrical conductivity, which is beneficial for heat dissipation of the chip and for electrical connection between the pins and the chip. The frame material includes, but is not limited to, any one or more of iron, nickel, gold, and copper. During operation, the first chip 6 transfers heat to the base island 1, which then dissipates the heat from the first chip 6, thereby reducing its temperature.

[0073] In this embodiment, the electromagnetic shielding wire 8 is located inside the first molding layer 4 and spans across the side of the first chip 6 away from the frame 1. The end of the electromagnetic shielding wire 8 is electrically connected to the electromagnetic shielding layer 10. The electromagnetic shielding wire 8 includes multiple single wires, and the two ends of the multiple single wires are respectively electrically connected to the electromagnetic shielding layer 10 which is disposed opposite to them. The electromagnetic shielding wire 8, the electromagnetic shielding layer 10, the grounding wire 6, and the grounding pin 12 are grounded.

[0074] In one specific embodiment, multiple electromagnetic shielding wires 8 are arranged in a grid pattern within the first molding layer 4 to reduce external electromagnetic interference to the first chip 6.

[0075] In another embodiment, the multiple electromagnetic shielding wires 8 may or may not be in contact at the locations where they form cross nodes.

[0076] In other embodiments, multiple electromagnetic shielding wires 8 are arranged in a parallel line structure and are unidirectionally disposed within the first plastic encapsulation layer 4.

[0077] See Figure 1 In this embodiment, the first end of the vertical interconnect structure 9 (the end closest to the pin) is electrically connected to the ground pin 3 or the non-ground pin 2, and the second end of the vertical interconnect structure 9 is directly electrically connected to the second chip 7.

[0078] See Figure 2 In this embodiment, the first end of the vertical interconnect structure 9 is electrically connected to the ground pin 3 or the non-ground pin 2, and the second end of the vertical interconnect structure 9 is electrically connected to the second chip 7 through the lead 11.

[0079] The lead wire 11 and the vertical interconnect structure 9 are made of gold, copper, or aluminum. Other conductive materials may also be used, provided that conductivity requirements are met.

[0080] In this embodiment, the second end of the vertical interconnect structure 9 is exposed on the upper surface of the first molding layer 4, and the surface of the second end of the vertical interconnect structure 9 is provided with a welding structure or a wiring structure.

[0081] Specifically, in this embodiment, the vertical interconnect structure 9 is a vertical bonding wire, which is vertically disposed on the upper surface of the grounding pin 3 and the ungrounded pin 2, and the end of the vertical bonding wire away from the pin is exposed on the upper surface of the first plastic sealing layer 4.

[0082] In other embodiments, the vertical interconnect structure 9 is a conductive post, which is vertically disposed on the upper surface of the grounded pin 2 and the ungrounded pin 3, with the end of the conductive post away from the pin exposed on the upper surface of the first molding layer 4.

[0083] In this embodiment, the electromagnetic shielding layer 10 on the side of the first molding layer 4 and the second molding layer 5, and the electromagnetic shielding line 8 constitute the five-sided electromagnetic shielding structure of the second chip 7, and the electromagnetic shielding layer 10 on the side of the first molding layer 4 and the electromagnetic shielding line 8 constitute the five-sided electromagnetic shielding structure of the first chip 6.

[0084] On the one hand, this structure can achieve vertically divided electromagnetic shielding of multiple chips. On the other hand, the first chip has a 5-sided electromagnetic shielding structure, and different electromagnetic shielding requirements can be achieved by reasonably selecting the types of the first chip and the second chip.

[0085] In this embodiment, the plane where the lowest point of the electromagnetic shielding layer 10 is located on the sidewall of the first molding layer 4 is higher than the plane where the upper surface of the pin is located.

[0086] In this embodiment, the top plane of the electromagnetic shielding layer 10 located on the sidewall of the second molding layer 5 is higher than the plane of the top surface of the second chip 7, and the plane of the lowest point of the electromagnetic shielding layer 10 located on the sidewall of the first molding layer 4 is lower than the plane of the upper surface of the first chip 6.

[0087] The first molding layer 4 covers the first chip 6, the vertical interconnect structure 9, the ground wire 13, the frame, and the electromagnetic shielding wire 8, which can prevent bridging or short circuits with other circuit components.

[0088] See Figure 1 and Figure 2 In this embodiment, the second molding layer 5 covers the second chip 7, which can prevent bridging or short circuits with other circuit components.

[0089] See Figure 1 and Figure 2 In this embodiment, the first chip 6 is electrically connected to the ground pin 3 and the non-ground pin 2 via the lead 11. The electromagnetic shielding line 8 is located above the lead 11 and the first chip 6, so that the electromagnetic shielding line 8 can avoid the first chip 6, and a short circuit will not occur between the electromagnetic shielding line 8, the lead 11 and the first chip 6.

[0090] See Figure 1 and Figure 3 In this embodiment, the electromagnetic shielding wires 8 are arranged in a grid pattern within the first molding layer 4. The grid-structured electromagnetic shielding wires 8 are used to block electromagnetic interference from the top of the first chip 6.

[0091] In other embodiments, the electromagnetic shielding lines 8 can also be arranged unidirectionally in parallel lines within the first molding layer 4, which can also reduce the electromagnetic interference received by the first chip 6 from the outside.

[0092] In this embodiment, the upper surface of the base island 1 is square in shape, and the grounding pin 3 and the non-grounding pin 2 are arranged symmetrically around the base island 1.

[0093] In other embodiments, the upper surface of the base island 1 may also be configured in other shapes, such as rectangle, circle or pentagon, with grounding pin 3 and non-grounding pin 2 disposed on both sides of the base island 1.

[0094] In this embodiment, refer to Figure 1 and Figure 2 The sidewall surfaces of the first molding layer 4 and the second molding layer 5 are provided with stepped grooves from bottom to top. The depth of the stepped grooves is greater than the height of the first molding layer 4. The electromagnetic shielding layer 10 is disposed on the surface of the stepped grooves of the first molding layer 4 and the second molding layer 5. The depth direction of the stepped grooves is consistent with the height direction of the first molding layer 4 and the second molding layer 5, and the height direction of the first molding layer 4 and the second molding layer 5 is vertically perpendicular to the frame.

[0095] In other embodiments, see Figure 11 , Figure 12 The electromagnetic shielding layer 10 covers the sidewall surfaces of the first molding layer 4 and the second molding layer 5. The lower surface of the electromagnetic shielding layer 10 is lower than the lower surface of the first chip 6 and higher than the upper surface of the pin. The upper surface of the electromagnetic shielding layer 10 is higher than the upper surface of the second chip 7. Therefore, it is not necessary to set a stepped groove on the sidewall of the first molding layer 4 and the second molding layer 5 during packaging.

[0096] For ease of production, the upper surface of the electromagnetic shielding layer 10 is lower than the upper surface of the second molding layer 5. The electromagnetic shielding layer 10 can be integrally wrapped around the sidewall surfaces of the first molding layer 4 and the second molding layer 5.

[0097] In this embodiment, refer to Figure 1 , Figure 2 The first molding layer 4 has a stepped opening on its surface edge near the frame, which isolates the pins from the electromagnetic shielding layer 10. The stepped opening can be formed by cutting.

[0098] In other embodiments, see Figure 11 , Figure 12 A gap is provided between the outer wall surface of the pin near the first molding layer 4 and the inner wall surface of the electromagnetic molding layer 10, or a gap is provided between the lower surface of the electromagnetic shielding layer 10 and the upper surface of the pin. The gap ensures that the electromagnetic shielding layer 10 is isolated from the pin. The gap can be formed by cutting during packaging.

[0099] See Figure 1 , Figures 4 to 10 This embodiment also provides a packaging method for an electromagnetic shielding chip stacked packaging structure, including the following steps:

[0100] S10, a frame is provided, the frame including multiple frame units and connecting ribs connecting each frame unit, each frame unit including a base island 1 and pins spaced apart from the base island 1, the pins including grounded pins 3 and non-grounded pins 2;

[0101] S20, the first chip 6 is mounted on the upper surface of the base island 1;

[0102] S30, wiring of vertical interconnection structure 9, electromagnetic shielding line 8 and grounding line 13 is formed on the upper surface of the frame unit;

[0103] S40, the first chip 6, frame, vertical interconnect structure 9, electromagnetic shielding line 8 and grounding line 13 are first encapsulated to form the first encapsulation layer 4, and the end of the vertical interconnect structure 9 away from the frame is exposed.

[0104] S50, a second chip 7 is mounted on the upper surface of the first molding layer 4. The second chip 7 is electrically connected to the vertical interconnect structure 9. The upper surface of the first molding layer 4 and the second chip 7 are then molded a second time to form the second molding layer 5.

[0105] S60, using a single cutting process, a groove 12 is formed by half-cutting on the back side of the relative grounding pin 3 (cutting direction is from the lower surface of the frame unit upward into the second plastic sealing layer 5), so that the electromagnetic shielding wire 8 and the grounding wire 13 are exposed from the side wall of the groove 12.

[0106] S70, an electromagnetic shielding layer 10 is formed on the inner surface of the groove 12, and the electromagnetic shielding layer 10 is electrically connected to the electromagnetic shielding wire 8, the grounding wire 13 and the pin.

[0107] S80, using a secondary cutting process to cut part of the pins and electromagnetic shielding layer 10 within the groove 12, separating the electromagnetic shielding layer 10 from the pins. In step S80, the cutting width is greater than the cutting width in step S60, and the cutting depth in step S80 is greater than the height of the pins.

[0108] In step S90, the molding layer and electromagnetic shielding layer 10 of the groove 12 are cut using a three-stage cutting process to finally obtain a single chip stack structure. The cutting width in step S90 is smaller than the cutting width in step S60.

[0109] In step S30, when wiring, both ends of the electromagnetic shielding wire 8 can be connected to the connecting ribs on the outside of the frame unit; one end of the grounding wire is connected to the upper surface of the grounding pin 3 near the connecting rib, and the other end is connected to the upper surface of the corresponding grounding pin 3 in the adjacent frame unit near the connecting rib, or connected to the connecting rib on the outside of the frame unit.

[0110] In step S40, after the first molding, the upper surface of the first molding layer 4 is polished to expose the upper end of the vertical interconnect structure 9.

[0111] During molding, the molding layer material is at least one of epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. Alternatively, the molding layer material may also include at least one of polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyimide, ethylene-vinyl acetate copolymer, or polyvinyl alcohol. The molding layer may also contain inorganic or organic fillers. The materials of the first molding layer 4 and the second molding layer 5 may be the same or different.

[0112] When the second chip 7 and the vertical interconnect structure 9 are electrically connected by leads 11, in step S50 of the packaging method of this embodiment, it is also necessary to wire the vertical interconnect structure 9 and the second chip 7, and the two ends of the leads are electrically connected to the vertical bonding wire and the second chip 7.

[0113] When the first chip 6 and the pin are electrically connected by the lead 11, in step S30 of the packaging method of this embodiment, the lead 11 also needs to be wired. One end of the lead is electrically connected to the first chip 6, and the other end of the lead 11 is electrically connected to the ground pin 3 or the non-grounded pin 2.

[0114] When the electromagnetic shielding layer 10 covers the sidewall surfaces of the first molding layer 4 and the second molding layer 5, and there is no need to set step grooves in the second molding layer 5 and the first molding layer 4, in step S90 of the packaging method of this embodiment, the protruding part of the second molding layer 5 corresponding to the groove 12 and the electromagnetic shielding layer 10 are cut from top to bottom using a three-cutting process, and finally a single chip stack structure is obtained.

[0115] The above embodiments are illustrative of the present invention and are not intended to limit the present invention. Any simple modifications to the present invention are within the protection scope of the present invention.

Claims

1. An electromagnetic shielded chip stack package structure, characterized by ,include: A frame, the frame including a base island and pins spaced apart from the base island, the pins including grounded pins and non-grounded pins; The first chip is mounted on the surface of the base island; A first molding layer covers the frame and the first chip, and exposes the lower surface of the frame; The second chip is mounted on the upper surface of the first molding layer; A second molding compound layer is stacked on the upper surface of the first molding compound layer and covers the second chip; A vertical interconnect structure is located within the first molding compound layer, with one end of the vertical interconnect structure electrically connected to a pin and the other end of the vertical interconnect structure exposed on the upper surface of the first molding compound layer and electrically connected to the second chip. An electromagnetic shielding layer is located on the sidewall surface of the first molding layer and the second molding layer, and the electromagnetic shielding layer is isolated from the pins; An electromagnetic shielding wire is located within the first molding layer and spans across the side of the first chip away from the frame, and the end of the electromagnetic shielding wire is electrically connected to the electromagnetic shielding layer. The grounding wire is located inside the first plastic encapsulation layer, and its two ends are electrically connected to the grounding pin and the electromagnetic shielding layer, respectively.

2. The electromagnetic shielded chip stack package structure of claim 1, wherein: The vertical interconnect structure is a vertical bonding wire, which is vertically disposed on the upper surface of the ground pin and the non-ground pin. The end of the vertical bonding wire away from the pin is exposed on the upper surface of the first molding layer and is electrically connected to the second chip.

3. The electromagnetic shielded chip stack package structure of claim 1 or 2, wherein: The first end of the vertical interconnect structure is electrically connected to a grounded pin or a non-grounded pin, and the second end of the vertical interconnect structure is directly electrically connected to the second chip.

4. The electromagnetic shielded chip stack package structure of claim 1 or 2, wherein: The first end of the vertical interconnect structure is electrically connected to a grounded pin or a non-grounded pin, and the second end of the vertical interconnect structure is electrically connected to the second chip via a lead, which is located above the electromagnetic shielding line.

5. The electromagnetic shielded chip stack package structure of claim 1, wherein: The vertical interconnect structure is a conductive post, which is vertically disposed on the upper surface of the grounded pin and the ungrounded pin, with the end of the conductive post away from the pin exposed on the upper surface of the first molding layer.

6. The electromagnetic shielded chip stack package structure of claim 1, wherein: The electromagnetic shielding layer on the side of the first molding layer and the electromagnetic shielding line constitute the five-sided electromagnetic shielding structure of the first chip.

7. The electromagnetic shielded chip stack package structure of claim 1, wherein: The plane containing the lowest point of the electromagnetic shielding layer located on the sidewall of the first molding layer is higher than the plane containing the upper surface of the pin.

8. The electromagnetic shielded chip stack package structure of claim 1, wherein: The top plane of the electromagnetic shielding layer located on the sidewall of the second molding layer is higher than the top surface of the second chip, and the plane containing the lowest point of the electromagnetic shielding layer located on the sidewall of the first molding layer is lower than the plane containing the upper surface of the first chip.

9. The electromagnetic shielded chip stack package structure of claim 1, wherein: The first chip is electrically connected to the grounded pin and the non-grounded pin via leads, and the electromagnetic shielding wire is located above the leads and the first chip.

10. The electromagnetic shielding chip stacked packaging structure as described in claim 1, characterized in that: The electromagnetic shielding wires are arranged in a grid pattern within the first plastic encapsulation layer.

11. The electromagnetic shielding chip stacked packaging structure as described in claim 1, characterized in that: The electromagnetic shielding wire is unidirectionally disposed within the first plastic encapsulation layer.

12. The electromagnetic shielding chip stacked packaging structure as described in claim 1, characterized in that: The grounding pins and ungrounding pins are arranged symmetrically around the base island.

13. The electromagnetic shielding chip stacked packaging structure as described in claim 1, characterized in that: The grounding pins and non-grounding pins are located on both sides of the base island.

14. The electromagnetic shielding chip stacked packaging structure as described in claim 1, characterized in that: The sidewall surfaces of the first and second molding layers are provided with stepped grooves from bottom to top, and the depth of the stepped grooves is greater than the depth of the first molding layer. The electromagnetic shielding layer is disposed on the surface of the stepped grooves of the first and second molding layers.

15. The electromagnetic shielding chip stacked packaging structure as described in claim 1, characterized in that: The electromagnetic shielding layer covers the sidewall surfaces of the first molding layer and the second molding layer. The lower surface of the electromagnetic shielding layer is lower than the lower surface of the first chip and higher than the upper surface of the pin. The upper surface of the electromagnetic shielding layer is higher than the upper surface of the second chip.

16. The electromagnetic shielding chip stacked packaging structure as described in claim 1, characterized in that: The first molding layer has a stepped opening on the surface edge near the frame side, which isolates the electromagnetic shielding layer from the pins.

17. The electromagnetic shielding chip stacked packaging structure as described in claim 1, characterized in that: A gap is provided between the outer wall surface of the pin near the first molding layer and the inner wall surface of the electromagnetic shielding layer, or a gap is provided between the lower surface of the electromagnetic shielding layer and the upper surface of the pin.

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