Chip packaging structure

By using a chip packaging structure with a specific angle layout and wide and narrow pin design, the problems of large size, poor heat dissipation, complex process and low reliability of traditional three-phase intelligent power modules are solved, achieving high-efficiency production and excellent heat dissipation performance and reliability.

CN224419267UActive Publication Date: 2026-06-26INNOSCIENCE (SHENZHEN) SEMICON CO LTD
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Patent Information

Application Number
CN202521878116.5
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-08-29
Publication Date
2026-06-26
Estimated Expiration
2035-08-29

AI Technical Summary

Technical Problem

Traditional three-phase intelligent power modules have large packaging volumes, making them unsuitable for tape and reel packaging, resulting in low production efficiency; they also have high thermal resistance, affecting performance; large chip spacing necessitates hybrid bonding processes, leading to high costs and low yields; and the packaging process is prone to stress, impacting reliability.

Method used

The chip packaging structure with a specific angle layout includes a first die-carrying stage and a second die-carrying stage, which compactly arranges driver chips and power chips. It uses a wide and narrow pin design and interconnect structure to optimize thermal management and electrical performance, and reduce process complexity and cost.

Benefits of technology

This achieves reduced packaging size, improved production efficiency and reliability, enhanced heat dissipation, reduced costs, increased production yield, and improved module stability.

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Abstract

The utility model relates to a chip packaging structure. The chip packaging structure comprises a first slide holder, a second slide holder and a chip assembly, the first slide holder is provided with a first mounting area and a second mounting area which are arranged at an interval along a first direction, the second slide holder is provided with a third mounting area, and the third mounting area and the first mounting area are arranged at an interval along a second direction. The chip assembly comprises a driving chip arranged in the second installation area, a first power chip arranged in the first installation area and a second power chip arranged in the third installation area. Wherein the first direction is the extension direction of the center connecting line of the first power chip and the driving chip, the second direction is the extension direction of the center connecting line of the first power chip and the second power chip, and the included angle between the two directions is smaller than 90 degrees. By optimizing the relative position and the included angle of the mounting areas on the slide holder, more compact chip layout is realized, the packaging volume is effectively reduced, and the heat dissipation performance and the packaging reliability are improved.
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