Chip package structure

Abstract

The application relates to a chip packaging structure, which comprises a first carrier substrate, a second carrier substrate and a chip assembly. The first carrier substrate is provided with a first mounting area and a second mounting area which are arranged at intervals along a first direction, and the second carrier substrate is provided with a third mounting area which is arranged at intervals with the first mounting area along a second direction. The chip assembly comprises a driving chip arranged on the second mounting area, a first power chip arranged on the first mounting area and a second power chip arranged on the third mounting area. The first direction is the extension direction of the center line of the first power chip and the driving chip, the second direction is the extension direction of the center line of the first power chip and the second power chip, and the angle between the two directions is less than 90 DEG. The relative position and the angle of the mounting areas on the carrier substrate are optimized, so that a more compact chip layout is realized, the packaging volume is effectively reduced, and the heat dissipation performance and the packaging reliability are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more particularly to a chip packaging structure. Background Technology

[0002] Traditional three-phase intelligent power modules typically use DIP packaging, integrating multiple driver chips and power devices. This approach has significant drawbacks: First, the package size is large, making tape and reel packaging and automated surface mount technology (SMT) production impossible, resulting in low production efficiency; second, the module has high thermal resistance, affecting performance; third, the large chip spacing requires a complex bonding process using a mix of gold and copper wires, leading to high costs and low yields; finally, the large package size is prone to generating significant stress, causing reliability issues such as delamination. Utility Model Content

[0003] This application provides a chip packaging structure for carrying a chip, including:

[0004] The first mounting stage is provided with a first mounting area and a second mounting area arranged at intervals along a first direction;

[0005] The second mounting stage is provided with a third mounting area; the third mounting area is arranged at a distance from the first mounting area along a second direction.

[0006] A chip assembly, comprising a driver chip disposed in the second mounting area, a first power chip disposed in the first mounting area, and a second power chip disposed in the third mounting area;

[0007] The first direction is the extension direction of the line connecting the center point of the first power chip and the center point of the driver chip, and the second direction is the extension direction of the line connecting the center point of the first power chip and the center point of the second power chip. The angle between the first direction and the second direction is less than 90°.

[0008] In one embodiment, the first stage includes a first support portion and a second support portion, the first mounting area is disposed on the first support portion, and the second mounting area is disposed on the second support portion;

[0009] The second stage includes a third support portion and an extension portion, wherein the third mounting area is disposed on the third support portion; wherein,

[0010] A groove is formed at the junction of the first support portion and the second support portion, and a protrusion is formed at the junction of the third support portion and the extension portion. The groove is adapted to the shape of the protrusion so that the first substrate stage and the second substrate stage fit together tightly.

[0011] In one embodiment, the groove is an arc-shaped groove, and the protrusion is a matching arc-shaped protrusion.

[0012] In one embodiment, the extension is inclined in a third direction relative to the third mounting portion, and the angle between the third direction and the second direction is smaller than the angle between the first direction and the second direction.

[0013] In one embodiment, the chip packaging structure further includes:

[0014] Multiple first pins are disposed on the side of the second carrier portion away from the first carrier portion;

[0015] Multiple second pins are disposed on the side of the first carrier portion away from the second carrier portion;

[0016] The first pins are used for electrical connection with a chip disposed on the second mounting area, and the second pins are used for electrical connection with chips disposed on the first mounting area and the third mounting area. The width of the second pins is greater than the width of the first pins.

[0017] In one embodiment, the chip package structure includes a region to be molded for encapsulation, and a package line is a boundary line used to delineate the region to be molded; both the first pin and the second pin extend from inside the package line to outside the package line; wherein...

[0018] A recess is provided on the second pin located outside the package line, and the recess divides the part of the second pin located outside the package line into two or more parts.

[0019] In one embodiment, the chip packaging structure further includes an outer frame and a connecting rib, the outer frame surrounding the first and second wafer stages, and the connecting rib connecting the first and second wafer stages and the outer frame.

[0020] In one embodiment, the connecting rib is provided with a break point groove.

[0021] In one embodiment, the first wafer carrier is provided with at least one first locking hole, and the orthographic projection of the first locking hole on the first wafer carrier does not overlap with the orthographic projection of the first mounting area and the second mounting area on the first wafer carrier; and / or

[0022] The second mounting stage is provided with a second locking hole, and the orthographic projection of the second locking hole on the second mounting stage does not overlap with the orthographic projection of the third mounting area on the second mounting stage.

[0023] In one embodiment, it further includes:

[0024] An interconnection structure is provided, through which the driver chip is electrically connected to the first power chip and the second power chip;

[0025] A molding compound is used to encapsulate the first wafer stage, the second wafer stage, the chip assembly, and the interconnect structure.

[0026] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0027] As described in the above embodiments, the chip packaging structure of this application includes a first wafer stage, a second wafer stage, and a chip assembly. The first wafer stage has a first mounting area and a second mounting area arranged at intervals along a first direction, and the second wafer stage has a third mounting area, which is arranged at intervals from the first mounting area along a second direction. The chip assembly includes a driver chip disposed in the second mounting area, a first power chip disposed in the first mounting area, and a second power chip disposed in the third mounting area. The first direction is the extension direction of the line connecting the centers of the first power chip and the driver chip, and the second direction is the extension direction of the line connecting the centers of the first and second power chips; the angle between the two directions is less than 90°. This application optimizes the relative positions and angles of the mounting areas on the wafer stage to achieve a more compact chip layout, effectively reducing the package size and improving heat dissipation performance and package reliability.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a chip packaging structure according to an embodiment of this application from one perspective.

[0031] Figure 2 A schematic diagram of the chip packaging structure and chip assembly according to an embodiment of this application from one perspective.

[0032] Figure 3 This is a non-transparent top view of the chip packaging structure in one embodiment of this application.

[0033] Figure 4 This is a perspective-based top view of the chip packaging structure in one embodiment of this application.

[0034] Explanation of reference numerals in the attached figures:

[0035] 1. First wafer stage; 11. First carrier portion; 12. Second carrier portion; 13. Groove; 2. Second wafer stage; 21. Third carrier portion; 22. Extension portion; 23. Protrusion; 31. First pin; 32. Second pin; 320. Recess; 40. Area to be encapsulated; 41. Encapsulation line; 5. Outer frame; 6. Connecting rib; 7. Locking hole; 71. First locking hole; 72. Second locking hole; 81. Driver chip; 82. First power chip; 83. Second power chip; 9. Interconnection structure.

[0036] X, first direction; Y, second direction; Z, third direction.

[0037] D1, the first center point; D2, the second center point; D3, the third center point. Detailed Implementation

[0038] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The manner described in the following exemplary embodiments does not represent all manner consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0039] As described in the background section, traditional three-phase intelligent power modules typically employ dual in-line packages (DIPs), whose internal circuit topology integrates up to six MOSFET chips and three driver chips, with each driver chip responsible for controlling the switching of two MOSFETs. This packaging scheme has several significant structural defects, limiting its performance in high-density, high-reliability applications.

[0040] First, the physical size of DIP packages is relatively large, and the module volume is huge, which makes it impossible to use standard tape and reel packaging. Therefore, it is difficult to use automated placement equipment for efficient production in the subsequent surface mount technology (SMT) process. It largely relies on manual or semi-automatic operation, resulting in low production efficiency, increased production costs, and difficulty in ensuring consistency.

[0041] Secondly, from a thermal management perspective, this packaging structure has high thermal resistance, which is not conducive to the timely dissipation of heat generated during the operation of the power chip. The MOSFET and driver chip generate concentrated heat during operation. If the heat dissipation path is inadequate, it can easily lead to an increase in the chip junction temperature, thereby affecting the electrical performance, output capability, and long-term operating life of the entire module.

[0042] Furthermore, to meet electrical insulation and wiring requirements, the chips within the module are spaced far apart, necessitating the use of both gold and copper wire bonding for signal interconnection. Gold wire bonding is expensive, while copper wire bonding presents challenges in matching oxidation and hardness, significantly increasing the complexity of the wire bonding process and material costs. This also makes it difficult to improve production yield and results in poor batch economics.

[0043] Finally, due to the large package size and the large amount of molding compound used, under temperature cycling, humidity sensitivity, or mechanical stress, the mismatch of the coefficients of thermal expansion (CTE) between different materials can easily lead to reliability problems such as interface delamination, internal cracks, or even bond point detachment, affecting the stability and service life of the module in harsh environments.

[0044] In summary, traditional DIP-packaged three-phase intelligent power modules have significant shortcomings in terms of size, heat dissipation, process complexity, and reliability, and a new packaging structure is urgently needed to overcome these defects.

[0045] Based on this, this application discloses a chip packaging structure, referring to... Figures 1 to 4 The chip packaging structure includes a first wafer stage 1 and a second wafer stage 2. The first wafer stage 1 has a first mounting area (not shown in the figure) and a second mounting area (not shown in the figure) spaced apart along a first direction X. The second wafer stage 2 has a third mounting area (not shown in the figure). The third mounting area and the first mounting area are spaced apart along a second direction Y.

[0046] The chip packaging structure also includes chip components located on the first die-mounting stage 1 and the second die-mounting stage 2. These include a driver chip 81 disposed in the second mounting area, a first power chip 82 disposed in the first mounting area, and a second power chip 83 disposed in the third mounting area. The driver chip 81 is electrically connected to the first power chip 82 and the second power chip 83 and is configured to control their switching operations.

[0047] Specifically, the materials of the first power chip 82 and the second power chip 83 include, but are not limited to, gallium nitride (GaN), and may also be semiconductor materials such as silicon (Si), silicon carbide (SiC) or gallium arsenide (GaAs).

[0048] Specifically, there is no limit to the number of chips that can be carried in each of the first, second, and third mounting areas. A single chip can be set, or multiple chips can be set in parallel, stacked, or integrated to meet different power levels or functional requirements.

[0049] Specifically, the shape and area of ​​the first, second, and third mounting areas can be adapted to the size of the chip they support. For example, the mounting areas can all be rectangular regions, and their areas can be equal or unequal.

[0050] Furthermore, the area of ​​the second mounting area is smaller than that of the first and third mounting areas to accommodate the size difference between the driver chip 81 and the power chip.

[0051] Specifically, the first direction X is the extension direction of the line connecting the center point of the first power chip 82 and the center point of the driver chip 81, and the second direction Y is the extension direction of the line connecting the center point of the first power chip 82 and the center point of the driver chip 81. The angle between the first direction X and the second direction Y is less than 90°.

[0052] For ease of understanding, please refer to Figure 2 and Figure 4 The center point of the driver chip 81 can be labeled as the first center point D1, the center point of the first power chip 82 as the second center point D2, and the center point of the second power chip 83 as the third center point D3. Accordingly, the first direction X is the extension direction of the line connecting the first center point D1 and the second center point D2, and the second direction Y is the extension direction of the line connecting the first center point D1 and the third center point D3.

[0053] It should be noted that the "center point" mentioned in this application is not limited to a strict geometric point, but refers to the central area where the core functions of the chip are located. Its specific location can be reasonably determined according to the chip shape and packaging requirements. For rectangular chips, the center point is usually the intersection of its diagonals or the area near that intersection; for circular or polygonal chips, the center point can be its geometric center or centroid; for irregularly shaped chips, the center point can be its core functional area or a reference point specified according to layout requirements.

[0054] Specifically, the angle between the first direction X and the second direction Y is an acute angle. For example, this angle can be any acute angle less than 90°, such as 45°, 60°, or 80°. Different angles provide flexibility to achieve specific layout compactness.

[0055] The chip packaging structure provided in this application achieves a compact spatial layout across the three mounting areas through a specific angular arrangement. Firstly, this specific arrangement significantly improves packaging space utilization, overcoming the technical problems of traditional multi-chip modules being too large, unable to be taped, and unautomated mounting. Secondly, this arrangement optimizes the physical separation of power and signal paths, improving thermal management and electrical performance, and reducing crosstalk and thermal resistance. Thirdly, this arrangement avoids mixed wire bonding processes, making it possible to use standardized bonding materials, thereby improving production yield and reducing process complexity and cost. Finally, the overall structure is more compact and robust, effectively reducing the risk of internal stress and delamination caused by mismatched coefficients of thermal expansion, significantly enhancing the module's reliability and lifespan.

[0056] In some implementations, the first installation area and the third installation area have the same area, and the center points of the first installation area and the third installation area are collinear.

[0057] This layout allows the two power mounting areas to be symmetrically and aligned on the frame, which helps to balance the overall structure of the package, making subsequent chip mounting, bonding and other processes more regular, and optimizing the overall heat distribution uniformity after packaging.

[0058] Meanwhile, this symmetrical and aligned layout makes it easier to achieve consistent or approximate interconnect path lengths from the driver chip 81 (located in the second mounting area) to the two power chips (located in the first and third mounting areas, respectively). This regular wiring reduces differences in signal transmission delay, helping to optimize the consistency of high-frequency switching characteristics. Simultaneously, the compact spatial arrangement effectively shortens the interconnect distance between chips, reducing bond wire parasitic inductance and loop resistance, thereby improving electrical performance. Furthermore, the clear wiring channels also reduce process complexity, which is beneficial for improving production yield.

[0059] In some implementations, the chip package structure is integrally formed by mechanical stamping or chemical etching processes. (See reference...) Figure 1 The integrated frame includes a first substrate stage 1 having a first support portion 11 and a second support portion 12, a first mounting area located on the first support portion 11, and a second mounting area located on the second support portion 12. The second substrate stage 2 has a third support portion 21 and an extension portion 22, with the third mounting area located on the third support portion 21.

[0060] Continue to refer to Figure 1 A groove 13 is formed at the junction of the first support portion 11 and the second support portion 12, and a protrusion 23 is formed at the junction of the third support portion 21 and the extension portion 22. The groove 13 is adapted to the shape of the protrusion 23 so that the first wafer stage 1 and the second wafer stage 2 fit together tightly. By matching the shapes of the groove 13 and the protrusion 23, the contours of the first wafer stage 1 and the second wafer stage 2 can be nested together, thereby reducing the overall layout area of ​​the chip packaging structure and achieving compact space utilization.

[0061] Furthermore, the groove 13 and the protrusion 23 can have various matching geometries. For example, in one embodiment, the groove 13 is an arcuate groove 13, and the protrusion 23 is a matching arcuate protrusion 23. The arcuate profile helps to smooth the stress distribution and reduce stress concentration at the structure during frame stamping or use.

[0062] In another embodiment, the groove 13 is a V-shaped groove 13, and the protrusion 23 is a matching V-shaped protrusion 23. The V-shaped structure has the advantages of simple processing and clear positioning intention.

[0063] In another embodiment, the groove 13 is a rectangular groove 13, and the protrusion 23 is a matching rectangular protrusion 23. The rectangular structure is beneficial for achieving extremely high material utilization within a limited planar space, making the layout more compact.

[0064] In some embodiments, the chip package structure employs a partitioned pin layout design. Multiple first pins 31 are located on the side of the second carrier portion 12 away from the first carrier portion 11, for electrical connection with the driver chip 81 on the second mounting area. Multiple second pins 32 are located on the side of the first carrier portion 11 away from the second carrier portion 12, for electrical connection with the power chips on the first mounting area and the third mounting area. The width of the second pins 32 is significantly larger than that of the first pins 31.

[0065] Specifically, in addition to its electrical connection function, the second pin 32 also serves as the main heat dissipation path for the power chip on the first carrier portion 11 and the third carrier portion 21. The large second pin 32 provides a larger surface area and thermal capacity, enabling rapid conduction of heat generated during chip operation to the outside of the package, significantly reducing the operating junction temperature of the power chip and thus improving the overall heat dissipation efficiency and power density of the package. This design achieves coordinated electrothermal management, simultaneously optimizing electrical performance and thermal reliability within a limited space.

[0066] Furthermore, the extension 22 is inclined relative to the third mounting part in the third direction Z, and the angle between the third direction Z and the second direction Y is smaller than the angle between the first direction X and the second direction Y.

[0067] Specifically, the third direction Z can be understood as the extension direction of the line connecting the center point of the first power chip 82 and the center point of the extension 22.

[0068] It should be noted that the center point of the first power chip 82 (i.e., the second center point D2) can be referred to the above content and will not be repeated here. The center point of the extension 22 can be defined as the geometric center, centroid, or any representative location point within the main structural range of the extension 22. This point is reasonably determined according to the specific shape and structural characteristics of the extension 22 and is used to accurately characterize its spatial orientation and directional relationship. At the same time, the center point of the extension 22 is not limited to a strict geometric point, but can be the central region within its contour range, such as the geometric center, centroid, or other representative regions used to characterize its main position.

[0069] In this application, the pin layout works in conjunction with the inclined extension 22 of the die stage, resulting in a more concentrated and compact pin arrangement, reducing the overall package footprint and providing a foundation for high-density integration. The differentiated design of wide and narrow pins also improves the mechanical strength of the frame and enhances the structural reliability of the package under temperature cycling conditions.

[0070] Reference Figure 1 The extension 22 has a strip-shaped structure and slopes upwards to the right. This sloped design provides ample layout space for the driver chip 81 in the second mounting area, and allows the multiple first pins 31 used to connect to the driver chip 81 to be arranged on the same side of the driver chip 81. This clustered pin arrangement effectively shortens the wiring distance between the pins and the pads of the driver chip 81, reduces parasitic inductance in the signal transmission path, optimizes the wiring channel in this area, and improves signal integrity and package reliability.

[0071] In some embodiments, the tilt angle of the extension 22 can be adjusted according to the number of pins and the arrangement density. For example, the tilt angle can be selected between 5° and 30° to achieve a balance between compact layout and electrical insulation.

[0072] In some implementations, the number of first pins 31 is greater than the number of second pins 32, but the total cross-sectional area of ​​the second pins 32 is greater than the total cross-sectional area of ​​the first pins 31, in order to meet the current distribution requirements of different functions.

[0073] In some implementations, the horizontal width ratio of the first pin 31 to the second pin 32 ranges from 2 to 12. It is readily understood that, in order to better dissipate heat through the pins, the width of the second pin 32 can be as wide as possible while still meeting the creepage distance requirements of adjacent pins.

[0074] In some implementations, refer to Figure 1 and Figure 2 The chip packaging structure includes a region 40 to be molded for molding, and a packaging line 41 is a boundary line used to delineate the region 40 to be molded. (Refer to...) Figure 1 and Figure 2 The package line 41 is schematically indicated by a dashed box. Both the first pin 31 and the second pin 32 extend from inside the package line 41 to outside it. It should be noted that pins located inside the package line 41 can be understood as inner pins, and pins located outside the package line 41 are outer pins. Therefore, based on their relationship with the package line 41, the first pin 31 can be divided into a first inner pin and a first outer pin, and the second pin 32 can be divided into a second inner pin and a second outer pin.

[0075] In some implementations, refer to Figure 1 and Figure 2 A recess 320 is provided on the second pin 32 (i.e., the second outer pin) located outside the package line 41. The recess 320 divides the portion of the second pin 32 located outside the package line 41 into two or more portions. It can be understood that the recess 320 divides the portion of the second pin 32 located outside the plastic package line into two or more mutually isolated pin segments.

[0076] Furthermore, the recess 320 can have various embodiments. In one embodiment, the recess 320 is a V-shaped groove 13 with its opening facing away from the molding compound. In another embodiment, the recess 320 is a U-shaped or rectangular groove, integrally formed on the second pin 32 by stamping or etching. In yet another embodiment, the recess 320 is a through hole penetrating the thickness of the pin or a non-penetrating blind groove.

[0077] The recessed portion 320 structure divides the wide second lead 32 at the lead-cutting point, thereby dispersing the stress concentration generated during lead-cutting and preventing lead deformation or breakage. It improves the filling condition of the molding compound at the lead, preventing micro-cracks in the molding compound caused by stress concentration. Simultaneously, it ensures the heat dissipation performance of the wide lead while improving the reliability of the lead-cutting process and the molding quality.

[0078] In some implementations, refer to Figure 1 and Figure 2 The chip packaging structure also includes an outer frame 5 and a connecting rib 6. The outer frame 5 surrounds the first die carrier 1 and the second die carrier 2. The connecting rib 6 connects the first die carrier 1, the second die carrier 2 and the outer frame 5, forming an integrally formed lead frame structure during the packaging manufacturing process.

[0079] In some implementations, the number of connecting ribs on the substrate stage can be adjusted according to actual structural strength requirements, allowing for the installation of one or more connecting ribs to accommodate substrate stages of different sizes and the connection requirements of the external frame. This design, through flexible configuration of the number of connecting ribs, balances material cost and process feasibility while ensuring the overall mechanical stability of the frame.

[0080] Furthermore, a breakpoint groove (not shown in the figure) is provided on the connecting rib portion 6. The breakpoint groove can have various implementations:

[0081] In one embodiment, the break groove is a V-shaped groove, formed on the surface of the connecting rib 6 near the outer frame 5.

[0082] In another embodiment, the break point groove is a U-shaped groove, which is formed on the side surface of the connecting rib portion 6 near the slide stage.

[0083] In another embodiment, the breakpoint groove is a through groove that penetrates the thickness of the connecting rib portion 6.

[0084] In another embodiment, the breakpoint groove is a plurality of rectangular grooves arranged in parallel and spaced apart along the length direction of the connecting rib portion 6.

[0085] In this embodiment, a pre-designed breakpoint groove structure guides the fracture path during rebar cutting, ensuring accurate fracture location and regular shape. The breakpoint groove also effectively disperses stress generated during rebar cutting, preventing stress concentration that could lead to frame deformation or damage to the encapsulation. Finally, the breakpoint groove controls the fracture location, avoiding the formation of metal burrs and improving encapsulation reliability.

[0086] In some embodiments, a locking hole 7 is provided on the first wafer stage 1, the second wafer stage 2, the first pin 31, and the second pin 32.

[0087] Specifically, during the subsequent molding process, the keyhole 7 can be injection molded to form a molding flow channel, which enhances the bonding force between the chip packaging structure and the molding body of the subsequent packaging process, avoids product delamination, improves product reliability, and reduces packaging costs.

[0088] Furthermore, this application does not limit the shape and location of the keyhole 7; its shape can be adjusted according to the location. For example, the keyhole 7 can be a circular, square, or cross-shaped through hole, or any one of an elliptical or polygonal hole. For example, multiple keyholes 7 can be arranged in an array, uniformly distributed around the mounting platen area. For example, the inner wall of the keyhole 7 can be provided with a roughened texture or microstructure to further enhance the adhesion to the molding compound.

[0089] In one embodiment, refer to Figure 1 The first mounting stage 1 is provided with at least one first locking hole 71. The orthographic projection of the first locking hole 71 on the first mounting stage 1 does not overlap with the orthographic projection of the first mounting area and the second mounting area on the first mounting stage 1.

[0090] In another embodiment, continue to refer to Figure 1 The second mounting stage 2 is provided with a second locking hole 72, and the orthographic projection of the second locking hole 72 on the second mounting stage 2 does not overlap with the orthographic projection of the third mounting area on the second mounting stage 2.

[0091] In one embodiment, refer to Figure 1 The keyhole 7 is located on the first inner pin. This enhances the molding bond, prevents delamination, improves filling performance, and increases package reliability.

[0092] In some embodiments, the chip package structure further includes an interconnect structure 9 and a molding compound. The driver chip 81 is electrically connected to the first power chip 82 and the second power chip 83 via the interconnect structure 9. The molding compound is used to encapsulate the first die-mount stage 1, the second die-mount stage 2, the chip assembly, and the interconnect structure 9.

[0093] Furthermore, the interconnect structure 9 is not limited to wire bonding. It can also use copper clips, aluminum strips, three-dimensional interconnects or other conductive connection structures to achieve electrical and thermal connections between chips and between chips and pins, thereby adapting to the requirements of different application scenarios such as high frequency and high current for parasitic parameters and heat dissipation performance.

[0094] In this packaging structure, the die-mounting area with a specific angle layout achieves a compact arrangement of the driver chip 81 and the power chip, significantly reducing the package size. Simultaneously, the wide and narrow pin partitioning design provides electrical connection while enabling high-current transmission and efficient heat dissipation. Secondly, the keyhole structure on the die-mounting area enhances the bonding strength of the molding compound and prevents delamination failure. Finally, the groove 13 design of the connecting rib 6 optimizes the reliability of the rib cutting process; the mutually adaptable concave-convex contour structure further improves space utilization.

[0095] The various structures work together to achieve high-density integration, excellent heat dissipation performance, high reliability, and good process adaptability within a limited space.

[0096] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in this application should be understood in their ordinary sense by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application specification and claims do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similarly, the terms "a" or "one," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one, which will be separately stated if only "a" is referred to. "A plurality" or "several" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and / or "upper," etc., are for ease of description only and are not limited to a location or spatial orientation. The terms "comprising" or "including," etc., mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The terms “connection” or “link” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0097] The specific embodiments described herein are merely illustrative examples of the spirit of this application. Those skilled in the art to which this application pertains may make various modifications, additions, or use similar methods to replace the described specific embodiments, without departing from the spirit of this application or exceeding the scope defined by the appended claims.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A chip package structure, characterized by, include: The first mounting stage is provided with a first mounting area and a second mounting area arranged at intervals along a first direction; The second mounting stage is provided with a third mounting area; the third mounting area is arranged at a distance from the first mounting area along a second direction. A chip assembly, comprising a driver chip disposed in the second mounting area, a first power chip disposed in the first mounting area, and a second power chip disposed in the third mounting area; The first direction is the extension direction of the line connecting the center point of the first power chip and the center point of the driver chip, and the second direction is the extension direction of the line connecting the center point of the first power chip and the center point of the second power chip. The angle between the first direction and the second direction is less than 90°.

2. The chip package structure of claim 1, wherein, The first stage includes a first support portion and a second support portion, the first mounting area is disposed on the first support portion, and the second mounting area is disposed on the second support portion; The second stage includes a third support portion and an extension portion, wherein the third mounting area is disposed on the third support portion; wherein, A groove is formed at the junction of the first support portion and the second support portion, and a protrusion is formed at the junction of the third support portion and the extension portion. The groove is adapted to the shape of the protrusion so that the first substrate stage and the second substrate stage fit together tightly.

3. The chip package structure of claim 2, wherein, The groove is an arc-shaped groove, and the protrusion is a matching arc-shaped protrusion.

4. The chip packaging structure according to claim 2, characterized in that, The extension is inclined in a third direction relative to the third bearing portion, and the angle between the third direction and the second direction is smaller than the angle between the first direction and the second direction.

5. The chip packaging structure according to claim 2, characterized in that, The chip packaging structure also includes: Multiple first pins are disposed on the side of the second carrier portion away from the first carrier portion; Multiple second pins are disposed on the side of the first carrier portion away from the second carrier portion; The first pins are used for electrical connection with a chip disposed on the second mounting area, and the second pins are used for electrical connection with chips disposed on the first mounting area and the third mounting area. The width of the second pins is greater than the width of the first pins.

6. The chip packaging structure according to claim 5, characterized in that, The chip packaging structure includes a region to be molded for encapsulation, and a packaging line is a boundary line used to delineate the region to be molded; both the first pin and the second pin extend from inside the packaging line to outside the packaging line; wherein... A recess is provided on the second pin located outside the package line, and the recess divides the part of the second pin located outside the package line into two or more parts.

7. The chip packaging structure according to any one of claims 1-6, characterized in that, The chip packaging structure also includes an outer frame and a connecting rib. The outer frame surrounds the first and second wafer carriers, and the connecting rib connects the first and second wafer carriers to the outer frame.

8. The chip packaging structure according to claim 7, characterized in that, The connecting rib section is provided with a break point groove.

9. The chip packaging structure according to any one of claims 1-6, characterized in that, The first wafer carrier stage is provided with at least one first locking hole, and the orthographic projection of the first locking hole on the first wafer carrier stage does not overlap with the orthographic projection of the first mounting area and the second mounting area on the first wafer carrier stage; and / or The second mounting stage is provided with a second locking hole, and the orthographic projection of the second locking hole on the second mounting stage does not overlap with the orthographic projection of the third mounting area on the second mounting stage.

10. The chip packaging structure according to any one of claims 1-6, characterized in that, Also includes: An interconnection structure is provided, through which the driver chip is electrically connected to the first power chip and the second power chip; A molding compound is used to encapsulate the first wafer stage, the second wafer stage, the chip assembly, and the interconnect structure.

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