LED linear control chip and LED linear drive circuit with thyristor detection

Abstract

This utility model relates to the field of LED linear driving technology, and discloses an LED linear control chip and an LED linear driving circuit with thyristor detection. The LED linear control chip includes a transistor JFET1, a bandgap reference unit, an analog comparator CMP, a pulse trigger SPT, an AND gate, a trigger branch, an inverter INV, a D flip-flop DT11, a first current control unit, a second current control unit, and an adder. In practical use, the control chip of this utility model, by setting a trigger branch, when the driving circuit with the control chip is not connected to the thyristor, after experiencing the power frequency cycle of the D flip-flop in the trigger branch, the current BLEED in the existing circuit is canceled, reducing the power consumption of the system. Moreover, when the driving circuit with the control chip is connected to the thyristor, the working state is the same as that of the existing circuit.

Description

Technical Field

[0001] This utility model relates to the field of LED linear drive technology, specifically to an LED linear control chip with thyristor detection and an LED linear drive circuit. Background Technology

[0002] In the field of LED linear driving, to ensure compatibility of traditional offline input LED linear driving circuits with thyristors, a discharge current needs to be added when the input voltage is insufficient to turn on the LED, thus allowing the thyristor to operate stably. The circuit diagram of an existing LED linear driving circuit with a thyristor is shown below. Figure 1 Its working principle is as follows:

[0003] When the input voltage VIN is rectified into a pulsating bus voltage VBUS after passing through the rectifier bridge, and the bus voltage VBUS is less than the turn-on voltage VLED of the load LED, the load LED does not work, and the BLEED control module works. The current IBLEED flowing through the MOSFET Q2 in the BLEED control module through the bus voltage VBUS via resistor RBLEED is controlled at VREF / RCSB. In addition, theoretically, the current flowing through RBLEED also includes the operating current of the control chip, but the operating current of the control chip is generally negligible compared to VREF / RCSB, so it is usually calculated according to VREF / RCSB. At this time, the current IBLEED is the entire input current. Without an input current, the thyristor conduction would be unstable.

[0004] When the bus voltage VBUS is greater than the turn-on voltage VLED, the current control module starts working. The bus voltage VBUS flows through the load LED and the MOSFET Q1 of the current control module. The current flowing through the load LED is controlled within VREF / RCS. The portion of the bus voltage VBUS greater than the turn-on voltage VLED is applied to the MOSFET Q1. Since the current flowing through the load LED is also the input current, the SCR can operate stably when there is no current BLEED. From the above, we can see that the current feedback of resistor BLEED is the sum of the voltages across resistors RCSB and RCS. When there is a voltage VREF across resistor RCS, the current BLEED is automatically canceled.

[0005] for Figure 1 The waveforms of the relevant current and voltage of the thyristor in the circuit shown are as follows: Figure 2 As shown, the waveforms of the relevant current and voltage when the thyristor is removed are as follows: Figure 3 As shown.

[0006] Combination Figure 2 and Figure 3Current bleeding occurs as a loss and does not pass through the load LED. The loss from current bleeding affects the overall efficiency and system heat generation, thus affecting the system stability. Therefore, current bleeding needs to be eliminated in applications without a thyristor. Utility Model Content

[0007] In view of the shortcomings of the background technology, the present invention provides an LED linear control chip with thyristor detection and an LED linear drive circuit. The technical problem to be solved is that in the existing LED constant current drive circuit, when there is no thyristor connected, there is still current in the circuit that increases the power consumption when the input voltage is less than the conduction voltage of the load LED.

[0008] To solve the above technical problems, in the first aspect, this utility model provides the following technical solution: an LED linear control chip with thyristor detection, including a transistor JFET1, a bandgap reference unit, an analog comparator CMP, a pulse trigger SPT, an AND gate, a trigger branch, an inverter INV, a D trigger DT11, a first current control unit, a second current control unit, and an adder.

[0009] The input terminal of transistor JFET1 is used to input an external voltage, and the output terminal of transistor JFET1 is electrically connected to the bandgap reference unit. The bandgap reference voltage is used to provide a reference voltage and a working voltage.

[0010] The positive input terminal of the analog comparator CMP is used to input the reference voltage, and the negative input terminal of the analog comparator CMP is used to input the feedback voltage of the external voltage. The positive output terminal of the analog comparator CMP is electrically connected to the input terminal of the pulse flip-flop SPT. The negative output terminal of the analog comparator CMP is electrically connected to one input terminal of the AND gate and the clock terminal of the D flip-flop DR11. The output terminal of the pulse flip-flop SPT is electrically connected to the other input terminal of the AND gate and the input terminal of the inverter INV. The output terminal of the inverter INV is electrically connected to the D input terminal of the D flip-flop DT11.

[0011] The trigger branch includes multiple D flip-flops connected in series. The series connection is such that the QP output of the front-end D flip-flop is electrically connected to the D input of the back-end D flip-flop. The output of the AND gate is electrically connected to the clock input of all the D flip-flops in the trigger branch. The QP output of the D flip-flop DT11 is electrically connected to the reset input of all the D flip-flops in the trigger branch.

[0012] The first current control unit includes an operational amplifier EA1 and a first switching transistor Q1. The positive input terminal of the operational amplifier EA1 is used to input a reference voltage. The negative input terminal of the operational amplifier EA1 is electrically connected to one input terminal of the adder and the output terminal of the first switching transistor Q1, respectively. The output terminal of the operational amplifier EA1 is electrically connected to the control terminal of the first switching transistor Q1.

[0013] The second current control unit includes an operational amplifier EA2 and a second switch Q2. The positive input terminal of the operational amplifier EA2 is electrically connected to one end of a resistor R100 and the input terminal of a control switch SW, respectively. The other end of the resistor R100 is used to input a reference voltage. The control terminal of the control switch SW is electrically connected to the QP output terminal of the D flip-flop at the end of the trigger branch. The output terminal of the control switch SW is grounded. The negative input terminal of the operational amplifier EA2 is electrically connected to the input terminal of the adder. The output terminal of the operational amplifier EA2 is electrically connected to the control terminal of the second switch Q2. The output terminal of the second switch Q2 is electrically connected to the other input terminal of the adder.

[0014] In one embodiment of the first aspect, the trigger branch comprises ten D flip-flops connected in series.

[0015] In one embodiment of the first aspect, the first switch Q1 is an NMOS transistor, the drain of the NMOS transistor is the input terminal of the first switch Q1, the gate of the NMOS transistor is the control terminal of the first switch Q1, and the source of the NMOS transistor is the output terminal of the first switch Q1.

[0016] In one embodiment of the first aspect, the second switch Q2 is an NMOS transistor, the drain of the NMOS transistor is the input terminal of the second switch Q2, the gate of the NMOS transistor is the control terminal of the second switch Q2, and the source of the NMOS transistor is the output terminal of the second switch Q2.

[0017] In one embodiment of the first aspect, the transistor JFET is of type NMOS.

[0018] In one embodiment of the first aspect, the present invention further includes a chip body, wherein the transistor JFET1, bandgap reference unit, analog comparator CMP, pulse trigger SPT, AND gate AND, trigger branch, inverter INV, D trigger DT11, first current control unit, second current control unit, adder, resistor R100 and control switch SW are all disposed on the chip body.

[0019] In one embodiment of the first aspect, the chip body is further provided with a VCC pin, a DRNB pin, a DRN pin, a CS pin, a CSB pin, a GND pin, and a ZVT pin. The VCC pin is electrically connected to the output terminal of the transistor JFET. The DRNB pin is electrically connected to the input terminal of the transistor JFET and the input terminal of the second switch Q2. The DRN pin is electrically connected to the input terminal of the first switch Q1. The CS pin is electrically connected to the output terminal of the first switch Q1. The CSB pin is electrically connected to the output terminal of the second switch Q2. The GND pin is the chip's ground pin. The ZVT pin is electrically connected to the negative input terminal of the analog comparator CMP.

[0020] In one embodiment of the first aspect, the DRNB pin and the DRN pin are arranged sequentially on the top of the chip body along the left-right direction, the ZVT pin is arranged on the left side of the chip body, and the VCC pin, GND pin, CS pin and CSB pin are arranged sequentially on the bottom of the chip body along the left-right direction.

[0021] Secondly, this utility model also provides an LED linear driving circuit, including the aforementioned LED linear control chip with thyristor detection, and further including resistors R1-R5, capacitors C1 and C2, diode D1, and a rectifier bridge. The positive output terminal of the rectifier bridge is electrically connected to one end of resistor R1, one end of resistor R3, and the anode of diode D1, respectively. The other end of resistor R1 is electrically connected to one end of resistor R2 and the negative input terminal of analog comparator CMP, respectively. The other end of resistor R2 is grounded, and the other end of resistor R3 is electrically connected to the input terminal of transistor JFET. The output terminal of transistor JFET is grounded through capacitor C1. The output terminal of first switch Q1 is grounded through resistor R4, and the output terminal of second switch Q2 is grounded through resistor R5. The cathode of diode D1 is electrically connected to one end of capacitor C2, and the other end of capacitor C2 is used to be electrically connected to the input terminal of first switch Q1. The two ends of capacitor C2 are also used to be connected in parallel with the load LED.

[0022] In one embodiment of the second aspect, the input terminal of the rectifier bridge is also electrically connected to a thyristor.

[0023] The advantages of this invention compared to the prior art are as follows: By setting a trigger branch, when the drive circuit with the control chip is not connected to the thyristor, the current BLEED in the existing circuit is canceled after experiencing the power frequency cycle of the D flip-flop in the trigger branch, thus reducing the power consumption of the system. Moreover, when the drive circuit with the control chip is connected to the thyristor, the working state is the same as that of the existing circuit. Attached Figure Description

[0024] Figure 1The circuit diagram is for an existing LED linear drive circuit.

[0025] Figure 2 for Figure 1 Simulation waveforms of relevant voltages and currents during circuit simulation;

[0026] Figure 3 for Figure 1 Simulation waveforms of relevant voltages and currents when the circuit is simulated without the thyristor;

[0027] Figure 4 This is a circuit diagram of the control chip in Example 1;

[0028] Figure 5 The circuit diagram is shown for the LED linear driving circuit in Example 2.

[0029] Figure 6 for Figure 5 Simulation waveforms of relevant voltages and currents of the circuit without thyristor simulation;

[0030] Figure 7 for Figure 5 Simulation waveforms of relevant voltages and currents during circuit simulation. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0032] Example 1

[0033] like Figure 4 As shown, the LED linear control chip with thyristor detection provided in this embodiment includes a transistor JFET1, a bandgap reference unit 5, an analog comparator CMP, a pulse trigger SPT, an AND gate, a trigger branch 6, an inverter INV, a D trigger DT11, a first current control unit 3, a second current control unit 4, and an adder SUM.

[0034] The input terminal of transistor JFET1 is used to input an external voltage, and the output terminal of transistor JFET1 is electrically connected to the bandgap reference unit 5. The bandgap reference voltage 5 is used to provide the reference voltage VREF and the operating voltage VD; wherein the provided reference voltage VREF may include multiple voltages with different values.

[0035] The positive input of the analog comparator CMP is used to input the reference voltage VREF2, which can be generated by the bandgap reference unit 5. The negative input of the analog comparator CMP is used to input the feedback voltage of the external voltage. The positive output of the analog comparator CMP is electrically connected to the input of the pulse flip-flop SPT. The negative output of the analog comparator CMP is electrically connected to one input of the AND gate and the clock terminal of the D flip-flop DR11. The output of the pulse flip-flop SPT is electrically connected to the other input of the AND gate and the input of the inverter INV. The output of the inverter INV is electrically connected to the D input of the D flip-flop DT11.

[0036] Trigger branch 6 includes multiple D flip-flops connected in series. The QP output of the front-end D flip-flop is electrically connected to the D input of the back-end D flip-flop. The output of the AND gate is electrically connected to the clock input of all the D flip-flops in the trigger branch. The QP output of the D flip-flop DT11 is electrically connected to the reset input of all the D flip-flops in the trigger branch.

[0037] The first current control unit 3 includes an operational amplifier EA1 and a first switching transistor Q1. The positive input terminal of the operational amplifier EA1 is used to input a reference voltage. The negative input terminal of the operational amplifier EA1 is electrically connected to one input terminal of the adder and the output terminal of the first switching transistor Q1, respectively. The output terminal of the operational amplifier EA1 is electrically connected to the control terminal of the first switching transistor Q1.

[0038] The second current control unit 4 includes an operational amplifier EA2 and a second switch Q2. The positive input terminal of the operational amplifier EA2 is electrically connected to one end of the resistor R100 and the input terminal of the control switch SW. The other end of the resistor R100 is used to input a reference voltage. The control terminal of the control switch SW is electrically connected to the QP output terminal of the D flip-flop at the end of the trigger branch 6. The output terminal of the control switch SW is grounded. The negative input terminal of the operational amplifier EA2 is electrically connected to the input terminal of the adder. The output terminal of the operational amplifier EA2 is electrically connected to the control terminal of the second switch Q2. The output terminal of the second switch Q2 is electrically connected to the other input terminal of the adder.

[0039] In practical use, the control chip of this utility model, by setting up trigger branch 6, when the drive circuit with the control chip is not connected to the thyristor, after experiencing the power frequency cycle of the D flip-flop in the trigger branch 6, the current BLEED in the existing circuit is canceled, reducing the power consumption of the system. Moreover, when the drive circuit with the control chip is connected to the thyristor, the working state is the same as the existing circuit.

[0040] Specifically, in this embodiment, as Figure 4As shown, trigger branch 6 includes ten D flip-flops connected in series, namely D flip-flops DT1-D flip-flops DT10; in a certain embodiment, the exact number of D flip-flops in trigger branch 6 can be set according to actual needs.

[0041] Specifically, in this embodiment, the first switch Q1 is an NMOS transistor, with its drain as the input terminal, its gate as the control terminal, and its source as the output terminal. Similarly, in this embodiment, the second switch Q2 is an NMOS transistor, with its drain as the input terminal, its gate as the control terminal, and its source as the output terminal. Additionally, the JFET transistor is of the NMOS type.

[0042] Specifically, in this embodiment, the present invention also includes a chip body 100, and transistor JFET1, bandgap reference unit 5, analog comparator CMP, pulse trigger SPT, AND gate, trigger branch 6, inverter INV, D trigger DT11, first current control unit 3, second current control unit 4, adder SUM, resistor R100 and control switch SW are all disposed on the chip body 100.

[0043] In addition, the chip body 100 is also provided with VCC pin, DRNB pin, DRN pin, CS pin, CSB pin, GND pin and ZVT pin. VCC pin is electrically connected to the output terminal of transistor JFET, DRNB pin is electrically connected to the input terminal of transistor JFET and the input terminal of second switch Q2, DRN pin is electrically connected to the input terminal of first switch Q1, CS pin is electrically connected to the output terminal of first switch Q1, CSB pin is electrically connected to the output terminal of second switch Q2, GND pin is the ground pin of the chip, and ZVT pin is electrically connected to the negative input terminal of analog comparator CMP.

[0044] In this embodiment, the distribution positions of the VCC pin, DRNB pin, DRN pin, CS pin, CSB pin, GND pin, and ZVT pin on the chip body are as follows: Figure 5 , Figure 4 The pinout is only for illustrative purposes and is intended to facilitate connection with the chip circuitry; among them, in Figure 5 In the chip body 100, the DRNB pin and DRN pin are arranged sequentially on the top of the chip body 100 along the left-right direction, the ZVT pin is arranged on the left side of the chip body 100, and the VCC pin, GND pin, CS pin and CSB pin are arranged sequentially on the bottom of the chip body 100 along the left-right direction.

[0045] Furthermore, the operation of the control chip in this embodiment is explained in Embodiment 2, and will not be described again here.

[0046] Example 2

[0047] like Figure 5 As shown, this embodiment provides an LED linear driving circuit, including the LED linear control chip with thyristor detection as in Embodiment 1, and also includes resistors R1-R5, capacitors C1 and C2, diode D1, and rectifier bridge 1. The positive output terminal of rectifier bridge 1 is electrically connected to one end of resistor R1, one end of resistor R3, and the anode of diode D1, respectively. The other end of resistor R1 is electrically connected to one end of resistor R2 and the negative input terminal of analog comparator CMP, respectively. The other end of resistor R2 is grounded, and the other end of resistor R3 is electrically connected to the input terminal of transistor JFET. The output terminal of transistor JFET is grounded through capacitor C1. The output terminal of first switch Q1 is grounded through resistor R4, and the output terminal of second switch Q2 is grounded through resistor R5. The cathode of diode D1 is electrically connected to one end of capacitor C2, and the other end of capacitor C2 is used to be electrically connected to the input terminal of first switch Q1. The two ends of capacitor C2 are also used to be connected in parallel with the load LED.

[0048] In addition, in actual implementation, the input terminal of rectifier bridge 1 is also electrically connected to thyristor 2.

[0049] Figure 5 The circuit shown works as follows:

[0050] After the current is connected, that is, when the bus voltage, i.e. the voltage output from the positive output terminal of rectifier bridge 1, is greater than the operating voltage of the load LED, the equivalent load of the first switching transistor Q1 changes to ensure that the current flowing through the load LED is ILED=VREF / RCS.

[0051] At the same time, after power-on, the QP output of D flip-flops DT1~DT11 is low by default. At this time, the working state of the first current control unit 3 and the second current control unit 4 is similar to that of the existing circuit, which will not be described in detail here.

[0052] The voltage at pin ZVT is denoted as VZVT. VZVT is the result of voltage division of the bus voltage, so when the bus voltage reaches its lowest point, VZVT will inevitably decrease. When VZVT is less than the reference voltage VREF2, the positive output of the analog comparator CMP, denoted as OP, is high, and the negative output, denoted as ON, is low. The transition of OP from low to high triggers the output of the pulse flip-flop SPT to output a pulse voltage. The designed pulse duration can be 700µs. At this time, the output of the AND gate is also low, and the output of the inverter INV is also low. The circuit operation process is explained below in two states:

[0053] In the first state: when there is no thyristor 2 in the drive circuit, the voltage VZVT will quickly exceed the reference voltage VREF2. By setting the resistance values ​​of resistors R1 and R2, it can be made so that when the voltage VZVT is higher than VREF2, the pulse output of the pulse trigger SPT has not yet ended. That is, when OP is low and ON outputs high, the output of the pulse trigger SPT is still high. Obviously, when the clock terminal of the D flip-flop DT11 jumps from low to high, the output of the pulse trigger SPT is still high and the output of the inverter INV is still low. Therefore, the output of the QP terminal of the D flip-flop DT11 is still low.

[0054] At the same time, when ON is high, the output of the pulse flip-flop SPT is high, and the output of the AND gate jumps from low to high. Because the D input of the D flip-flop DT1 is connected to the working voltage VD, which is high, the output of the QP output of the D flip-flop DT1 is high.

[0055] Because the level of D in D flip-flops DT2 to DT10 does not change in time when the clock signal changes, the output of the QP terminal of D flip-flops DT2 to DT10 remains unchanged and remains at a low level.

[0056] Similarly, the same action repeats when the second bus voltage trough arrives. The only difference is that because the D input of D flip-flop DT2 is connected to the QP output of D flip-flop DT1, and the voltage output of the QP terminal of D flip-flop DT1 became high after the previous voltage VZVT was higher than the reference voltage VREF2, the output of the QP terminal of D flip-flop DT2 becomes high again when the voltage VZVT is higher than the reference voltage VREF2. This process continues until, after 10 voltages VZVT are higher than the reference voltage VREF2, the output of the QP terminal of D flip-flop DT10 becomes high.

[0057] When the QP output of the D flip-flop DT10 goes high, the control switch SW is turned on, and the positive input of the operational amplifier EA2 is pulled low to near ground. Therefore, the current through the current channel resistor R3 is equal to... Figure 1 The current IBLEED in the circuit is approximately 0 / RCS1=0. At this point, there is no current IBLEED in the input current, which saves circuit power consumption.

[0058] The second state: In this state, thyristor 2 is connected to the circuit. When the input of rectifier bridge 1 is connected to thyristor 2, the waveform of the bus voltage will be partially lost due to the chopping effect of thyristor 2. By reasonably setting the resistance values ​​of resistors R1 and R2, when the voltage VZVT is higher than the reference voltage VREF2, i.e., when ON is high and OP is low, the pulse of the pulse trigger STP has ended, and its output has returned to low level. Therefore, the output level of the AND gate does not change, and thus there is no Clk signal at the clock terminals of D flip-flops DT1-DT10.

[0059] Simultaneously, when ON jumps from low to high level, since the pulse of the pulse flip-flop STP ends, the inverter INV outputs a high level, the QP output of the D flip-flop DT11 outputs a high level, the reset terminals of D flip-flops DT1-DT10 are forcibly pulled high, and the QP output terminals of D flip-flops DT1-DT10 are forcibly output a low level.

[0060] Since the QP output of the D flip-flop DT10 is forced to output a low level, the control switch SW will not be closed, and the positive input of the operational amplifier EA2 remains unchanged at the reference voltage VREF2. It should also be noted that the input impedance of the operational amplifier EA2 is usually very high, reaching tens of megohms. The effect of adding a 10kΩ resistor at its input on the input voltage is negligible.

[0061] In the dimming mode with a thyristor, if a false trigger occurs when the voltage VZVT is higher than the reference voltage VREF2, the pulse output of the pulse trigger SPT will end, and the thyristor-free mode will not be triggered immediately. This is because the output of the QP terminal of the D flip-flop DT must jump to a high level starting from D flip-flop DT1. Furthermore, in 10 consecutive voltage VZVTs higher than the reference voltage VREF2, if the output of the pulse trigger SPT returns to a low level even once, the QP output of D flip-flop DT11 will reset the QP outputs of D flip-flops DT1-DT10. This ensures that after the system is equipped with a thyristor, it will not occasionally misjudge the absence of a thyristor, thus erroneously causing the current flowing through resistor R1 to be zero, increasing the system's anti-interference capability.

[0062] In this embodiment, Figure 5 The simulated waveforms of the relevant voltage and current when the thyristor 2 is removed and present are as follows: Figure 6 and Figure 7 As shown, when the thyristor 2 is removed, the current flowing through resistor R3 becomes zero in some intervals, reducing power consumption. When the thyristor 2 is connected, the circuit of this application operates in a similar state to existing circuits.

[0063] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. LED linear control chip with silicon controlled detector, characterized in that, It includes transistor JFET1, bandgap reference unit, analog comparator CMP, pulse flip-flop SPT, AND gate, trigger branch, inverter INV, D flip-flop DT11, first current control unit, second current control unit, and adder; The input terminal of transistor JFET1 is used to input external voltage, and the output terminal of transistor JFET1 is electrically connected to the bandgap reference unit, which is used to provide reference voltage and operating voltage. The positive input terminal of the analog comparator CMP is used to input the reference voltage, and the negative input terminal of the analog comparator CMP is used to input the feedback voltage of the external voltage. The positive output terminal of the analog comparator CMP is electrically connected to the input terminal of the pulse flip-flop SPT. The negative output terminal of the analog comparator CMP is electrically connected to one input terminal of the AND gate and the clock terminal of the D flip-flop DR11. The output terminal of the pulse flip-flop SPT is electrically connected to the other input terminal of the AND gate and the input terminal of the inverter INV. The output terminal of the inverter INV is electrically connected to the D input terminal of the D flip-flop DT11. The trigger branch includes multiple D flip-flops connected in series. The series connection is such that the QP output of the front-end D flip-flop is electrically connected to the D input of the back-end D flip-flop. The output of the AND gate is electrically connected to the clock input of all the D flip-flops in the trigger branch. The QP output of the D flip-flop DT11 is electrically connected to the reset input of all the D flip-flops in the trigger branch. The first current control unit includes an operational amplifier EA1 and a first switching transistor Q1. The positive input terminal of the operational amplifier EA1 is used to input a reference voltage. The negative input terminal of the operational amplifier EA1 is electrically connected to one input terminal of the adder and the output terminal of the first switching transistor Q1, respectively. The output terminal of the operational amplifier EA1 is electrically connected to the control terminal of the first switching transistor Q1. The second current control unit includes an operational amplifier EA2 and a second switch Q2. The positive input terminal of the operational amplifier EA2 is electrically connected to one end of a resistor R100 and the input terminal of a control switch SW, respectively. The other end of the resistor R100 is used to input a reference voltage. The control terminal of the control switch SW is electrically connected to the QP output terminal of the D flip-flop at the end of the trigger branch. The output terminal of the control switch SW is grounded. The negative input terminal of the operational amplifier EA2 is electrically connected to the input terminal of the adder. The output terminal of the operational amplifier EA2 is electrically connected to the control terminal of the second switch Q2. The output terminal of the second switch Q2 is electrically connected to the other input terminal of the adder.

2. The LED linear control chip with silicon controlled detector according to claim 1, characterized in that, The triggering branch consists of ten D flip-flops connected in series.

3. The LED linear control chip with silicon controlled detector according to claim 1, characterized in that, The first switch Q1 is an NMOS transistor. The drain of the NMOS transistor is the input terminal of the first switch Q1, the gate of the NMOS transistor is the control terminal of the first switch Q1, and the source of the NMOS transistor is the output terminal of the first switch Q1.

4. The LED linear control chip with thyristor detection according to claim 1, characterized in that, The second switch Q2 is an NMOS transistor. The drain of the NMOS transistor is the input terminal of the second switch Q2, the gate of the NMOS transistor is the control terminal of the second switch Q2, and the source of the NMOS transistor is the output terminal of the second switch Q2.

5. The LED linear control chip with thyristor detection according to claim 1, characterized in that, The transistor JFET is of type NMOS.

6. The LED linear control chip with thyristor detection according to claim 1, characterized in that, It also includes the chip body, on which the transistor JFET1, bandgap reference unit, analog comparator CMP, pulse trigger SPT, AND gate, trigger branch, inverter INV, D trigger DT11, first current control unit, second current control unit, adder, resistor R100 and control switch SW are all mounted.

7. The LED linear control chip with thyristor detection according to claim 6, characterized in that, The chip body also has a VCC pin, a DRNB pin, a DRN pin, a CS pin, a CSB pin, a GND pin, and a ZVT pin. The VCC pin is electrically connected to the output terminal of the JFET transistor. The DRNB pin is electrically connected to the input terminal of the JFET transistor and the input terminal of the second switch Q2. The DRN pin is electrically connected to the input terminal of the first switch Q1. The CS pin is electrically connected to the output terminal of the first switch Q1. The CSB pin is electrically connected to the output terminal of the second switch Q2. The GND pin is the chip's ground pin. The ZVT pin is electrically connected to the negative input terminal of the analog comparator CMP.

8. The LED linear control chip with thyristor detection according to claim 7, characterized in that, The DRNB and DRN pins are arranged sequentially at the top of the chip body along the left-right direction, the ZVT pin is arranged on the left side of the chip body, and the VCC, GND, CS and CSB pins are arranged sequentially at the bottom of the chip body along the left-right direction.

9. An LED linear driving circuit, characterized in that, The LED linear control chip with thyristor detection as described in any one of claims 1-8 further includes resistors R1-R5, capacitors C1 and C2, diode D1, and a rectifier bridge. The positive output terminal of the rectifier bridge is electrically connected to one end of resistor R1, one end of resistor R3, and the anode of diode D1, respectively. The other end of resistor R1 is electrically connected to one end of resistor R2 and the negative input terminal of analog comparator CMP, respectively. The other end of resistor R2 is grounded, and the other end of resistor R3 is electrically connected to the input terminal of transistor JFET. The output terminal of transistor JFET is grounded through capacitor C1. The output terminal of first switch Q1 is grounded through resistor R4, and the output terminal of second switch Q2 is grounded through resistor R5. The cathode of diode D1 is electrically connected to one end of capacitor C2, and the other end of capacitor C2 is used to be electrically connected to the input terminal of first switch Q1. The two ends of capacitor C2 are also used to be connected in parallel with the load LED.

10. The LED linear driving circuit according to claim 9, characterized in that, The input terminal of the rectifier bridge is also electrically connected to a thyristor.

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