测试结构

Abstract

本申请涉及半导体领域，具体提供一种测试结构，旨在解决在对半导体进行热载流子注入效应测试时，测试单元的测试效率低的技术问题。为此目的，本申请的测试结构包括：多个MOS器件，每个MOS器件均包括位于衬底中的源区、漏区、位于源区与漏区之间且间隔设置的轻掺杂漏区、以及位于衬底上的栅极，栅极与轻掺杂漏区具有交叠区；其中，在多个MOS器件中，至少有两个MOS器件的交叠区面积不同或沟道长度不同；每个MOS器件的源区均通过源极金属走线连接至源极焊盘，每个MOS器件的栅极均通过栅极金属走线连接至栅极焊盘，多个MOS器件的漏区各自通过漏极金属走线分别连接到对应的漏极焊盘，衬底引出环通过引出金属走线连接到引出焊盘。

Claims

1. A test structure, comprising: A plurality of MOS devices are arranged at intervals. Each MOS device includes a source region, a drain region, a lightly doped drain region located between the source and drain regions and spaced apart, and a gate structure located on the substrate. A channel is formed between the source and drain regions. The gate structure includes a stacked gate dielectric layer and a gate. The gate and the lightly doped drain region have an overlapping region when projected onto the surface of the substrate. Among the plurality of MOS devices, at least two MOS devices have different overlapping region areas or different channel lengths. A substrate lead-out ring formed in the substrate, the orthographic projection of the substrate lead-out ring on the substrate surface surrounding the plurality of MOS devices; A metal wiring layer includes multiple pads and multiple metal traces; the orthographic projections of the multiple pads on the substrate surface are all located outside the orthographic projection of the substrate lead-out ring on the substrate surface; the multiple pads include a source pad, a gate pad, multiple drain pads, and a lead-out pad; the multiple metal traces include source metal traces, gate metal traces, multiple drain metal traces, and lead-out metal traces, wherein the source region of each MOS device is connected to the source pad through the source metal trace, the gate of each MOS device is connected to the gate pad through the gate metal trace, the drain regions of the multiple MOS devices are each connected to their respective drain pads through drain metal traces, and the substrate lead-out ring is connected to the lead-out pad through lead-out metal traces.

2. The test structure of claim 1, wherein, The plurality of MOS devices are arranged along the channel width direction; The source regions of the multiple MOS devices are located on the same side, and the drain regions are located on the same side.

3. The test structure of claim 1, wherein, It also includes shallow trench isolation regions located in the substrate for separating adjacent MOS devices.

4. The test structure according to any of claims 1-3, characterized in that, Among the plurality of MOS devices: at least two MOS devices have different overlap area and the same channel length; or, at least two MOS devices have the same overlap area and different channel length.

5. The test structure of claim 4, wherein, In the plurality of MOS devices, each MOS device has the same channel length and a different area of ​​the overlapping region.

6. The test structure of claim 4, wherein, In the plurality of MOS devices, the channel lengths of each MOS device are different, and the areas of the overlapping regions are all the same.

7. The test structure according to claim 4, characterized in that, The test structure includes multiple groups of MOS devices, each group of MOS devices includes multiple MOS devices, the overlapping area of ​​the MOS devices in each group is the same but the channel length is different, and the overlapping area between groups is different.

8. The test structure of claim 1, wherein, It also includes a well region located in the substrate; the substrate lead-out ring, the source region and the drain region are all located in the well region.

9. The test structure of claim 1, wherein, It also includes an isolation dielectric layer located on the substrate and the gate structure. The isolation dielectric layer has multiple through holes, and the through holes are provided with metal plugs. The metal plugs are used to connect the source region, drain region, gate, substrate lead-out ring and corresponding metal traces, respectively.

10. The test structure of claim 1 or 9, wherein, The gate structure also includes sidewalls located on both sides of the gate.

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