Interconnect structure and semiconductor power module

Abstract

The utility model relates to the technical field of semiconductor, disclose a kind of interconnection structure and semiconductor power module. The interconnection structure includes: substrate, at least one power chip and connecting key;Power chip includes at least one layer of first metallization layer arranged on upper surface and at least one layer of second metallization layer arranged on lower surface;The surface of substrate is provided with first active plating and / or first planarization surface, and second metallization layer is interconnected with first active plating and / or first planarization surface;The surface of connecting key connects the upper surface of power chip and substrate. By the above-mentioned mode, the utility model can save cost and reduce process risk, improve the reliability of semiconductor power module.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to an interconnect structure and a semiconductor power module. Background Technology

[0002] As new energy vehicles develop towards higher power density and higher reliability, the requirements for electrical performance and packaging of power devices and modules are becoming increasingly stringent. To meet these demands, silicon carbide power devices and modules are gaining popularity. In terms of packaging, advanced interconnect technologies, high-performance packaging materials, low stray inductance, and high heat dissipation performance are also becoming industry trends.

[0003] Currently, the power module packaging structure of related technologies generally includes a ceramic copper-clad substrate, a power chip, metal wires, a lead frame, and a plastic encapsulation shell. The packaging method is as follows: Tin-based solder or sintering material (generally silver-based high-temperature paste) is coated onto the upper circuit copper layer surface of the ceramic copper-clad substrate corresponding to the power chip location; the power chip is then sequentially attached to its corresponding position, and its lower surface is reflow soldered or pressure sintered; the ceramic copper-clad substrate and lead frame are fixedly installed using a positioning fixture, and the pre-coated solder at the connection point is vacuum reflow soldered; the upper surface of the power chip is then connected to the circuit layer of the ceramic copper-clad substrate using metal wires (generally ultrasonic welding); the completed product with surface mount wire bonding is placed in an injection mold for injection molding to form a plastic encapsulation shell; the connecting frame portion of the lead frame is cut off, and the pins are bent into the required shape (for PCB board mounting). The metal wires and lead frame serve as circuit conductors, enabling internal and external circuit interconnection.

[0004] The above power module packaging structure has the following disadvantages:

[0005] (1) The connection between power chips and metal frames (busbars) or copper-clad ceramic substrates often relies on silver-based sintering paste, which has a high material cost;

[0006] (2) Solder and paste may experience problems such as dimensional shrinkage and overflow during drying, sintering and other processes, which may affect accuracy and even insulation performance.

[0007] (3) The silver-based sintering paste process requires a silver layer to be pre-placed on the surface of the metal frame (busbar) or copper-clad ceramic substrate. As a result, there are reliability issues such as silver migration, high-temperature oxidation and plating dewetting between the silver / copper interface and the silver / pre-placed silver interface of the paste.

[0008] (4) The multilayer metal interface structure has large stray inductance and high loss. Utility Model Content

[0009] This invention provides an interconnection structure and a semiconductor power module that can solve the above-mentioned problems.

[0010] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: providing an interconnection structure, comprising:

[0011] At least one power chip, the power chip comprising at least one first metallization layer disposed on the upper surface and at least one second metallization layer disposed on the lower surface;

[0012] A substrate, wherein the surface of the substrate is provided with a first activated plating layer and / or a first planarization surface, and the second metallization layer is interconnected with the first activated plating layer and / or the first planarization surface;

[0013] A connecting key connects the upper surface of the power chip to the surface of the substrate.

[0014] According to one embodiment of the present invention, the first activated coating is a single layer or a composite layer.

[0015] According to one embodiment of the present invention, the first metallization layer and the second metallization layer may have the same or different number of layers.

[0016] According to one embodiment of the present invention, the substrate of the power chip is provided with a microtrench array structure, and the second metallization layer is located on the surface of the microtrench array structure.

[0017] According to one embodiment of the present invention, the microgroove array structure includes a plurality of microgrooves arranged in an array, the depth of the microgrooves is 10-2000nm, and the ratio between the width of the top of the dam and the width of the bottom of the dam in the microgroove array structure is 0.1-10.

[0018] According to one embodiment of the present invention, the interconnection structure further includes a copper foil layer disposed on the upper surface of the power chip, the copper foil layer being used to connect the connection key.

[0019] According to one embodiment of the present invention, the surface of the copper foil layer is provided with a second activated plating layer and / or a second planarized surface.

[0020] According to one embodiment of the present invention, the interconnection structure further includes a heat sink, which is connected to the back side of the substrate.

[0021] According to one embodiment of the present invention, the back side of the substrate and / or the surface of the heat sink are provided with a third activated plating layer and / or a third planarized surface.

[0022] To solve the above-mentioned technical problems, another technical solution adopted by this utility model is to provide a semiconductor power module, including: a housing, the interconnection structure, and terminals for connecting the interconnection structure to an external circuit.

[0023] The beneficial effects of this utility model are as follows: An interconnect structure includes: at least one power chip, the power chip including at least one first metallization layer disposed on the upper surface and at least one second metallization layer disposed on the lower surface; a substrate, the surface of the substrate having a first activated plating layer and / or a first planarization surface, the second metallization layer being interconnected with the first activated plating layer and / or the first planarization surface; and a connecting key, the connecting key connecting the upper surface of the power chip to the surface of the substrate. Compared with traditional interconnection methods, the connection between the power chip and the substrate does not rely on silver-based sintering paste, which not only saves energy... It reduces the cost of slurry and the investment in equipment and energy consumption related to printing processes. It also solves problems such as dimensional shrinkage, slurry overflow, and chip tilting caused by slurry drying and sintering processes, thus improving assembly accuracy. In addition, it eliminates the need for a pre-plated silver layer on the substrate surface, saving costs and reducing process risks. It also avoids reliability issues such as silver migration, high-temperature oxidation, and plating dewetting between the silver / copper interface and between the slurry silver and the pre-plated silver interface. Furthermore, due to the simplified structure of the interface metallization layer, the corresponding thermal conductivity, electrical conductivity, and anti-stray performance are also improved, thereby enhancing the reliability of semiconductor power modules. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the interconnection structure according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the interconnection structure according to another embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the interconnection structure according to another embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the interconnection structure according to another embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of the interconnection structure according to another embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the interconnection structure according to another embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the interconnection structure according to another embodiment of the present invention.

[0031] The meanings of the labels in the attached diagram are as follows:

[0032] 100 - Interconnect structure; 10 - Power chip; 20 - First activated plating layer and / or first planarization surface; 30 - Substrate; 40 - Connector; 50 - Second metallization layer; 60 - Copper foil layer; 70 - Heat sink; 80 - First metallization layer; 31 - Circuit copper layer; 32 - Insulating layer; 33 - Heat dissipation copper layer; 51 - Micro trench; 21 - Second activated plating layer and / or second planarization surface; 22 - Third activated plating layer and / or third planarization surface. Detailed Implementation

[0033] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present utility model, and not all of them. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0034] The terms "first," "second," and "third" in this utility model are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this utility model are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0035] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0036] Figure 1 This is a schematic diagram of the interconnection structure according to an embodiment of the present invention. Figure 1As shown, the interconnect structure 100 includes at least one power chip 10, a substrate 30, and a connecting bond 40. The power chip 10 includes at least one first metallization layer 80 on its upper surface and at least one second metallization layer 50 on its lower surface. The surface of the substrate 30 is provided with a first activation plating layer and / or a first planarization surface 20, and the second metallization layer 50 is interconnected with the first activation plating layer and / or the first planarization surface 20. The connecting bond 40 connects the upper surface of the power chip 10 to the surface of the substrate 30.

[0037] Please see Figure 2 The interconnect structure 100 can be fabricated using the following method:

[0038] Step S1: Provide a substrate and at least one power chip;

[0039] Step S2: When there is no preset metallization layer on the upper surface and / or lower surface of the power chip, a first metallization layer is preset on the upper surface of the power chip and / or a second metallization layer is preset on the lower surface of the power chip.

[0040] In step S2, "no preset metallization layer" means that a metallization layer may not exist, or a metallization layer may exist but its outermost layer is not the preset metallization layer. When the upper and / or lower surfaces of the power chip do not have a preset metallization layer, a metallization layer needs to be fabricated according to the actual application. The metallization layer can be a single layer or multiple layers, and each layer can be made of a single metal, alloy, or compound.

[0041] As one embodiment, when at least one metallization layer exists on the upper and / or lower surfaces of the power chip 10, and the outermost layer of the metallization layer is not a preset metallization layer, a first metallization layer 80 is pre-formed on the upper surface of the power chip 10 and / or a second metallization layer 50 is pre-formed on the lower surface of the power chip 10. In this embodiment, the first metallization layer 80 and / or the second metallization layer 50 are preset metallization layers, and the materials of the first metallization layer 80 and the second metallization layer 50 can be the same or different.

[0042] As one embodiment, when there is no metallization layer on the upper surface and / or lower surface of the power chip 10, at least one first metallization layer 80 is pre-formed on the upper surface of the power chip 10 and / or at least one second metallization layer 50 is pre-formed on the lower surface of the power chip 10. In this embodiment, the materials of the first metallization layer 80 and the second metallization layer 50 can be the same or different.

[0043] Wherein, when the number of layers of the first metallization layer 80 is 1, this layer is the outermost layer; when the number of layers of the first metallization layer 80 is greater than 1, the outermost layer is the most surface layer. The outermost layer of the first metallization layer 80 is a predetermined metallization layer, which can be a single metal, alloy, or compound. For example, the outermost layer of the first metallization layer 80 can be one of Au, Cu, Ag, Al, Ni, Pd, Zn, and Pt layers.

[0044] When the number of layers in the second metallization layer 50 is 1, this layer is the outermost layer; when the number of layers in the second metallization layer 50 is greater than 1, the outermost layer is the most surface layer. The outermost layer of the second metallization layer 50 is a predetermined metallization layer, which can be a single metal, alloy, or compound. For example, the outermost layer of the second metallization layer 50 can be one of Au, Cu, Ag, Al, Ni, Pd, Zn, and Pt layers.

[0045] Step S3: Perform activation coating treatment and / or planarization treatment on the substrate surface to form an activation coating and / or planarization surface;

[0046] In step S3, the first activated plating layer and / or the first planarization surface 20 can reduce the connection difficulty between the substrate 30 and the power chip 10. The preparation methods of the first activated plating layer include, but are not limited to, electroplating, electroless plating, physical vapor deposition, chemical vapor deposition, and mechanical cold spraying. The preparation methods of the first planarization surface include, but are not limited to, electrolytic polishing, machining, mechanical grinding, mirror finishing, and mechanical chemical grinding. In one feasible embodiment, only the surface of the substrate 30 is treated with the activated plating layer. In another feasible embodiment, only the surface of the substrate 30 is planarized. In yet another feasible embodiment, the activated plating layer treatment and planarization treatment of the substrate 30 surface can be understood as follows: first, the surface of the substrate 30 is treated with the activated plating layer to form the first activated plating layer, and then the activated plating layer is planarized to form the first planarization surface.

[0047] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated plating layer and / or planarized surface.

[0048] In step S4, please refer to Figure 1 The power chip 10 is placed on the substrate 30, with the first activated plating layer and / or the first planarization surface 20 facing the power chip 10. In a hot-press diffusion apparatus, it is sintered for 1-60 minutes at a temperature of 180-300°C and a pressure of 1-30 MPa to achieve interconnection between the first activated plating layer and / or the first planarization surface 20 and the second metallization layer 50, thus completing the interconnection between the substrate 30 and the power chip 10.

[0049] Step S5: Connect the upper surface of the power chip to the substrate using a connector to obtain an interconnect structure.

[0050] In this step, the connecting key includes wire bonding, metal strips, or clips.

[0051] The interconnect structure 100 is connected to the power chip 10 via diffusion between the substrate 30 and the power chip 10. It does not rely on sintering paste, which not only saves paste costs and equipment investment and energy consumption related to printing processes, but also solves problems such as dimensional shrinkage, paste overflow, and chip tilting caused by paste drying and sintering processes, thus improving assembly accuracy. In addition, there is no need to pre-plat a silver layer on the substrate surface, which saves costs and reduces process risks, while also avoiding reliability issues such as silver migration, high-temperature oxidation, and plating dewetting between the silver / copper interface and between the paste silver and pre-plated silver interface. Furthermore, since the structure of the interface metallization layer is simplified, the corresponding thermal conductivity, electrical conductivity, and anti-stray performance are also improved.

[0052] As one example, please refer to Figure 1 The substrate 30 includes a ceramic copper-clad substrate, a metal frame or a metal busbar, wherein the ceramic copper-clad substrate includes a circuit copper layer 31, an insulating layer 32 and a heat dissipation copper layer 33 arranged sequentially from top to bottom.

[0053] For example, please see Figure 1 When the substrate 30 is a ceramic copper-clad substrate, the interconnect structure 100 includes a first metallization layer 80, a power chip 10, a second metallization layer 50, a first activation plating layer and / or a first planarization surface 20 and the substrate 30 arranged sequentially from top to bottom. The second metallization layer 50 is located on the lower surface of the power chip 10 and is opposite to the first activation plating layer and / or the first planarization surface 20. The power chip 10 is connected to the substrate 30 through a connecting key 40.

[0054] As one example, please refer to Figure 3 The power chip 10 has a microtrench array structure on its substrate, and a second metallization layer 50 is located on the surface of the microtrench array structure. Further, the microtrench array structure includes multiple microtrenches 51 arranged in an array. The depth H of the microtrench 51 is 10-2000 nm, and the ratio between the width W1 at the top of the dam and the width W2 at the bottom of the dam is 0.1-10. The array shape of the microtrench 51 can be rectangular, square, spiral, or concentric circles, etc., and is not specifically limited here. The microtrench array structure can improve the connection strength between the power chip 10 and the substrate 30.

[0055] As one embodiment, the first activated coating is a single layer or a composite layer, and the outermost layer of the activated coating is a single metal, alloy, or compound. For example, when the first activated coating is a composite layer, the outermost layer of the first activated coating is one of Au, Cu, Ag, Al, Ni, Pd, Zn, and Pt coatings.

[0056] As one example, please refer to Figure 4 The interconnect structure 100 further includes a copper foil layer 60 disposed on the upper surface of the power chip 10, the copper foil layer 60 being used to connect the connecting bond 40. That is, the interconnect structure 100 includes, from top to bottom, a copper foil layer 60, a first metallization layer 80, a power chip 10, a second metallization layer 50, a first activation plating layer and / or a first planarization surface 20, and a substrate 30.

[0057] As one example, please refer to Figure 5 The lower surface of the copper foil layer 60 is provided with a second activated plating layer and / or a second planarization surface 21. That is, the interconnect structure 100 includes, from top to bottom, a copper foil layer 60, a second activated plating layer and / or a second planarization surface 21, a first metallization layer 80, a power chip 10, a second metallization layer 50, a first activated plating layer and / or a first planarization surface 20, and a substrate 30. The lower surface of the copper foil layer 60 undergoes activated plating and / or planarization treatment, enabling it to be directly connected to the first metallization layer 80. No pre-placed nano-silver film or other connecting materials are required between the lower surface of the copper foil layer 60 and the upper surface of the power chip 10. Compared with traditional on-chip copper layer processes, this simplifies the fabrication process and saves material costs.

[0058] As one example, please refer to Figure 6 The interconnect structure 100 also includes a heat sink 70, which is connected to the back side of the substrate 30. The heat sink 70 helps dissipate heat from the interconnect structure 100, preventing the interconnect structure 100 from overheating and affecting its performance.

[0059] As one example, please refer to Figure 7 The back side of the substrate 30 and / or the surface of the heat sink 70 are provided with a third activating plating layer and / or a third planarization surface 22. Taking the back side of the substrate 30 as an example where the third activating plating layer and / or the third planarization surface 22 is provided, the interconnect structure 100 includes, from top to bottom, a copper foil layer 60, a second activating plating layer and / or a second planarization surface 21, a first metallization layer 80, a power chip 10, a second metallization layer 50, a first activating plating layer and / or a first planarization surface 20, a substrate 30, a third activating plating layer and / or a third planarization surface 22, and a heat sink 70, wherein the substrate 30 is a ceramic copper-clad substrate.

[0060] This embodiment performs an activation plating treatment and / or planarization treatment on the back side of the substrate 30 and / or the surface of the heat sink 70, enabling the back side of the substrate 30 and / or the surface of the heat sink 70 to be directly connected. The heat sink 70 can be connected to the back side of the substrate 30 through a hot-pressing sintering process, without the need for connecting materials such as tin-based solder. Compared with traditional interconnect structures, the interconnect structure 100 of this embodiment does not require connecting materials such as tin-based solder to connect the heat sink 70 and the substrate 30, thereby avoiding the problem of high material costs caused by a large connection area between the substrate 30 and the heat sink 70, which would result in a large amount of solder or sintering paste.

[0061] An embodiment of this utility model also provides a semiconductor power module, including: a housing, an interconnection structure 100 disposed in the housing, and terminals for connecting the interconnection structure to an external circuit. The terminals include signal terminals and functional terminals.

[0062] The above are merely embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. An interconnection structure, characterized in that, include: At least one power chip, the power chip comprising at least one first metallization layer disposed on the upper surface and at least one second metallization layer disposed on the lower surface; A substrate, wherein the surface of the substrate is provided with a first activated plating layer and / or a first planarization surface, and the second metallization layer is interconnected with the first activated plating layer and / or the first planarization surface; A connecting key connects the upper surface of the power chip to the surface of the substrate.

2. The interconnection structure according to claim 1, characterized in that, The first activated coating is a single layer or a composite layer.

3. The interconnection structure according to claim 1, characterized in that, The first metallization layer and the second metallization layer may have the same or different number of layers.

4. The interconnection structure according to claim 1, characterized in that, The power chip has a microtrench array structure on its substrate, and the second metallization layer is located on the surface of the microtrench array structure.

5. The interconnection structure according to claim 4, characterized in that, The microgroove array structure includes multiple microgrooves arranged in an array, the depth of the microgrooves is 10-2000nm, and the ratio between the width of the top of the dam and the width of the bottom of the dam is 0.1-10.

6. The interconnection structure according to claim 1, characterized in that, The interconnect structure further includes a copper foil layer disposed on the upper surface of the power chip, the copper foil layer being used to connect the connection key.

7. The interconnection structure according to claim 6, characterized in that, The surface of the copper foil layer is provided with a second activated plating layer and / or a second planarized surface.

8. The interconnection structure according to claim 1, characterized in that, The interconnect structure further includes a heat sink, which is connected to the back side of the substrate.

9. The interconnection structure according to claim 8, characterized in that, The back side of the substrate and / or the surface of the heat sink are provided with a third activated plating layer and / or a third planarization surface.

10. A semiconductor power module, characterized in that, include: The housing, the interconnection structure as described in any one of claims 1-9, and the wiring terminals for connecting the interconnection structure to an external circuit.

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