A new driving system for panels of DGL

Abstract

The utility model discloses a new DGL's Panel's drive system, include: control chip TCON, drive chip and liquid crystal panel Panel, control chip TCON is connected with drive chip, is used for according to external signal output control signal and drive signal, the output of drive chip is connected with liquid crystal panel Panel, is used for according to control signal, drive signal, with the picture data signal of timing output required by liquid crystal panel, liquid crystal panel is used for corresponding display according to picture data signal. The utility model adopts 6port3pair's Minilvds interface architecture, from process to test, greatly reduced the cost of cof, in addition 6port3pair's Minilvds interface architecture can realize the parallel processing of data, promoted the data transmission efficiency of single cof, thereby make the transmission efficiency of Panel's drive system greatly improve.

Description

Technical Field

[0001] This utility model belongs to the field of panel driving technology, specifically relating to a new DGL panel driving system. Background Technology

[0002] As panel manufacturers across the country gradually release their production capacity, the panel market is in a state of oversupply, and panel prices have been declining. Panel manufacturers are also actively researching various cost reduction technologies.

[0003] In TV display driver architecture, the source cof is the main component driving the source line of the TFT LCD, responsible for outputting the display voltage. Traditional driver systems mostly choose a 12-pin MiniLVDS interface or P2P interface cof architecture. To save costs, a 6-pin P2P interface cof architecture has been introduced on the market; however, although the transmission speed of the P2P interface cof is faster, its cost is too high, which would lead to excessively high production costs if used for mass production. On the other hand, the traditional MiniLVDS cof has the problem of slow transmission speed and does not support the 6-pin cof architecture. Utility Model Content

[0004] To address the aforementioned problems in the existing technology, this utility model provides a novel driving system for DGL panels. The technical problem to be solved by this utility model is achieved through the following technical solution: This utility model embodiment provides a new driving system for DGL panels, including: The control chip TCON, the driver chip, and the LCD panel; among them, The control chip TCON is connected to the driver chip and is used to output control signals and drive signals according to external signals. The output terminal of the driver chip is connected to the LCD panel and is used to output screen data signals according to the timing required by the LCD panel based on the control signals and drive signals; the driver chip adopts a 6-port 3-pair Minilvds interface architecture. The LCD panel is used to display images according to the image data signals.

[0005] In one embodiment of this utility model, the driver chip includes: Six parallel Minilvds interfaces cof.

[0006] In one embodiment of this utility model, each cof in the driver chip is connected to the control chip TCON via the Minilvds interface.

[0007] In one embodiment of this utility model, the driver chip adopts a 6-port 3-pair Minilvds interface architecture, including: It has 6 independent ports and 3 pairs of signal divisions.

[0008] In one embodiment of this utility model, the liquid crystal panel adopts a 1D2G architecture or a 1G1D architecture.

[0009] In one embodiment of this invention, the 1G1D architecture consists of a data conversion channel and a single gamma voltage generator.

[0010] In one embodiment of this invention, the 1D2G architecture consists of a data conversion channel and a dual gamma voltage generator.

[0011] The beneficial effects of this utility model are: The solution provided in this embodiment of the utility model adopts a 6-port 3-pair Minilvds interface architecture for the driver chip, replacing the 6-P2P interface COF architecture used in the traditional technology with a 6-port 3-pair Minilvds interface. From the manufacturing process to testing, the cost of COF is greatly reduced. In addition, the 6-port 3-pair Minilvds interface architecture can realize parallel data processing, improve the data transmission efficiency of a single COF, thereby greatly improving the transmission efficiency of the panel's driving system. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the drive system for a traditional 12cof architecture panel. Figure 2 This is a schematic diagram of the drive system for another traditional 12cof architecture panel; Figure 3 This is a schematic diagram of the drive system for a newly launched 6cof architecture panel on the market. Figure 4 This is a schematic diagram of the drive system for a newly introduced 6cof architecture Panel. Figure 5 A schematic diagram of the structure of a new DGL panel driving system provided for an embodiment of this utility model; Figure 6 A schematic diagram of a new DGL panel driving system with a 1D2G architecture provided for an embodiment of this utility model; Figure 7 This is a schematic diagram of a new DGL panel driving system with a 1G1D architecture provided in an embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0014] A schematic diagram of a traditional panel drive system, such as... Figure 1 As shown, Figure 1 This corresponds to the traditional 12cof architecture panel. The driver chip in the driver system adopts a Minilvds interface architecture with 4 ports (groups) and 6 pairs (pairs), with a speed of 300M / pair. This driver is a multi-drop architecture. A schematic diagram of the driver system structure for another traditional 12cof architecture panel is shown below. Figure 2 As shown, Figure 2 The corresponding driver system adopts a point-to-point architecture, requiring 12 pairs, with a transmission rate of 1.6G / pair. It can be seen that this driver system requires 12 cofs.

[0015] Figure 1 The traditional panel driver system shown uses a Minilvds cof architecture of 4 ports and 6 pairs. This means that when transmitting data in each group, the data of each cof chip under its responsibility needs to be transmitted sequentially, cof1->cof2->cof3... This cannot be output in parallel and wastes a lot of time. Therefore, it cannot support the 6cof architecture and can only support the traditional 12cof architecture.

[0016] A schematic diagram of the driver system for newly launched 6cof architecture panels on the market, such as... Figure 3 , Figure 4 As shown, it can be seen that Figure 3 The corresponding driving system requires 6 COFs, which is half the number compared to the traditional 12-COF architecture driving system. However, the gate for controlling the TFT LCD in this driving system is twice that of the traditional driving system. This can be understood as follows: although this driving system saves 6 COFs, it still uses P2P COFs, and because the data volume remains the same, each COF changes from 1-pair P2P to 2-pair P2P, making the cost per COF too high.

[0017] Figure 4The corresponding driving system adopts a new panel architecture, changing from the traditional 3840*2160 to 2560*3240. The gate of the TFT LCD controlled by this driving system is 1.5 times that of the traditional driving system. Although it also saves 6 COFs, it still uses P2P COFs. Furthermore, because the amount of data remains unchanged, each COF has changed from 1 pair P2P to 2 pair P2P, making the cost of each COF too high.

[0018] Both of the above 6COF architectures use P2P interfaces for transmission. However, P2P COFs are too expensive, and each COF chip needs to be changed from 1 pair to 2 pairs. The traditional Minilvds COF architecture is 4-port 6-pair, with a transmission rate of 300M / pair, and does not support the 6COF architecture. Due to its high-speed performance in manufacturing and testing, the P2P interface is more expensive than the new high-speed Minilvds interface COF. However, its output needs to transmit some control signals, gamma signals, and other functional signals such as CRC. Some customized P2P interfaces add additional control functions, and with their own characteristic IP, such as 8B10B (which increases the amount of video data transmission), in addition to transmitting the effective video data, these added functional data also consume bandwidth, resulting in a decrease in actual data transmission efficiency.

[0019] To address the aforementioned problems, this invention provides a novel DGL (Dual Gata Like) panel driving system, such as... Figure 5 As shown, it may include: The control chip TCON, the driver chip, and the LCD panel; among them, The control chip TCON is connected to the driver chip and is used to output control signals and drive signals according to external signals. The output of the driver chip is connected to the LCD panel and is used to output screen data signals according to the timing required by the LCD panel based on the control signals and drive signals. The driver chip adopts a 6-port 3-pair Minilvds interface architecture. An LCD panel is used to display images based on data signals.

[0020] The driver chip may include: Six parallel cofs.

[0021] Each cof in the driver chip is connected to the control chip TCON via the Minilvds interface.

[0022] The driver chip adopts a 6-port 3-pair miniLVDS interface architecture and may include: It has 6 independent ports and 3 pairs of signal divisions.

[0023] Applied to a 6cof architecture panel, using the Minilvds signal interface, each cof contains 3 pairs of data transmission channels, each cof works independently, and the 6 cofs can output in parallel.

[0024] The 6cof architecture LCD panel can adopt a 1D2G architecture or a new 1G1D architecture.

[0025] 1D2G architecture, such as Figure 6 As shown, in order to reduce the number of source cofs, this embodiment of the invention adopts a 1D2G Panel architecture. This architecture can reduce the number of source lines by half compared to 1G1D, but the number of gates controlling the TFT LCD is twice that of 1G1D. The specific architecture is shown in the figure. Taking UD (3840*2160) as an example, with 960 source channels, 6 source cofs are required (6 * 960 = 5760 = 11520 / 2). This architecture can save 6 source cofs.

[0026] The new 1G1D architecture, such as Figure 7 As shown, the architecture is further divided into several sub-branches. This utility model takes one of them as an example, and other architecture drivers should also be within the protection scope of this utility model. The source cof of this architecture is 1280 channels, so this new architecture requires 7680 / 1280=6 cofs, which saves 6 cofs compared to the normal architecture (1G1D 3840*2160).

[0027] Both the 1D2G and 1G1D architectures proposed above can use the Minilvds 6-port 3-pair architecture. The high-speed Minilvds has a speed of 400Mbps and a data transmission rate of 2.4Gbps / pair. Since Minilvds only transmits valid video data, it can meet the requirements for 4K video data transmission. The 6COF architecture designed in this embodiment replaces the P2P interface with the Minilvds interface, effectively reducing COF costs.

[0028] This utility model embodiment adopts a 6-port 3-pair Minilvds interface architecture for the driver chip, replacing the P2P interface used in traditional technology with the Minilvds interface, which greatly reduces the cost of COF from process to testing; in addition, the 6-port 3-pair Minilvds interface architecture can realize parallel data processing, improve the data transmission efficiency of a single COF, thereby greatly improving the transmission efficiency of the panel's driver system.

[0029] It should be noted that the above description is merely a preferred embodiment of the present utility model and is not intended to limit the scope of protection of the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model are included within the scope of protection of the present utility model.

Claims

1. A novel driving system for a DGL panel, characterized in that, include: The control chip TCON, the driver chip, and the LCD panel; among them, The control chip TCON is connected to the driver chip and is used to output control signals and drive signals according to external signals. The output terminal of the driver chip is connected to the LCD panel and is used to output screen data signals according to the timing required by the LCD panel based on the control signals and drive signals; the driver chip adopts a 6-port 3-pair Minilvds interface architecture. The LCD panel is used to display images according to the image data signals.

2. The new DGL panel driving system according to claim 1, characterized in that, The driver chip includes: Six parallel Minilvds interfaces cof.

3. The new DGL panel driving system according to claim 2, characterized in that, Each cof in the driver chip is connected to the control chip TCON via the Minilvds interface.

4. The new DGL panel driving system according to claim 1, characterized in that, The driver chip adopts a 6-port 3-pair Minilvds interface architecture, including: It has 6 independent ports and 3 pairs of signal divisions.

5. A novel DGL panel driving system according to claim 1, characterized in that, The LCD panel adopts a 1D2G architecture or a 1G1D architecture.

6. A novel DGL panel driving system according to claim 5, characterized in that, The 1G1D architecture consists of a data conversion channel and a single gamma voltage generator.

7. A novel DGL panel driving system according to claim 5, characterized in that, The 1D2G architecture consists of a data conversion channel and dual gamma voltage generators.

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