A current correction circuit, a current steering DAC and an electronic device

Abstract

The application relates to a current correction circuit, a current steering DAC and an electronic device. The current correction circuit comprises a resistor, a current source group and a switch group. The current source group comprises first and second current sources. One end of the resistor is connected to a power supply or ground. The sources / emitters of the two current sources are connected to the other end of the resistor. The two ends of a first switch group in the i-th switch group are connected to first and second bias voltages respectively. The connection ends of two switches in the first switch group are connected to the control end of the first current source. The two ends of a second switch group in the i-th switch group are connected to the first and second bias voltages respectively. The connection ends of two switches in the second switch group are connected to the control end of the second current source. The switch group makes the first current source and the second current source in the current source group connected to the switch group to be turned on and turned off staggered and makes the drain / collector of one current source in the current source group output a correction current. The application has the advantages of low mismatch, low temperature drift, simple structure and low cost.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a current correction circuit with low mismatch, a current steering DAC, and an electronic device. Background Technology

[0002] With the continuous development and advancement of electronic products, more and more electronic products require circuits with lower current mismatch. Digital-to-analog converters (DACs), in particular, require low current mismatch. DACs can convert digital signals to analog signals, so their applications are very widespread. Current-steering DACs, as an important DAC implementation architecture, are commonly used in high-speed, high-precision applications. Current-steering DACs are typically composed of basic current source weighting units, which sum the current source weights based on the input digital signal to obtain the corresponding analog signal.

[0003] The traditional current-driven DAC structure is shown in the attached figure. Figure 1 Taking into account factors such as speed, area, power consumption, matching, and performance, current-controlled DACs are typically composed of segmented current sources, with different segments representing different weights. Typically, the weights of higher-order segments are composed of identical weights encoded by thermometers, while the weights of lower-order segments are composed of binary weights encoded by binary codes.

[0004] Considering actual manufacturing processes, the current weights output by the current source weighting unit (i.e., the aforementioned current source weights) will deviate from the designed weights. The accuracy of the current source weights directly affects the overall performance of the current-driven DAC. To achieve a high-precision current-driven DAC, it is usually necessary to correct or compensate for the current source weights. This correction or compensation can be performed in the digital domain or the analog domain. However, with the development of advanced semiconductor manufacturing processes, especially current deep submicron processes such as 7nm and 3nm, the channel modulation effect of devices is more severe, and device matching is more sensitive. Existing methods for compensating current source weights result in poor current source accuracy, mismatch, and temperature drift due to mismatch, which in turn significantly reduces the overall performance of the current-driven DAC.

[0005] Therefore, it is important to achieve current correction while also improving the accuracy, mismatch, and temperature drift of the current during correction. Furthermore, it is necessary to consider the complex structure, high cost, and poor stability of the corresponding current correction circuit. Summary of the Invention

[0006] To address some or all of the aforementioned technical problems, this application provides a current correction circuit, a current steering DAC, and an electronic device.

[0007] The current correction circuit provided in this application includes: a resistor R1; N current source groups; and N switch groups corresponding one-to-one with the N current source groups. The switch groups are used to stagger the on / off states of the first and second current sources in the current source groups connected to the switch group, and to output a correction current from the drain / collector of one current source in the current source group, for correcting the current I being corrected. m Each current source group includes a first current source Msci and a second current source Msi, 1≤i≤N. The source / emitter of each current source in each current source group is electrically connected to the other end of the resistor R1, one end of the resistor R1 is connected to a power supply or ground. Each switch group includes a first switch group and a second switch group. Both the first and second switch groups include two switches connected in series. When one switch in the first switch group of the i-th switch group is closed, the other switch in the first switch group is open. When one switch is closed, the other switch in the second switch group is open; the two ends of the first switch group in the i-th switch group are electrically connected to the first bias voltage and the second bias voltage respectively, the connection ends of the two switches in the first switch group in the i-th switch group are electrically connected to the control terminal of the first current source of the i-th current source group, the two ends of the second switch group in the i-th switch group are electrically connected to the first bias voltage and the second bias voltage respectively, and the connection ends of the two switches in the second switch group in the i-th switch group are electrically connected to the control terminal of the second current source of the i-th current source group.

[0008] In a preferred embodiment, both the first current source and the second current source are PMOS current sources. One end of the resistor R1 is connected to a power supply, and the sources of the two current sources in each current source group are electrically connected to the other end of the resistor R1. The two ends of the first switch group in the i-th switch group are electrically connected to a first bias voltage and a second bias voltage, respectively. The connection terminals of the two switches in the first switch group in the i-th switch group are electrically connected to the gate of the first current source in the i-th current source group. The two ends of the second switch group in the i-th switch group are electrically connected to the first bias voltage and the second bias voltage, respectively. The connection terminals of the two switches in the second switch group in the i-th switch group are electrically connected to the gate of the second current source in the i-th current source group. The current output from the drain of the first current source in each current source group is used to correct the corrected current I. m， The drain of the second current source in the current source group is used to ground through the load.

[0009] In a preferred embodiment, it further includes one or more stacked isolation layers, each isolation layer including N isolation devices, and the N isolation devices are respectively electrically connected to the N current source groups.

[0010] In a preferred embodiment, the first current source and the second current source are PMOS, NMOS, NPN, or PNP devices.

[0011] In a preferred embodiment, the N isolation devices in each isolation layer are of the same type as the first current source and the second current source.

[0012] In a preferred embodiment, each isolation device includes a first isolation element and a second isolation element, both of which are PMOS transistors; the gate of the first isolation element in each isolation device is connected to a third bias voltage, and the source of the first isolation element is connected to the drain of a corresponding first current source; the gate of the second isolation element in each isolation device is connected to a third bias voltage, and the source of the second isolation element is connected to the drain of a corresponding second current source; the current output from the drain of one isolation element in each isolation device is used to correct the corrected current I. m， The drain of the other isolator is grounded through the load.

[0013] In a preferred embodiment, the size ratio of the first isolator and the second isolator in each isolator is the same as the size ratio of the first current source and the second current source, wherein the size ratio is the ratio of the width of the device to the length of the device.

[0014] This application also provides a current-steering DAC, which includes a driving circuit connected to an input digital signal, a plurality of control switch groups controlled by the driving circuit, a plurality of current source weighting circuits connected between a power supply and the plurality of control switch groups, and a current correction circuit for correcting the corrected current output by the current source weighting circuits, wherein the other end of the plurality of control switch groups is used for electrical connection to a load, and the current correction circuit is any of the current correction circuits described above.

[0015] In a preferred embodiment, the current source weighting circuit includes: a resistor R0 and a current source M0 to be corrected. One end of the resistor R0 is connected to a power supply or ground, and the other end of the resistor R0 is connected to the source / emitter of the current source M0 to be corrected. The drain / collector of the current source M0 to be corrected is connected to the drain / collector of the current source that outputs the correction current in the current source group. The first bias voltage is connected to the control terminal of the current source to be corrected.

[0016] This application also provides an electronic device that includes any of the above-described current correction circuits.

[0017] The current correction circuit provided in this application combines a resistor, several current source groups, and switch groups connected one-to-one with each current source group. The control terminals of both current source groups are electrically connected to the connection terminals of switches in the switch groups, allowing the switch groups to control the direction of the current flowing from the current source groups. In this invention, the switch group control causes the first and second current sources in the current source groups to be switched on and off, resulting in one current source in the current source group outputting a correction current to increase or decrease the current being corrected. By controlling the on / off state of the switches in each switch group and setting the proportional relationship between the components in the current source groups, the direction and magnitude of the current output by the current correction circuit can be adjusted through the current source groups, switch groups, and resistor R1, thereby increasing or decreasing the current being corrected to the desired current value. Furthermore, this current correction circuit improves current accuracy, achieves low mismatch and low temperature drift, has fewer electronic components, a very simple circuit structure, good stability, and low cost. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the existing DAC circuit structure; Figure 2 This is a circuit diagram of a current correction circuit according to an embodiment of the present invention. Figure 3 This is a schematic diagram of a current correction circuit based on a PMOS current source electrically connected to the circuit where the current to be corrected is located, according to one embodiment of the present invention. Figure 4 This is a schematic diagram of a current correction circuit based on an NMOS current source electrically connected to the circuit where the current to be corrected is located, according to one embodiment of the present invention. Figure 5 This is a schematic diagram of a current correction circuit containing an isolation device electrically connected to the circuit containing the current being corrected in one embodiment of this utility model. Figure 6 This is a circuit diagram of a DAC in one embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this utility model clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be adopted to implement this utility model. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of this utility model disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of this utility model.

[0021] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0022] To illustrate the technical solutions described in this utility model, the technical solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0023] To fully understand this utility model, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this utility model. Preferred embodiments of this utility model are described in detail below; however, in addition to these detailed descriptions, this utility model may have other embodiments.

[0024] The current correction circuit provided by this invention can be used to correct the current being corrected, thereby obtaining the desired current. For example, the current being corrected can be increased or decreased to obtain the desired accuracy and precision. Moreover, this current correction circuit can achieve low mismatch and low temperature drift, and its circuit structure is simple, stable, and low in cost.

[0025] The current correction circuit provided by this utility model includes: a resistor R1, N current source groups, and N switch groups corresponding one-to-one with the N current source groups. The switch groups can control the direction of the current flowing from the current source groups. The number N of current source groups can be designed according to the preset / required current range and accuracy. For example, the current to be corrected is I... m The value of N can be set according to the desired current, thereby setting the number of current source groups and switch groups. Therefore, after the current output by the current correction circuit corrects the current being corrected, the desired current can be obtained. For example, by adjusting the current I in the current source weighting unit of the current steering DAC... m By performing corrections, the desired current weight can be obtained, which in turn can reduce the mismatch of the DAC.

[0026] Each of the switch groups includes a first switch group and a second switch group, and each switch group includes two switches connected in series. When one switch in the first switch group of the i-th switch group is closed, the other switch in the first switch group is open; when one switch in the second switch group of the i-th switch group is closed, the other switch in the second switch group is open. Each current source group includes a first current source Msci and a second current source Msi, where 1 ≤ i ≤ N. One end of the resistor R1 is connected to a power supply or ground, and the source / emitter of the two current sources in each current source group is electrically connected to the other end of the resistor R1. The two ends of the first switch group in the two series-connected i-th switch groups are electrically connected to a first bias voltage and a second bias voltage, respectively. The connection terminals of the two switches in the first switch group of the i-th switch group are electrically connected to the control terminal of the first current source in the i-th current source group. The two ends of the second switch group in the i-th switch group are electrically connected to the first bias voltage and the second bias voltage, respectively. The connection terminals of the two switches in the second switch group of the i-th switch group are electrically connected to the control terminal of the second current source in the i-th current source group. The switching group is used to stagger the on / off states of the first current source and the second current source in the current source group connected thereto, and to cause the drain / collector of the first current source Msci or the drain / collector of the second current source Msi in the current source group to output a correction current for correcting the current I being corrected. mAs can be seen from the above, the two current sources in each current source group can form a differential structure, and the first switch group and the second switch group can also form a differential structure. Moreover, the control terminals of the two current source groups are electrically connected to the connection terminals of the two switches in the switch group, which allows the switch group to control the direction of the current flowing out of the current source group.

[0027] In this invention, by controlling the on / off state of the switches in each switch group, the conduction and disconnection of the first and second current sources in the current source group can be staggered, thereby allowing the current output from either the first or second current source to be used to correct the current being corrected. Furthermore, by controlling the on / off state of the switches in each switch group, setting the proportional relationship between the components in the current source group, and adjusting the resistor R1, the direction and magnitude of the current output by the current correction circuit can be adjusted, thereby increasing or decreasing the current being corrected to the desired current value. Moreover, by combining the above circuit structure and the corresponding component parameter settings, the current correction circuit can output the desired current range and accuracy, thus allowing the current being corrected to be adjusted to the required range and accuracy, and achieving low mismatch and low temperature drift. Both the first and second switch groups include two switches, allowing one switch to be on while the other is off. This switch group has a simple structure, low cost, and its on / off state is easily controlled, making the current-controlled DAC adaptable to a wider range of applications.

[0028] It is worth noting that the correction circuit provided by this invention has fewer electronic components, a very simple circuit structure, good stability, and low cost. These are all very important for the circuit.

[0029] The first and second current sources in the current source group provided by this utility model are preferably PMOS, NMOS, NPN, or PNP devices, which have simple structure, low cost, and enable high accuracy of the corrected current.

[0030] Figure 2 This is a circuit diagram of a current correction circuit provided in one embodiment of the present invention. In each current source group, the two current sources Msci and Msi are both PMOS current sources. One end of resistor R1 is connected to the power supply, and the sources of the two current sources in each current source group are electrically connected to the other end of resistor R1. Figure 2Each of the aforementioned switch groups includes: a first switch group and a second switch group forming a differential structure with the first switch group. Each switch group includes two switches connected in series. The two ends of the first switch group in the i-th switch group are electrically connected to a first bias voltage Vb1 and a second bias voltage Vb2, respectively. The connection terminals of the two switches in the first switch group in the i-th switch group are electrically connected to the control terminal of the first current source Msci of the i-th current source group. The two ends of the second switch group in the i-th switch group are electrically connected to the first bias voltage Vb1 and the second bias voltage Vb2, respectively. The connection terminals of the two switches in the second switch group in the i-th switch group are electrically connected to the control terminal of the second current source Msi of the i-th current source group. When one switch in the first switch group in the i-th switch group is closed, the other switch in the first switch group is open; when one switch in the second switch group in the i-th switch group is closed, the other switch in the second switch group is open. The current output from the drain of the first current source in each current source group is the aforementioned correction current, and this correction current is used to correct the current I being corrected. m。 The drain of the second current source in the current source group is used to ground through the load.

[0031] Depend on Figure 2 It can be seen that resistor R1 forms the source negative feedback resistor, and the current from the power supply to the branch containing resistor R1 is Is. The drain current output from the first current source Msci is Ic, and the drain current output from the second current source Msi is Is-Ic. The drain current Ic of the first current source Msci can be used to correct the current being corrected, I. m The current correction circuit provided in this embodiment has a simple structure, low cost, low mismatch, good circuit stability, and high current accuracy.

[0032] See Figure 3 As shown, Figure 3 A current correction circuit and a corrected current I are provided in an embodiment of this utility model. m A schematic diagram of the electrical connections of the circuit. The current being corrected, I... m The circuit in question is a current source weighting circuit, which includes a resistor R0 and a current source M0. One end of the resistor R0 is connected to a power supply, and the other end is electrically connected to the source of the PMOS-type current source M0. The drain of the current source M0 is connected to the drain of the first current source, so that the current being corrected is corrected by the current output from the first current source. The control terminal of the current source M0 is also connected to the first bias voltage Vb1. The current I flowing from the resistor R0 to the current source M0 is... m This refers to the current being corrected as described above. Figure 3 The drain current Ic of the medium current source Msci flows to the current source M0 to correct the current I.m During calibration, the drain current of current source Mci flows to ground through the load. This allows the gates of the current sources in the current source group and the gate of the current source being calibrated M0 to share a common bias voltage, and the drains of the current sources in the current source group and the drain of the current source being calibrated to share a common voltage node. This improves the consistency of the devices and circuits, thereby increasing the accuracy of current calibration. Furthermore, it improves the mismatch and temperature drift of the current-controlled DAC to which the current calibration circuit is applied.

[0033] The following is combined Figure 3 The working principle and process of this utility model are described in the following embodiments: Taking a PMOS current source as an example, resistor R0 and current source M0 constitute the corrected current source weighting circuit, which generates the corrected current Im. The first input terminal of resistor R0 is connected to the power supply, and the second input terminal of resistor R0 and the source terminal of current source M0 are connected to node Vs1. The gate of each current source device in the current source group is connected to bias voltages Vb1 and Vb2 respectively via differential control switches. The drains of two current source devices are connected to two common nodes Vo1 and Vo2 respectively. The corrected current source weighting circuit and the current correction circuit have the same gate bias voltage Vb1 and common drain outputs Vo1 and Vo2 as matching terminals, outputting current to ground. By setting the proportional relationship between R1 and R0, and... Figure 3 By determining the proportional relationship between the dimensions of components Ms1, Msc1, Ms2, Msc2, ..., Msn, Mscn, and M0, the relationship between the current Is and the current Im being calibrated can be obtained. The proportional relationship is the ratio of the width to the length of the component (i.e., W / L). For example, if R1 = R0, and the W / L value of Ms1 = the W / L value of Msc1, the W / L value of Ms2 = the W / L value of Msc2, ..., the W / L value of Msn = the W / L value of Mscn, then the proportional relationship of the current Is = Im in the branch containing resistor R1 can be obtained. Other proportional relationships can be obtained through similar design. For example, if a current source for thermometer coding is required, then R1 = R0, and the W / L value of Ms1 = the W / L value of Ms2 = ... = the W / L value of Msn = 1 / N. The W / L value of M0; for example, if a binary encoded current source is required, then the W / L value of Ms1 should be designed to be 2. The W / L value of MS1, the W / L value of Ms3 = 2 The W / L value of MS2. Specific current relationships include, but are not limited to, thermometer encoding, binary encoding, and other mixed encoding methods.

[0034] The ratio of the width to the length of each component will be referred to as Z, for example, ZM. siFor current source device M si The aforementioned ratio Z. From Figure 3 It can be seen that resistor R1 forms a negative feedback resistor, and any two current source devices M si and M sj (Assuming ZM) si =ZM sj The mismatch value of the output current is shown in formula (1). (1) Where I is the current source device M si Or M sj The ideal current is given by β, where ΔI is the deviation between the actual current and the ideal current; β = μC. ox W / L, μ is the mobility, C ox The gate oxide thickness of the aforementioned device is given by W, its width by L, its length by Δβ, and its deviation from the ideal value by Vth; Vth is its threshold voltage, and g is the gate oxide thickness. m For its transconductance, R is Figure 3 The resistance value of resistor R1 is considered, and its mobility and threshold voltage exhibit significant temperature drift. Typically, g m Since R>>1, it can be seen from the above formula (1) that the value of current mismatch will be attenuated by the previous coefficient 1 / (1+gmR) factor. m The value of R is usually much greater than 1, so the current mismatch value on the left side of the above formula is usually much less than 1, resulting in very low current mismatch. Therefore, the current mismatch of the current correction circuit provided by this invention is even lower.

[0035] In contrast to the case without negative feedback resistor, i.e. R=0, equation (1) becomes equation (2). (2) Comparing equations (1) and (2), it is evident that the coefficient 1 / (1+gmR) is typically much smaller than 1, corresponding to a current mismatch in the current correction circuit provided by this invention that is significantly lower than the current mismatch in the case of no resistance described above. Therefore, it can be seen from the above that the current correction circuit provided by this invention has the advantage of low mismatch, and in the case of low mismatch, it also has the advantage of low temperature drift. In this embodiment, a resistor R is introduced into the current source, and a switching group is used to control the current flow direction of the two current source devices in the current source group. For example, in a switch group, the switch connected to Vb1 in the first switch group is closed, and the other switch connected to Vb2 is open; in the switch group, the switch connected to Vb2 in the second switch group is open, and the switch connected to Vb1 in the second switch group is on. This causes the first current source in the current source group to be on and the second current source to be off, resulting in the current output from the drain of the first current source flowing to Vo1, and then to the corrected current source weight connected to the drain of the first current source, to correct the corrected current in the corrected current source weight. Conversely, if the second current source device in the current source group is on and the first current source device is off, the current output from the second current source device flows to Vo2. By designing the above-mentioned proportional relationship between the dimensions of the current source devices in the current source group, the output current I can be achieved. c With total current I S The proportional relationship, thus the output current I c After correcting the current to be corrected, the required current can be obtained, and the mismatch of the current correction circuit is very low. Furthermore, the gate input of the current source group and the gate of the current source to be corrected can share a common bias voltage, and the drain output of the current source group and the drain of the current source to be corrected can share a common voltage node. This method ensures that the current correction circuit and the current source to be corrected have the same bias voltage and proportionally sized devices, thus uniformly adapting to changes in process corner power supply and temperature. This results in a lower mismatch and a lower temperature drift due to the mismatch in the current correction circuit provided by this invention, eliminating the need for correction at different temperatures.

[0036] In a preferred embodiment, the ratio Z of the size of the first current source, the ratio Z of the size of the second current source, and the ratio Z of the size of the current source being corrected can be set to the same value. This results in better consistency, lower mismatch, and higher accuracy of the output current in the current correction circuit.

[0037] See Figure 4The embodiment of this utility model shown is wherein the current source group in the current correction circuit provided by this utility model is an NMOS type device. The current sources in the current source weighting circuit of the current source being corrected, which is electrically connected to the current correction circuit, are all NMOS type devices of the same type as the current source group. One end of resistor R1 is grounded, and the other end is electrically connected to the source terminals of two current sources in each current source group. The drain of the first current source Msci in each current source group is the output terminal of the first voltage VO1 in the figure, and the drain of the second current source in each current source group is the output terminal of the second voltage VO2 in the figure. The current output from the drain of the first current source Msci or the drain of the second current source is used to compensate / correct the current I being corrected. m In the current source weighting circuit, one end of resistor R0 is grounded, and the other end of resistor R0 is connected to the source of the current source M0 being calibrated. The first voltage is connected to the drain of the current source M0 being calibrated, and the first bias voltage is connected to the gate of the current source being calibrated. This design is suitable for current calibration needs in different scenarios and for different electronic products.

[0038] In a preferred embodiment of this invention, the current correction circuit further includes one or more stacked isolation layers. Each isolation layer includes N isolation devices, each of which is connected to one of the N current source groups. One, two, or more isolation layers can be provided as needed. The current source group can be a single layer, and correspondingly, one or more isolation layers are stacked together with the layered current source group, with one isolation device in each isolation layer electrically connected to one current source group. The isolation layer provides isolation, improving the voltage consistency between the source and drain of the current sources in the current source group, resulting in better mismatch performance of the current correction circuit and making it more suitable for high power supply voltages. Preferably, the type of the N isolation devices in each isolation layer is the same as that of the first and second current sources, ensuring that the isolation devices have the same structure as the devices in the current source group, resulting in better isolation, better matching of the output current accuracy of the N current source groups, and better mismatch performance (i.e., lower mismatch).

[0039] See Figure 5 In the preferred embodiment shown, the current correction circuit includes an isolation layer comprising N isolation devices. Each isolation device includes a first isolation element and a second isolation element, both of which are PMOS transistors of the same type as the first and second current sources in the current source group. Correspondingly, the current source weighting circuit being corrected is compared to... Figure 3The illustrated embodiment further includes another current source M1 electrically connected to the current source M0 being calibrated. The gate of current source M1 is connected to a third bias voltage, the source of current source M1 is connected to the drain of current source M0, and the drain of current source M1 is electrically connected to the first and second isolators. The gate of the first isolator in each isolation device is connected to the third bias voltage, and the source of the first isolator is connected to the drain of the corresponding first current source. The drain of the first isolator is the output terminal of the first voltage VO1 in the figure, and the drain of the second isolator is the output terminal of the second voltage VO2 in the figure. The current output from the drain of the first isolator is used to compensate / calibrate the current I being calibrated. m In each isolation device, the gate of the second isolator is connected to a third bias voltage, the source of the second isolator is connected to the drain of the corresponding second current source, and the drain of the second isolator is grounded through the load. That is, Figure 5 In the embodiment, in the current source weighting circuit, resistor R0 is electrically connected to the isolation device through two current sources being calibrated. Specifically, resistor R0 is electrically connected to the drain of each first isolator through two current sources being calibrated, and the gate of the current source being calibrated and connected to the first isolator is simultaneously electrically connected to the third bias voltage. This ensures that the NMOS transistor in the isolation layer shares a common gate voltage with the current source being calibrated in the current source weighting circuit. This approach guarantees isolation while offering advantages such as lower mismatch, higher accuracy of the output calibration current, simple structure, small size, and low cost. Further preferably, the size ratio of the first and second isolators in each isolation device is the same as the size ratio of the first and second current sources. This size ratio is Z, which is the ratio of the width to the length of the device. This allows for uniform adaptation to changes in process corner power supply and temperature, resulting in lower mismatch and lower temperature drift due to mismatch, eliminating the need for calibration at different temperatures.

[0040] The current correction circuit provided by this utility model can be used in various scenarios that require current correction or adjustment, such as current steering DAC.

[0041] This utility model also provides a current-driven DAC, see [link / reference] Figure 6As shown, the current-steering DAC includes: a driving circuit, several control switch groups, a current source weighting circuit, and any one of the aforementioned current correction circuits used to correct the current output by the current source weighting circuit. The driving circuit is connected to the digital signal input to the DAC and can drive the aforementioned several control switch groups. The current source weighting circuit is electrically connected between the power supply and the several control switch groups. The other end of the several control switch groups is used to electrically connect to the load. The several control switch groups can be used to control whether the current of the current source weighting circuit is output to the load. A current source weighting circuit that needs to be corrected is electrically connected to one of the current correction circuits, that is, a current correction circuit is connected in parallel with the current weighting circuit that needs to be corrected. By adjusting the current correction circuit, the corresponding current source weighting circuit can output the desired current value, thereby enabling the current-steering DAC to perform the summation of the current source weights according to the input digital signal to obtain a more accurate analog signal, thus improving the accuracy of the current-steering DAC. Moreover, this gives the current-steering DAC the advantages of low mismatch and low temperature drift. If the current of N current source weighting circuits needs to be corrected, a current correction circuit can be connected in parallel with each of the N current source weighting circuits.

[0042] Furthermore, with the development of advanced semiconductor manufacturing processes, especially in the currently popular deep submicron processes (such as the current 7nm and 3nm advanced process technologies), the channel modulation effect of devices is more severe, and the mismatch problem of existing current-controlled DACs is more serious, with poorer temperature drift due to mismatch, which reduces the overall performance of current-controlled DACs. However, the current-controlled DAC provided by this invention can reduce or even avoid the problems caused by the aforementioned channel modulation effect. The current-controlled DAC provided by this invention has lower mismatch, and its structure is very simple, with lower cost and better stability, making it suitable for more application scenarios.

[0043] The structure of the current source weighting circuit in the current-rudder DAC provided by this utility model can be... Figure 3 , Figure 4 and Figure 5 The structure of the corrected current source weighting circuit shown can be found in the above embodiments, and will not be repeated here. It can make the structure of the current steering DAC simpler, lower in cost, lower in mismatch, and higher in accuracy.

[0044] Furthermore, this application also provides an electronic device that includes any of the aforementioned current correction circuits. The electronic device can be a chip / module containing the aforementioned DAC, or a voltage-controlled oscillator, data acquisition system, digital television equipment, medical equipment, measuring equipment, automotive electronic device, etc., that includes the aforementioned DAC.

[0045] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0046] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0047] In this application, the word "for example" is used to mean "used as an example, illustration, or explanation." Any embodiment described as "for example" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to make and use it. Various details are set forth in the above description for purposes of explanation.

[0048] It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A current correction circuit, characterized by, The current correction circuit comprises: a resistor R1; N current source groups; and N switch groups corresponding to the N current source groups, the switch groups being configured to stagger the on-off of the first current source and the second current source in the current source group connected to the switch group, and to output a correction current from the anode / cathode of one current source in the current source group, for correcting the corrected current I m ; Each of the current source groups comprises a first current source Msci and a second current source Msi, 1≤i≤N, the sources / emitters of the two current sources in each of the current source groups are electrically connected to the other end of the resistor R1, and one end of the resistor R1 is connected to a power supply or ground; Each of the switch groups comprises a first switch group and a second switch group, and each of the first switch group and the second switch group comprises two switches connected in series, when one of the two switches in the first switch group in the ith switch group is closed, the other switch in the first switch group is opened, and when one of the two switches in the second switch group in the ith switch group is closed, the other switch in the second switch group is opened; The two ends of the first switch group in the ith switch group are electrically connected to a first bias voltage and a second bias voltage respectively, the connection end of the two switches in the first switch group in the ith switch group is electrically connected to the control end of the first current source in the ith current source group, the two ends of the second switch group in the ith switch group are electrically connected to the first bias voltage and the second bias voltage respectively, and the connection end of the two switches in the second switch group in the ith switch group is electrically connected to the control end of the second current source in the ith current source group.

2. The current correction circuit according to claim 1, characterized in that, The first current source and the second current source are PMOS current sources, one end of the resistor R1 is connected to a power supply, and the sources of the two current sources in each of the current source groups are electrically connected to the other ends of the resistor R1; The two ends of the first switch group in the ith switch group are electrically connected to the first bias voltage and the second voltage respectively, the connection end of the two switches in the first switch group in the ith switch is electrically connected to the gate of the first current source in the ith current source group, the two ends of the second switch in the ith switch group are electrically connected to the first bias voltage and the second bias voltage, and the connection end of the two switches in the second switch group in the ith switch group are electrically connected to the gate of the second current source in the ith current source group. The current outputted from the drain of the first current source in each current source group is used to correct the current I to be corrected m， The drain of the second current source in the current source group is used to be grounded through a load.

3. The current correction circuit of claim 1, wherein, It also comprises one or several layers of isolation layers arranged in a stack, each of the isolation layers comprises N isolation devices, and the N isolation devices are electrically connected to the N current source groups respectively.

4. The current correction circuit according to claim 3, characterized in that, The first current source and the second current source are PMOS or NMOS or NPN or PNP devices.

5. The current correction circuit according to claim 4, characterized in that, The types of the N isolation devices in each of the isolation layers are the same as the types of the first current source and the second current source.

6. The current correction circuit according to claim 5, characterized in that, Each of the isolation devices comprises a first isolation device and a second isolation device, and the first isolation device and the second isolation device are PMOS tubes; The gate of the first isolation device in each of the isolation devices is connected to a third bias voltage, and the source of the first isolation device is connected to the drain of the corresponding first current source. The gate of the second isolation element in each isolation device is connected to a third bias voltage, the source of the second isolation element is connected to the drain of a corresponding second current source, and the drain output current of one isolation element in each isolation device is used to correct the current I to be corrected m， The drain of the other isolation element is connected to the load ground.

7. The current correction circuit according to any one of claims 2 to 6, characterized in that, The size ratio of the first isolation device and the second isolation device in each of the isolation devices is the same as the size ratio of the first current source and the size ratio of the second current source, and the size ratio is the ratio of the width of the device to the length of the device.

8. A current steering DAC, characterized by, It comprises: A driving circuit connected with an input digital signal, a plurality of control switch groups controlled by the driving circuit, a plurality of current source weight circuits connected between a power supply and the plurality of control switch groups, and a current correction circuit for correcting the corrected current output by the current source weight circuit, the other end of the plurality of control switch groups being used for electrical connection with a load, the current correction circuit being the current correction circuit of any one of claims 1 to 7.

9. The current steering DAC of claim 8, wherein, The current source weight circuit comprises a resistor R0 and a corrected current source M0, one end of the resistor R0 being connected to a power supply or ground, the other end of the resistor R0 being connected to the source / emitter of the corrected current source M0, the drain / collector of the corrected current source M0 being connected to the drain / collector of the current source outputting the corrected current in the current source group, and the first bias voltage being connected to the control end of the corrected current source.

10. An electronic device, comprising: The current correction circuit comprises: The current correction circuit of any one of claims 1 to 7.

Images