A power transistor

Abstract

The utility model relates to a kind of power transistor.The utility model includes first conductive type substrate;Back metal layer, setting in the back of first conductive type substrate;Second conductive type base area, forms in the front of part first conductive type substrate;First conductive type emission area, forms in the front of part second conductive type base area;First conductive type resistance ring, forms in the front of part first conductive type substrate;Insulating dielectric layer, covers the front of first conductive type substrate;Surface protection barrier layer, covers the front of insulating dielectric layer;Passivation layer, covers the front of surface protection barrier layer;Base area metal layer, setting in the front of passivation layer, and first opening and the front of second conductive type base area contact;Emission area metal layer, setting in the front of passivation layer and mutually isolated with base area metal layer, emission area metal layer is contacted in the front of first conductive type emission area by second opening.Effective improvement device overall performance can be carried out.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor transistor technology, and in particular to a power transistor. Background Technology

[0002] High-frequency, low-saturation-dropout NPN power transistors have a wide range of applications, with a very promising market prospect in automotive electronics, industrial equipment, relay drivers, high-speed inverters, converters, and other general high-current switching applications. These applications require characteristics such as low leakage current, low saturation voltage drop, high frequency, fast switching speed, good amplification consistency, and high reliability.

[0003] For a long time, the market for this type of power semiconductor product has been dominated by manufacturers from Europe, the United States, and Japan. Local users often have to rely on imported original components, which are expensive and have unstable supply channels. Therefore, manufacturers in the automotive electronics and industrial equipment sectors are eager for domestic power semiconductor companies to accelerate the research and development of high-end power devices to meet their actual needs. Consequently, the developed power transistors must simultaneously possess key characteristics such as low saturation voltage drop, high frequency, and fast switching.

[0004] For bipolar junction transistors (BJTs), minimizing power loss during switching requires increasing the switching speed of the transistor, shortening the switching time (ton, conduction time), storage time (ts, storage time), and fall time (tf, fall time) as much as possible. Simultaneously, the saturation voltage drop (Vce(sat)) of the power transistor must also be kept at a low level to better meet customer and market requirements, thereby enhancing product competitiveness and the overall technological level of the industry. Summary of the Invention

[0005] Therefore, this utility model provides a power transistor that has the advantages of low saturation voltage, high operating frequency, fast switching speed, high reliability, and good amplification consistency, which can effectively improve the overall performance of the device.

[0006] To solve the above-mentioned technical problems, this utility model provides a power transistor, comprising: First conductivity type substrate; A back metal layer is disposed on the back side of the first conductivity type substrate; A second conductivity type base region is formed on the front side of a portion of the first conductivity type substrate; A first conductivity type emitter region is formed in the center of the front side of a portion of the second conductivity type base region; A first conductivity type resistance ring is formed on the outer side of the front side of a portion of the first conductivity type substrate; An insulating dielectric layer covers the front side of the first conductivity type substrate; A surface protective barrier layer covers the front side of the insulating dielectric layer; A passivation layer covers the front side of the surface protective barrier layer; a first opening and a second opening are respectively provided along the passivation layer, penetrating the surface protective barrier layer and the insulating dielectric layer in sequence; A base metal layer is disposed on the front side of the passivation layer, and the first opening is in contact with the front side of the base region of the second conductivity type; An emitter metal layer is disposed on the front side of the passivation layer and isolated from the base metal layer. The emitter metal layer is in contact with the front side of the first conductivity type emitter region through the second opening. Wherein, when the first conductivity type is N-type, the second conductivity type is P-type, and when the first conductivity type is P-type, the second conductivity type is N-type.

[0007] In one embodiment of this invention, the junction depth and doping concentration of the first conductivity type emitter region and the first conductivity type resistive ring are the same.

[0008] In one embodiment of the present invention, the first conductive substrate includes a first substrate sublayer in contact with the back metal layer and a second substrate sublayer located above the first substrate sublayer.

[0009] In one embodiment of this invention, the doping concentration along the second substrate sublayer to the first substrate sublayer exhibits an abrupt distribution.

[0010] In one embodiment of this invention, the PN junction between the second conductivity type base region and the second substrate sublayer is a shallow junction deep PN junction.

[0011] In one embodiment of this utility model, the material of the insulating dielectric layer includes silicon dioxide.

[0012] In one embodiment of this utility model, the material of the surface protective barrier layer includes phosphosilicate glass.

[0013] In one embodiment of this invention, the passivation layer is made of silicon nitride.

[0014] In one embodiment of this utility model, the materials of both the base region metal layer and the emitter region metal layer include aluminum.

[0015] In one embodiment of the present invention, the back metal layer includes a titanium layer, a nickel layer and a silver layer sequentially distributed along a direction away from the first conductivity type substrate.

[0016] The above-mentioned technical solution of this utility model has the following advantages compared with the prior art: The power transistor described in this utility model has the advantages of low saturation voltage, high operating frequency, fast switching speed, high reliability, and good amplification consistency, which can effectively improve the overall performance of the device. Attached Figure Description

[0017] To make the content of this utility model easier to understand, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the power transistor according to an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the equivalent structure of the power transistor according to an embodiment of the present invention.

[0020] Explanation of reference numerals in the instruction manual: 1. N-type second substrate sublayer; 2. P+ type base region; 3. N+ type emitter region; 4. Insulating dielectric layer; 5. Base region metal layer; 6. Emitter region metal layer; 7. N+ type resistance ring; 8. Surface protective barrier layer; 9. Passivation layer; 10. N+ type first substrate sublayer; 11. Backside metal layer. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments are not intended to limit the present invention.

[0022] In this utility model, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this utility model, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model.

[0023] In this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc. are understood to exclude the stated number; "above," "below," "within," etc. are understood to include the stated number. In the description of this utility model, if "first" or "second" is used, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the order of the indicated technical features.

[0024] In this utility model, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to a fixed connection, a detachable connection, or an integrally formed connection; they can refer to a mechanical connection, an electrical connection, or a connection capable of mutual communication; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in conjunction with the specific content of the technical solution.

[0025] Reference Figure 1 As shown, a power transistor of this utility model includes: First conductivity type substrate; A back metal layer 11 is disposed on the back side of the first conductivity type substrate to form the collector C of the transistor. A second conductivity type base region is formed on the front side of a portion of the first conductivity type substrate; A first conductivity type emitter region is formed in the center of the front side of a portion of the second conductivity type base region; A first conductivity type resistance ring is formed on the outer side of the front side of a portion of the first conductivity type substrate; An insulating dielectric layer 4 covers the front side of the first conductive type substrate; A surface protective barrier layer 8 covers the front side of the insulating dielectric layer 4; A passivation layer 9 covers the front side of the surface protective barrier layer 8; a first opening and a second opening are respectively provided along the passivation layer 9, which penetrate the surface protective barrier layer and the insulating dielectric layer 4 in sequence; A base metal layer 5 is disposed on the front side of the passivation layer 9, and the first opening is in contact with the front side of the second conductivity type base region to form the base B of the transistor. The emitter metal layer 6 is disposed on the front side of the passivation layer 9 and is isolated from the base metal layer 5. The emitter metal layer 6 contacts the front side of the first conductivity type emitter region through the second opening to form the emitter E of the transistor.

[0026] Wherein, when the first conductivity type is N-type, the second conductivity type is P-type, and when the first conductivity type is P-type, the second conductivity type is N-type.

[0027] In this embodiment, an NPN transistor is used as an example, i.e., the first conductivity type is N-type and the second conductivity type is P-type, as shown in the reference. Figure 2 As shown, its terminals are collector C, base B, and emitter E. It should be noted that in other embodiments, interchanging the P-type and N-type doping types of the above layers constitutes a PNP transistor.

[0028] Specifically, the NPN transistor includes: N-type substrate; A back metal layer 11 is disposed on the back side of the N-type substrate to form the collector C of the transistor; P+ type base region 2 is formed on the front side of a portion of the N type substrate; The N+ type emitter region 3 is formed in the center of the front side of part of the P+ type base region 2; An N+ type resistance ring 7 is formed on the outer side of the front side of a portion of the N-type substrate; An insulating dielectric layer 4 covers the front side of the N-type substrate; A surface protective barrier layer 8 covers the front side of the insulating dielectric layer 4; A passivation layer 9 covers the front side of the surface protective barrier layer 8; a first opening and a second opening are respectively provided along the passivation layer 9, which penetrate the surface protective barrier layer 8 and the insulating dielectric layer 4 in sequence; A base metal layer 5 is disposed on the front side of the passivation layer 9, and the first opening is in contact with the front side of the P+ type base region 2 to form the base B of the transistor. The emitter metal layer 6 is disposed on the front side of the passivation layer 9 and is isolated from the base metal layer 5. The emitter metal layer 6 contacts the front side of the N+ type emitter region 3 through the second opening to form the emitter E of the transistor. Specifically, the junction depth and doping concentration of the N+ type emitter region 3 and the N+ type resistivity ring 7 are the same.

[0029] Specifically, the N-type substrate includes an N+ type first substrate sublayer 10 in contact with the back metal layer 11 and an N- type second substrate sublayer 1 located above the N+ type first substrate sublayer 10.

[0030] Specifically, the doping concentration along the N-type second substrate sublayer 1 to the N+ type first substrate sublayer 10 exhibits an abrupt distribution.

[0031] Specifically, the PN junction between the P+ type base region 2 and the N- type second substrate sublayer 1 is a shallow-deep PN junction. A shallow-base-deep junction process is used to improve the characteristic frequency.

[0032] Specifically, the insulating dielectric layer 4 is made of silicon dioxide (SiO2); the surface protective barrier layer 8 is made of phosphosilicate glass (PSG); and the passivation layer 9 is made of silicon nitride (Si3N4).

[0033] It should be noted that although SiO2 is very stable mechanically, chemically, and electrically, and has excellent passivation properties, its ability to mask alkali metal ions such as Na+ and K+ is poor, resulting in relatively high leakage current in typical mesa products. By adding a process, the chip is placed in a diffusion furnace filled with nitrogen gas doped with phosphorus. Phosphorus reacts with the silicon surface to form a phosphosilicate glass, which serves as the surface protective barrier layer 8 above the insulating dielectric layer 4. The phosphosilicate glass extracts, fixes, and blocks sodium ions, significantly reducing the influence of mobile ions like sodium on the semiconductor surface properties and decreasing leakage current. Furthermore, the passivation layer 9 formed above the surface protective barrier layer 8 uses silicon nitride, which reduces peak breakdown and further decreases the product's leakage current.

[0034] Specifically, the base region metal layer 5 and the emitter region metal layer 6 are made of aluminum.

[0035] Specifically, the back metal layer 11 includes a titanium layer, a nickel layer, and a silver layer distributed sequentially along the direction away from the N-type substrate.

[0036] The back metal layer 11 uses three metal layers of titanium, nickel, and silver to form the collector of the transistor. Traditionally, nickel is used as the back metal, but it has poor contact with silicon and is prone to oxidation in air, leading to poor die bonding. To solve the contact problem with the silicon wafer, titanium, which has good contact with both silicon and nickel, is used as a transition metal in the first layer. However, titanium has a high resistance and cannot be too thick. To protect the nickel from oxidation, the outermost third layer is protected with silver. Since silver can quickly melt into the solder during lead-tin soldering, it protects the nickel from oxidation without affecting the lead-tin soldering. This improves the chip's wettability, reduces die bonding voids, increases die bonding strength, and improves the device's power handling capacity and thermal fatigue performance, greatly increasing product reliability.

[0037] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solution of this utility model and not to limit it. Although this utility model has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solution of this utility model without departing from the spirit and scope of the technical solution of this utility model, and all such modifications and substitutions should be covered within the scope of the claims of this utility model.

Claims

1. A power transistor, characterized in that, include: First conductivity type substrate; A back metal layer is disposed on the back side of the first conductivity type substrate; A second conductivity type base region is formed on the front side of a portion of the first conductivity type substrate; A first conductivity type emitter region is formed in the center of the front side of a portion of the second conductivity type base region; A first conductivity type resistance ring is formed on the outer side of the front side of a portion of the first conductivity type substrate; An insulating dielectric layer covers the front side of the first conductivity type substrate; A surface protective barrier layer covers the front side of the insulating dielectric layer; A passivation layer covers the front side of the surface protective barrier layer; a first opening and a second opening are respectively provided along the passivation layer, penetrating the surface protective barrier layer and the insulating dielectric layer in sequence; A base metal layer is disposed on the front side of the passivation layer, and the first opening is in contact with the front side of the base region of the second conductivity type; An emitter metal layer is disposed on the front side of the passivation layer and isolated from the base metal layer. The emitter metal layer is in contact with the front side of the first conductivity type emitter region through the second opening. Wherein, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

2. A power transistor according to claim 1, characterized in that, The junction depth and doping concentration of the first conductivity type emitter region and the first conductivity type resistive ring are the same.

3. A power transistor according to claim 1, characterized in that, The first conductive type substrate includes a first substrate sublayer in contact with the back metal layer and a second substrate sublayer located above the first substrate sublayer.

4. A power transistor according to claim 3, characterized in that, The doping concentration along the second substrate sublayer to the first substrate sublayer exhibits an abrupt distribution.

5. A power transistor according to claim 3, characterized in that, The PN junction between the base region of the second conductivity type and the sublayer of the second substrate is a shallow junction or a deep PN junction.

6. A power transistor according to claim 1, characterized in that, The material of the insulating dielectric layer includes silicon dioxide.

7. A power transistor according to claim 1, characterized in that, The material of the surface protective barrier layer includes phosphosilicate glass.

8. A power transistor according to claim 1, characterized in that, The passivation layer is made of silicon nitride.

9. A power transistor according to claim 1, characterized in that, Both the base region metal layer and the emitter region metal layer are made of aluminum.

10. A power transistor according to claim 1, characterized in that, The back metal layer includes a titanium layer, a nickel layer, and a silver layer distributed sequentially along the direction away from the first conductivity type substrate.

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