Semiconductor structure

Abstract

A semiconductor structure includes a grain structure. The grain structure includes: a substrate; a first dielectric layer over the substrate; a first conductive structure in the first dielectric layer; a first edge protection layer on an edge surface of the first grain structure; and a first insulating layer laterally adjacent to the first edge protection layer, the first edge protection layer being between the first insulating layer and the edge surface of the first grain structure.

Description

Technical Field

[0001] This disclosure concerns semiconductor structures. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration of various electronic components. To accommodate the miniaturization of semiconductor components, wafer-level packaging has developed various technologies and applications that incorporate more different components with different functions. Iterative reductions in the minimum feature size have led to increased integration, allowing more components to be integrated into a given area.

[0003] With the continuous advancement of semiconductor technology, stacking and bonding semiconductor devices has become an effective alternative for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, the active circuitry, such as logic circuits, memory, and processor circuits, is at least partially fabricated on a separate substrate and then physically and electrically bonded together to form a functional device. These bonding processes employ complex techniques and require improvement. In addition to smaller electronic components, improvements in device packaging also seek to provide smaller packages that occupy less area than previous packages. Utility Model Content

[0004] Some embodiments described herein provide a semiconductor structure including a first grain structure. The first grain structure includes: a substrate; a first dielectric layer above the substrate; a first conductive structure in the first dielectric layer; a first edge protection layer on an edge surface of the first grain structure; and a first insulating layer laterally adjacent to the first edge protection layer, the first edge protection layer being between the first insulating layer and the edge surface of the first grain structure.

[0005] Some embodiments described herein provide a semiconductor structure comprising: a first grain structure, a bonding dielectric layer on the first grain structure, a second grain structure on the bonding dielectric layer, a first edge protection layer on an edge surface of the first grain structure, a first insulating layer laterally adjacent to the first edge protection layer and between a first insulating layer and the edge surface of the first grain structure, a second edge protection layer on an edge surface of the second grain structure, and a second insulating layer on the bonding dielectric layer and laterally adjacent to the second edge protection layer, the second edge protection layer being located between the second insulating layer and the edge surface of the second grain structure.

[0006] Some embodiments described herein provide a semiconductor structure comprising: a first grain structure, a bonding dielectric layer on the first grain structure, a second grain structure on the bonding dielectric layer, a first edge protection layer on an edge surface of the first grain structure, a first insulating layer laterally adjacent to the first edge protection layer and between a first insulating layer and an edge surface of the first grain structure, a second edge protection layer on an edge surface of the second grain structure, and a second insulating layer on the bonding dielectric layer and laterally adjacent to the second edge protection layer, the second edge protection layer being located between the second insulating layer and the edge surface of the second grain structure, wherein the second edge protection layer is located on the bonding dielectric layer and perpendicularly between the second insulating layer and the bonding dielectric layer. Attached Figure Description

[0007] The best understanding of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 A flowchart illustrating a method for forming a semiconductor package structure is shown according to some embodiments;

[0009] Figures 2 to 8 The semiconductor structure at various stages of forming the semiconductor package structure is illustrated according to some embodiments;

[0010] Figure 9 A semiconductor package structure is illustrated.

[0011] [Symbol Explanation]

[0012] 10: Method

[0013] 12,14,16,18,20,22,24,26,28,30: Operations

[0014] 100: Grain size

[0015] 101: Grain structure / semiconductor structure

[0016] 106: Supporting substrate

[0017] 108:Substrate

[0018] 109: Surface

[0019] 110: Downstream process structure

[0020] 111: Device Layer

[0021] 112: Interlayer dielectric layer

[0022] 114: Intermetallic dielectric layer

[0023] 116: Parts

[0024] 118: Passivation layer

[0025] 120: Membrane

[0026] 122: Dielectric layer

[0027] 124: Bonding Pad

[0028] 130: Edge protection layer / oxide nitride layer

[0029] 130L, 130V: Partial

[0030] 132, 134, 136, 138: Surface

[0031] 140: Gap or crack

[0032] 142: Inner grain closed ring structure

[0033] 150: Insulation layer

[0034] 160: Dielectric layer

[0035] 162: Bonding Pad

[0036] 164: Opening

[0037] 170: Conductive bumps or conductive balls

[0038] 172: Surface

[0039] 201: Grain structure / semiconductor structure

[0040] 209: Surface

[0041] 216: Parts

[0042] 222: Dielectric layer

[0043] 224: Bonding Pad

[0044] 230: Edge protection layer

[0045] 230L, 230V: Partial

[0046] 232: Surface

[0047] 234: Surface

[0048] 250: Insulation layer

[0049] 300: Semiconductor packaging structure / packaging SiON: Silicon oxynitride Detailed Implementation

[0050] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define relationships between the various embodiments and / or configurations discussed.

[0051] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0052] As used herein, terms such as “first,” “second,” and “third,” while describing various elements, components, regions, layers, and / or parts, should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. When terms such as “first,” “second,” and “third” are used herein, they do not imply sequence or order unless the context clearly indicates otherwise.

[0053] While the numerical ranges and parameter settings indicate the broad scope of this disclosure, the values ​​described in the specific embodiments have been reported as precisely as possible. However, any numerical value inherently contains some error, which is necessarily due to the standard deviation present in the respective test measurements. Furthermore, the terms "substantially," "approximately," and "about" as used herein generally indicate values ​​or ranges that are understandable to those skilled in the art. Alternatively, these terms "substantially," "approximately," and "about" mean that, in the consideration of those skilled in the art, this mean is within an acceptable standard deviation range. Those skilled in the art will understand that the acceptable standard error can vary depending on the technique used.

[0054] Other features and processes can also be included. For example, test structures can be included to aid in the verification testing of 3D packaged or 3DIC devices. Test structures can include, for example, test pads formed on redistribution layers or substrates, which allow for the use of 3D packaged or 3DIC testing, probes, and / or probe cards. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with intermediate verification testing methods that include known good dies to increase yield and reduce costs.

[0055] This disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. Embodiments of this disclosure pertain to a substrate or interconnect die and additional die interconnect structures connected thereto, such as System-on-a-Chip (SoIC) package designs and structures. The semiconductor structure includes a die structure whose sidewalls or edge surfaces are surrounded by at least one edge protection layer, such as an oxide nitride layer. The edge protection layer separates the edge surfaces of the die structure from a gap-filling dielectric material, preventing this gap-filling dielectric material from extending into any gaps or cracks on the edge surfaces of the die structure. Other features or processes may also be included. In some embodiments, the method of manufacturing the semiconductor structure includes forming an edge protection layer comprising an oxide nitride layer during assembly to surround the edge surfaces of the die structure. Therefore, the development of gap-filling dielectric cracks can be reduced or prevented. Furthermore, the overall strength of the semiconductor structure can also be improved or enhanced.

[0056] Examples of semiconductor packaging types include quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), 3D integrated circuit packages (3DICs), wafer-level packages (WLPs), package-on-packages (PoP), system-on-chip (SoC), or system-on-chip (SoIC) devices. Some of these 3D devices (e.g., 3DICs, SoCs, SoICs) are fabricated by placing a die on a wafer at the semiconductor wafer level. These 3D devices offer increased integration and other advantages, such as faster speeds and higher bandwidth due to reduced interconnect lengths between stacked chips. However, many challenges remain associated with 3D devices.

[0057] Figure 1 This is a flowchart of a method 10 for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Figure 1This is an embodiment of a method 10 for manufacturing a semiconductor structure. Method 10 includes several operations. In operation 12, a carrier substrate 106 and a first die structure 101 are provided, as shown... Figure 2 As shown. The carrier substrate 106 is configured to temporarily support a substrate or device thereon. The carrier substrate 106 is a blank glass, ceramic, silicon, or other suitable carrier substrate. The first grain structure 101 can be any monolithic semiconductor grain or a plurality of stacked semiconductor grains arranged perpendicularly and / or laterally relative to each other.

[0058] by Figure 2 For example, in some embodiments, the semiconductor die 101 includes a first semiconductor substrate (or base semiconductor substrate) 108 and various back-end-of-line (BEOL) structures 110. In some embodiments, the first semiconductor substrate 108 may include elemental semiconductors, such as silicon or germanium, and / or compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. In some embodiments, the first semiconductor substrate 108 may be a semiconductor-on-insulator (SOI) substrate. In various embodiments, the first semiconductor substrate 108 may be a planar substrate, a substrate with multiple fins, nanowires, or other forms known to those skilled in the art. Depending on the design requirements, the first semiconductor substrate 108 may be a P-type substrate or an N-type substrate and may have doped regions, such as P-type wells or N-type wells. The doped regions may be configured for N-type or P-type devices.

[0059] In some embodiments, the first semiconductor substrate 108 includes an isolation structure for at least one active region, such as shallow trench isolation (STI), and a first device layer may be disposed on / in the active region. The first device layer 111 includes various devices. In some embodiments, the various devices may include active elements, passive elements, or combinations thereof. In some embodiments, the first semiconductor substrate 108 may include circuitry for forming a storage array or other memory structure. In some embodiments, the first semiconductor substrate 108 may include circuitry for providing non-memory functions, such as communication, logic functions, processing, etc. In some embodiments, the device may include a collection of circuitry. This device may be, for example, a transistor, capacitor, resistor, diode, photodiode, fuse, or other similar device. In some embodiments, the first device layer includes a gate electrode, source or drain regions, spacers, etc.

[0060] The back-end process structure 110 includes layers stacked on a substrate 108 up to the surface 109 of a die 100. The surface 109 of the die 100 is opposite to the substrate 108. The back-end process structure 110 may include an interlayer dielectric (ILD) layer 112, one or more intermetallic dielectric (IMD) layers 114, various metal parts 116, and a passivation layer 118. In some embodiments, the interlayer dielectric layer 112 may be formed of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN or Si3N4), silicon carbide (SiC), or other similar dielectric materials, and may be deposited by any suitable deposition process. A “suitable deposition process” may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), and low-pressure CVD. Metal-organic CVD (MOCVD) process, plasma-enhanced CVD (PECVD) process, sputtering process, laser ablation, etc.

[0061] The intermetallic dielectric layer 114 may comprise an extremely low dielectric (ELK) dielectric material with a dielectric constant of less than about 2.6 (e.g., 2.5 to 2.2). In some embodiments, the ELK dielectric material comprises carbon-doped silicon oxide, fluorinated amorphous carbon, parylene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE; Teflon), or silicon oxide (SiOC) polymers. In some embodiments, the ELK dielectric material may comprise a porous version of an existing dielectric material, such as porous hydrogen silsesquioxane photoresist (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylene ether (PAE), porous SiLK, or porous silicon oxide (SiO2). The intermetallic dielectric layer 114 may be formed by any suitable deposition process. In some embodiments, the intermetallic dielectric layer 114 may be deposited by a PECVD process or by a spin coating process.

[0062] The metallic or conductive part 116 may include wires, lines, and via structures. The metallic part 116 may be formed of any suitable conductive material, such as tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, silver, gold, and combinations thereof. Other suitable conductive materials, such as conductive nitrogen compounds, are also possible and within the scope of this disclosure.

[0063] In operation 14, such as Figure 2As shown, a first die structure 101 is bonded over a carrier substrate 106. The first die structure 101 is bonded to the carrier substrate 106 via a bonding film (e.g., a polymer film 120) disposed between a bonding dielectric layer 122 (e.g., an RDL layer) of the first die structure 101 and the carrier substrate 106. The bonding dielectric layer 122 may also include bonding pads 124 formed therein, which enable electrical or thermal coupling to the bonding film 120. The bonding film 120 is a release film, a wafer adhesive film (DAF), an adhesive, or other materials suitable for bonding the die.

[0064] In operation 16, such as Figure 3 As shown, an edge protection layer, such as an oxide nitride layer 130, is disposed over the carrier substrate 106 and the first grain structure 101. The oxide nitride layer 130 is formed by deposition, chemical vapor deposition (CVD), or any other suitable process. In some embodiments, the oxide nitride layer 130 is formed to cover the upper surface 109 and the edge or sidewall surface 132 of the first grain structure 101. The oxide nitride layer 130 contacts the upper surface 109 and the edge surface 132 of the first grain structure 101. In some embodiments, the oxide nitride layer 130 is also located on the edge surface of the bonding film 120 and on the surface 134 of the carrier substrate 106 facing the first grain structure 101. In some embodiments, the bonding film 120 may extend beyond the first grain structure 101 (e.g., Figure 3 As shown, the oxide nitride layer 130 can be disposed on the upper surface 136 of the bonding film 120 facing the first grain structure 101.

[0065] In some embodiments, the oxide nitride layer 130 contains more than 5% oxygen (by weight). For example, the oxide nitride layer 130 comprises silicon oxynitride. In some embodiments, the thickness of the oxide nitride layer 130 is greater than 10 angstroms. In some embodiments, the thickness of the oxide nitride layer 130 is in the range of about 10 angstroms to about 80 angstroms.

[0066] In some embodiments, such as Figure 4As shown, the oxide nitride layer 130 extends into gaps or cracks 140 in the edge surface 132 of the first grain structure 101. Gaps or cracks 140 may arise from unintended mechanical forces or chemical reactions during the processing of the first grain structure 101 prior to or during the operation 14 of bonding the first grain structure 101 to the carrier substrate 106. For example, gaps or cracks 140 may be formed in or perpendicular to an inter-metal dielectric layer 114 on the edge surface 132 of the first grain structure 101. For example, gaps or cracks 140 may be formed perpendicularly between an inter-metal dielectric layer 114 and another dielectric layer (e.g., an etch stop layer). Gaps or cracks 140 can be formed by unintended physical forces or chemical reactions. For example, a plasma-cut dry etching process may selectively remove more dielectric material from the edge surface 132 of the grain structure, resulting in the formation of gaps or cracks 140, because low-k dielectric materials typically have higher etch rates compared to other materials (e.g., metallic materials or other dielectric materials such as silicon oxide). For example, picking up, placing or drying the first grain structure 101 may cause microcracks to appear on the edge surface 132, thereby leading to the formation of gaps or cracks 140.

[0067] The gap or crack 140 may be adjacent to a metal structure in the first grain structure 101. For example, the gap or crack 140 on the edge surface 132 may be adjacent to the inner grain-sealing structure 142 of the first grain structure 101. The oxide nitride layer 130 can prevent the gap-filling material (e.g., SiO2) surrounding the first grain structure 101 (described further later) from entering the gap or crack 140, so that the metal material (e.g., copper Cu) of the adjacent metal structure (e.g., the inner grain-sealing structure 142) will not diffuse into the SiO2 filling material, thereby improving the reliability of the semiconductor device. Furthermore, if SiO2 fills into the gap or crack 140, the SiO2 will grow unevenly, which may lead to pressure accumulation. The oxide nitride layer 130 can prevent or reduce the risk of such structural defects by preventing the surrounding SiO2 from extending into the gap or crack 140 (if any).

[0068] A nitrogen oxide layer 130 can be formed by using any type of process to cover the surface of the first grain structure 101 with a reactive gas. For example, the reactive gas can be nitrogen (N2). 2) Ammonia (NH4+) 4) Ethylene (C2H) 4) Or other suitable reactive gas processing. Multi-wafer fabrication (e.g., using a high-temperature tubular furnace) or monolithic fabrication (e.g., using a heated furnace) can be used to achieve reactive gas processing. Other suitable processes, which are included within the scope of this disclosure, may also be used.

[0069] In some embodiments, the edge protection layer 130 may be a material different from oxide nitride. For example, the edge protection layer 130 may be a carbonitride or a nitride such as silicon carbide oxide (SiOCN). The SiOCN layer 130 may be formed on the surface of the grain structure 101 using a reactive gas treatment process of any type. For example, the reactive gas may be ammonia (NH4+). 4) With ethylene (C2H) 4) Other dielectric materials may also be used for the edge protection layer 130, which are included within the scope of this disclosure.

[0070] In some embodiments, the edge protection layer 130 may comprise multiple layers stacked on top of each other. The multiple layers may be made of different materials, such as oxynitrides and nitrides, and may have different thickness values.

[0071] In operation 18, such as Figure 5 As shown, a portion of the edge protection layer 130 is removed, for example, a portion of the edge protection layer 130 is removed from the upper surface 109 of the grain structure 101. Figure 5 As shown, in some embodiments, a portion of the edge protection layer 130 on the upper surface 109 of the first grain structure 101 has been removed. The edge protection layer 130 remains on the edge surface 132 of the first grain structure 101, the edge surface 138 of the bonding film 120, and the upper surface 134 of the carrier substrate 106 facing the grain structure 101. The edge protection layer 130 is retained within the gap or crack 140. Figure 4 Other portions of the edge protector layer 130, such as the portion on surface 134 of the carrier substrate 106, may also be removed, which is suitable for various design scenarios. In some embodiments, measures are taken to ensure that at least a portion of the edge protector layer 130 remains on the edge surface 132 of the first grain structure 101. After operation 18, the thickness of the remaining portion of the edge protector layer 130 on the edge surface 132 of the grain structure 101 may range from 1 angstrom to approximately 10 angstroms. In some embodiments, when the edge protector layer 130 is silicon oxynitride (SiON), the remaining thickness of the edge protector layer 130 on the edge surface 132 may range from 1 angstrom to approximately 5 angstroms. When the edge protector layer 130 is a dielectric material other than silicon oxynitride (SiON), the remaining thickness of the edge protector layer 130 on the edge surface 132 may vary, and in some embodiments, the remaining thickness of the edge protector layer 130 on the edge surface 132 may be 50% of the remaining thickness when the edge protector layer 130 is silicon oxynitride (SiON).

[0072] A portion of the edge protective layer 130 may be removed by grinding and / or chemical mechanical polishing (CMP) or other suitable processes, all of which are included within the scope of this disclosure.

[0073] The edge protection layer 130 is retained on the edge surface 132 of the first grain structure 101 during operation 20, while referencing Figure 5 An insulating layer 150 is formed on a carrier substrate 106 and surrounds or laterally adjacent to the edge protection layer 130 and the first grain structure 101. For example, the insulating layer 150 is formed on a portion of the surface 134 of the carrier substrate 106 that is not occupied or overlapped by the first grain structure 101, such that the insulating layer 150 fills the "gap" left by the first grain structure 101. In some embodiments, the insulating layer 150 is disposed over the carrier substrate 106, the first grain structure 101, and the edge protection layer 130, and then a portion of the insulating layer 150 is removed, for example, to expose the upper surface 109 of the first grain structure 101. Polishing and / or CMP processes may be performed to remove portions of the insulating layer 150. The insulating layer 150 may comprise oxides, silicon oxide, or other dielectric materials. The insulating layer 150 may comprise dielectric materials having gap-filling properties or characteristics. In some embodiments, a second percentage (by weight) of the oxygen content of the insulating layer 150 is greater than a first percentage of the oxygen content of the edge protection layer 130.

[0074] In some embodiments, operation 18 is performed as part of operation 20. For example, while the insulating layer 150 is being formed, the edge protection layer 130 remains on the upper surface 109 of the first grain structure 101. Figure 5 As shown, portions of the edge protection layer 130 and the insulating layer 150 are removed together to expose the upper surface 109 of the first grain structure 101. This removal can be achieved by one or more suitable processes such as etching, planarization, chemical mechanical polishing (CMP), or any other appropriate method.

[0075] In operation 22, such as Figure 6 As shown, the bonding dielectric layer 160 and bonding pad 162 are formed over the first grain structure 101, the edge protection layer 130, and the insulating layer 150. The bonding dielectric layer 160 can be formed by depositing bonding dielectric material over the first grain structure 101, the edge protection layer 130, and the insulating layer 150 through deposition, CVD, or any other suitable process.

[0076] Bonding pad 162 can be formed in a via or through-hole in the bonding dielectric layer 160. For example, a portion of the bonding dielectric material can be removed by etching or any other suitable process to form an opening 164 extending through the bonding dielectric layer 160. Bonding pad 162 is formed by depositing conductive material into the opening 164 through electroplating, sputtering, deposition, or any other suitable process. The bonding dielectric layer 160 and bonding pad 162 can have a similar structure to the bonding dielectric layer 122 and bonding pad 124 (e.g., ...). Figure 2 (As shown).

[0077] In operation 24, such as Figure 7 As shown, the second grain structure 201 is bonded to the first grain structure 101. For example, the second grain structure 201 is disposed on the bonding dielectric layer 160 and bonded to the first grain structure 101 via a bonding dielectric layer 222 formed on the second grain structure 201. For example, bonding pads 224 formed in the bonding dielectric layer 222 of the second grain structure 201 are bonded to bonding pads 162, and the bonding dielectric layer 222 is bonded to the bonding dielectric layer 160. The second grain structure 201 can be bonded to the first grain structure 101 by hybrid bonding or any other suitable bonding process. In some embodiments, after the first grain structure 101 and the second grain structure 201 are bonded, a portion of the bonding dielectric layer 160 is exposed, and the exposed portion includes the surface 234 of the bonding dielectric layer 160 facing the second grain structure 201.

[0078] In operation 26, such as Figure 8 As shown, after the first grain structure 101 and the second grain structure 201 are bonded, an edge protection layer 230 is disposed on the edge surface 232 of the second grain structure 201 and deposited on the surface 234 of the bonding dielectric layer 160 exposed from the second grain structure 201. The material composition and formation process of the edge protection layer 230 on the second grain structure 201 may be the same as or different from the material composition and formation process of the edge protection layer 130 on the first grain structure 101. In some embodiments, a portion of the edge protection layer 230 is removed to expose the upper surface 209 of the second grain structure 201. Figure 4 Similarly, as shown, the edge protection layer 230 extends into the gaps or cracks in the edge surface 232 of the second grain structure 201 (for simplified illustration). Figure 8 (Not shown).

[0079] In operation 28, after the edge protection layer 230 is formed on the edge surface 232 of the second grain structure 201, an insulating layer 250 is formed on the bonding dielectric layer 160 and surrounds or laterally adjacent to the second grain structure 201. For example, the insulating layer 250 is formed on the portion of the surface 234 of the bonding dielectric layer 160 that is not occupied or overlapped by the second grain structure 201, such that the insulating layer 250 fills the “gap” left by the second grain structure 201. In some embodiments, the insulating layer 250 is disposed over the bonding dielectric layer 160, the second grain structure 201, and the edge protection layer 230, and then a portion of the insulating layer 250 is removed, for example, to expose the upper surface 209 of the second grain structure 201. Grinding and / or CMP processes may be performed to remove portions of the insulating layer 250. The insulating layer 250 may comprise oxide, silicon oxide, or other padding materials. In some embodiments, the oxygen content of the insulating layer 250, for example, by weight percentage, is greater than the oxygen content of the edge protection layer 230.

[0080] In some embodiments, if no other grain structures are arranged on the second grain structure 201, one or more insulating layers 250 or edge protection layers 230 may not be removed from the surface 209 of the second grain structure 201.

[0081] In operation 30, such as Figure 9 As shown, the carrier substrate 106 is removed. The carrier substrate 106 is separated from the first grain structure 101. For example, the carrier substrate 106 is separated from the first grain structure 101 by irradiating the polymer film 120 with electromagnetic radiation (e.g., UV light).

[0082] After separating the carrier substrate 106, the bonding film 120, a portion of the edge protection layer 130, and a portion of the insulating layer 150 can be removed to expose the bonding pads 124 in the bonding dielectric layer 122. The bonding film 120, a portion of the edge protection layer 130, and a portion of the insulating layer 150 can be removed by planarization, etching, CMP, or any other suitable process. In some embodiments, the bonding dielectric layer 122, the edge protection layer 130, and the insulating layer 150 have the same horizontal position on surface 172.

[0083] In some embodiments, such as Figure 9 As shown, conductive bumps or conductive balls 170 are formed on the conductive bonding pads 124 in the bonding dielectric layer 122. The conductive bumps or conductive balls 170 are formed by electroplating, solder paste, balling, or any other suitable process.

[0084] like Figure 9As shown, according to some embodiments of this disclosure, a semiconductor package structure 300 includes a first die structure or semiconductor structure 101 and a second die structure or semiconductor structure 201 stacked on the first die structure 101. The second semiconductor structure 201 is bonded to the first semiconductor structure 101. In some embodiments, the semiconductor package structure 300 is a system-integrated single-chip (SoIC) package structure, a wafer-on-a-substrate (CoWoS) package structure, an integrated fan-out (InFO) package structure, other 3D package structures, or other package structures involving assembling multiple semiconductor dies within the same package. The second semiconductor structure 201 is electrically connected to the first semiconductor structure 101 via, for example, bonding pads 162 and 224.

[0085] The bonding dielectric layer 222 of the second semiconductor structure 201 is bonded to the bonding dielectric layer 160 formed on the first semiconductor structure 300, and the bonding pad 224 of the second semiconductor structure 201 is bonded to the bonding pad 162 in the bonding dielectric layer 160. Each bonding pad 162 and bonding pad 224 extends through the corresponding dielectric layer 160 and dielectric layer 222, and is respectively connected to the semiconductor structure 101, the conductive component 116 of the semiconductor structure 201, and the conductive component 216.

[0086] Edge protection layers 130 and 230 are disposed on the edge surfaces 132 and 232 of each semiconductor structure 101 and semiconductor structure 201. Edge protection layers 130 and 230 are located between the edge surfaces 132 and 232 of the respective semiconductor structures 101 and 201, and separate the gap-filling insulating layers 150 and 250 from the edge surfaces 132 and 232 of the respective semiconductor structures 101 and 201. Edge protection layers 130 and 230 may extend into gaps or cracks 140 within the edge surfaces 132 and 232 of the respective semiconductor structures 101 and 201. Edge protection layer 230 may extend on the surface 234 of the bonding dielectric layer 160 between the first semiconductor structure 101 and the second semiconductor structure 201. An edge protection layer 230 may be vertically placed between insulating layers 150 and 250 in a portion 230L of the edge protection layer 230, which extends to the surface 234 of the bonding dielectric layer 160.

[0087] An edge protection layer 130 may be exposed on the surface 172 of the first semiconductor structure 101. Conductive bumps or conductive balls 170 are formed on the surface 172 of the first semiconductor structure 101.

[0088] In some embodiments, in the bonding film 120 (e.g. Figure 3 As shown, it extends beyond the first grain structure 101. Figure 3 (Not shown) When the edge protection layer 130 is disposed on the upper surface 136 of the bonding film 120 facing the first grain structure 101, the edge protection layer 130 may include a portion 130L, which extends from the portion 130L of the edge protection layer 130 and along the surface 172. For example, when the bonding film 120 is separated, the portion 130L of the edge protection layer 130 is not completely removed. The portion 130L of the edge protection layer 130 is perpendicularly located between the insulating layer 150 and the surface 172.

[0089] The portions 130V and 230V of edge protection layers 130 and 230 prevent insulating layers 150 and 250 from extending into the gaps of cracks in the edge surfaces 132 and 232 of the respective semiconductor structures 101 and 201. The portions 130V and 230V of edge protection layers 130 and 230 also prevent the diffusion of metallic material from conductive elements in semiconductor structures 101 and 201 into insulating layers 150 and 250. Therefore, edge protection layers 130 and 230 improve the mechanical and electrical reliability of package 300.

[0090] In some embodiments, one or more edge protection layers 130 and 230 are a multilayer structure and may contain multiple layers of different materials. For example, one or more edge protection layers 130 and 230 may contain a first silicon oxynitride (SiON) layer, a second SiON layer, and a nitride layer sandwiched between the first and second SiON layers.

[0091] In some embodiments, each die structure or semiconductor structure 101 and die structure or semiconductor structure 201 is a die, a wafer, or a package. In some embodiments, die structure 101 and die structure 201 are logic wafers, central processing unit (CPU) wafers, microcontroller (MCU) wafers, input / output (IO) wafers, application processor (AP) wafers, etc. Die structure 101 and die structure 201 may include a substrate, semiconductor elements formed in the substrate, a wafer mount, a passivation layer, a first dielectric layer, interconnect structures, conductive bonding pads, and / or conductive bumps.

[0092] In some embodiments, the semiconductor structure includes a first grain structure. The first grain structure includes: a substrate; a first dielectric layer above the substrate; a first conductive structure in the first dielectric layer; a first edge protection layer on an edge surface of the first grain structure; and a first insulating layer laterally adjacent to the first edge protection layer, the first edge protection layer being between the first insulating layer and the edge surface of the first grain structure.

[0093] In some embodiments, the first edge protection layer in the semiconductor structure comprises a dielectric material different from that of the first insulating layer.

[0094] In some embodiments, the first insulating layer in the semiconductor structure comprises silicon oxide, and the first edge protection layer comprises oxynitride.

[0095] In some embodiments, the first insulating layer in the semiconductor structure comprises silicon oxide, and the first edge protection layer comprises oxycarbonitride.

[0096] In some embodiments, the oxygen content of the first edge protection layer in the semiconductor structure includes a first percentage, and the oxygen content of the first insulating layer includes a second percentage, wherein the first percentage is less than the second percentage.

[0097] In some embodiments, the first edge protection layer in the semiconductor structure extends into the gaps at the edge surfaces of the first grain structure.

[0098] In some embodiments, the gap in the semiconductor structure is located in or perpendicular to the first dielectric layer.

[0099] In some embodiments, the semiconductor structure includes a substrate layer, wherein a first grain structure, a first insulating layer, and a first edge protection layer are located on the substrate layer.

[0100] In some embodiments, a portion of the first edge protection layer in the semiconductor structure is vertically located between the substrate layer and the first insulating layer.

[0101] In some embodiments, the semiconductor structure includes conductive bonding pads located in a substrate layer, wherein the conductive bonding pads are coupled to a first conductive structure.

[0102] In some embodiments, conductive bonding pads in the semiconductor structure extend through the substrate layer.

[0103] In some embodiments, the first grain structure in the semiconductor structure includes a bonding dielectric layer, which is located at the same horizontal position as the first edge protection layer on the surface of the semiconductor structure.

[0104] In some embodiments, the first insulating layer in the semiconductor structure is located at the same horizontal position on the surface of the semiconductor structure.

[0105] In some embodiments, a portion of the first edge protection layer in the semiconductor structure is vertically located between the first insulating layer and the surface of the semiconductor structure.

[0106] In some embodiments, the semiconductor structure includes bonding pads located in the bonding dielectric layer.

[0107] In some embodiments, the semiconductor structure includes conductive bumps or conductive balls located on bonding pads.

[0108] In some embodiments, the semiconductor structure includes a bonding dielectric layer on a first grain structure; a second grain structure on the bonding dielectric layer; a second edge protection layer on an edge surface of the second grain structure; and a second insulating layer laterally adjacent to the second edge protection layer, the second edge protection layer being located between the second insulating layer and the edge surface of the second grain structure, wherein the second edge protection layer is vertically located between the second insulating layer and the bonding dielectric layer.

[0109] In some embodiments, the semiconductor structure includes: a first grain structure, a bonding dielectric layer on the first grain structure, a second grain structure on the bonding dielectric layer, a first edge protection layer on an edge surface of the first grain structure, a first insulating layer laterally adjacent to the first edge protection layer and between a first insulating layer and the edge surface of the first grain structure, a second edge protection layer on an edge surface of the second grain structure, and a second insulating layer on the bonding dielectric layer and laterally adjacent to the second edge protection layer, the second edge protection layer being located between the second insulating layer and the edge surface of the second grain structure.

[0110] In some embodiments, the second edge protection layer in the semiconductor structure is located on the bonding dielectric layer and is perpendicularly located between the second insulating layer and the bonding dielectric layer.

[0111] In some embodiments, the semiconductor structure includes: a first grain structure, a bonding dielectric layer on the first grain structure, a second grain structure on the bonding dielectric layer, a first edge protection layer on an edge surface of the first grain structure, a first insulating layer laterally adjacent to the first edge protection layer and between a first insulating layer and an edge surface of the first grain structure, a second edge protection layer on an edge surface of the second grain structure, and a second insulating layer on the bonding dielectric layer and laterally adjacent to the second edge protection layer, the second edge protection layer being located between the second insulating layer and the edge surface of the second grain structure, wherein the second edge protection layer is located on the bonding dielectric layer and perpendicularly between the second insulating layer and the bonding dielectric layer.

[0112] In some embodiments, a method includes: bonding a grain structure to a base; performing an N2 process to form an edge protection layer on an edge surface of the grain structure; and forming an insulating layer laterally adjacent to the edge protection layer, the edge protection layer being located between the insulating layer and the edge surface of the grain structure.

[0113] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, Include: A first grain structure comprising: One substrate; A first dielectric layer above the substrate; A first conductive structure within the first dielectric layer; A first edge protection layer is located on an edge surface of the first grain structure; and A first insulating layer is laterally adjacent to the first edge protection layer, the first edge protection layer being located between the first insulating layer and the edge surface of the first grain structure.

2. The semiconductor structure as described in claim 1, characterized in that, The oxygen content of the first edge protective layer includes a first percentage, and the oxygen content of the first insulating layer includes a second percentage, wherein the first percentage is less than the second percentage.

3. The semiconductor structure as described in claim 1, characterized in that, It further includes a base layer, wherein the first grain structure, the first insulating layer and the first edge protection layer are located on the base layer.

4. The semiconductor structure as described in claim 3, characterized in that, A portion of the first edge protection layer is located vertically between the base layer and the first insulating layer.

5. The semiconductor structure as described in claim 3, characterized in that, It further includes a conductive bonding pad located in the substrate layer, wherein the conductive bonding pad is coupled to the first conductive structure.

6. The semiconductor structure as described in claim 5, characterized in that, The conductive bonding pad extends through the substrate layer.

7. The semiconductor structure as described in claim 1, characterized in that, The first grain structure includes a bonding dielectric layer, which is located at the same horizontal position on a surface of the semiconductor structure as the first edge protection layer.

8. The semiconductor structure as described in claim 1, characterized in that, Further includes: A one-bonded dielectric layer located on the first grain structure; A second grain structure located on the bonded dielectric layer; A second edge protection layer located on an edge surface of the second grain structure; and A second insulating layer is laterally adjacent to the second edge protection layer, and the second edge protection layer is located between the second insulating layer and the edge surface of the second grain structure. The second edge protection layer is located vertically between the second insulating layer and the bonding dielectric layer.

9. A semiconductor structure, characterized in that, Include: First grain structure; A one-bonded dielectric layer located on the first grain structure; A second grain structure located on the bonded dielectric layer; A first edge protection layer located on an edge surface of the first grain structure; A first insulating layer is laterally adjacent to the first edge protection layer, and the first edge protection layer is located between the first insulating layer and the edge surface of the first grain structure; A second edge protection layer located on an edge surface of the second grain structure; and A second insulating layer is located on the bonding dielectric layer and laterally adjacent to the second edge protection layer, the second edge protection layer being located between the second insulating layer and the edge surface of the second grain structure.

10. A semiconductor structure, characterized in that, Include: First grain structure; A one-bonded dielectric layer located on the first grain structure; A second grain structure located on the bonded dielectric layer; A first edge protection layer located on an edge surface of the first grain structure; A first insulating layer is laterally adjacent to the first edge protection layer, and the first edge protection layer is located between the first insulating layer and the edge surface of the first grain structure; A second edge protection layer located on an edge surface of the second grain structure; and A second insulating layer is located on the bonding dielectric layer and laterally adjacent to the second edge protection layer. The second edge protection layer is located between the second insulating layer and the edge surface of the second grain structure, wherein the second edge protection layer is located on the bonding dielectric layer and perpendicularly between the second insulating layer and the bonding dielectric layer.

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