Array substrate, display panel, display device

Abstract

This application provides an array substrate, a display panel, and a display device, relating to the field of display technology, for improving the reliability of the array substrate. The array substrate includes a substrate, a first conductive layer, an insulating layer, an active layer, and a second conductive layer. The first conductive layer is disposed on the substrate and includes a first signal line and a second signal line, with the end of the first signal line close to the second signal line. The insulating layer is disposed on the side of the first conductive layer away from the substrate, and includes a through-hole. The orthographic projection boundary of the through-hole on the substrate is connected to the orthographic projection boundary of the first signal line on the substrate, and also connected to the orthographic projection boundary of the second signal line on the substrate. The active layer is disposed on the side of the insulating layer away from the substrate, and the active layer is made of an oxide semiconductor material. The second conductive layer is disposed on the side of the active layer away from the substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] In the display field, metal oxide thin film transistors are widely used in array substrates because of their advantages of high mobility, high on / off ratio and high voltage withstand capability, making them suitable for a wider range of display products.

[0003] However, oxide thin-film transistor array substrates are sensitive to the manufacturing environment and are prone to burn-out due to static electricity during the fabrication process, thereby reducing product reliability. Utility Model Content

[0004] This application proposes an array substrate, a display panel, and a display device, aiming to improve the reliability of the array substrate.

[0005] To achieve the above objectives, embodiments of this application provide the following technical solutions: On one hand, an array substrate is provided, comprising a substrate, a first conductive layer, an insulating layer, an active layer, and a second conductive layer. The first conductive layer is disposed on the substrate and includes a first signal line and a second signal line, with the end of the first signal line close to the second signal line. The insulating layer is disposed on the side of the first conductive layer away from the substrate, and includes a through-hole. The orthographic boundary of the through-hole on the substrate is connected to the orthographic boundary of the first signal line on the substrate, and also connected to the orthographic boundary of the second signal line on the substrate. The active layer is disposed on the side of the insulating layer away from the substrate, and the active layer is made of an oxide semiconductor material. The second conductive layer is disposed on the side of the active layer away from the substrate.

[0006] The array substrate provided in this application includes a substrate, and a first conductive layer, an insulating layer, an active layer, and a second conductive layer sequentially disposed on the substrate. The first conductive layer includes a first signal line and a second signal line, with the end of the first signal line close to the second signal line; that is, the first and second signal lines are not connected and transmit different signals. The insulating layer includes a through-hole, the orthographic boundary of which is connected to the orthographic boundary of the first signal line and the orthographic boundary of the second signal line on the substrate. The active layer is made of an oxide semiconductor material.

[0007] Understandably, during the formation of the active layer of the oxide semiconductor material, only the first conductive layer on the substrate is conductive. The formation of the active layer will generate static electricity in the first conductive layer, and static electricity will accumulate between the end of the first signal line and the second signal line. Since the vias in the insulating layer connect the first and second signal lines, and the substrate lies beneath the vias, a portion of the first conductive layer can be retained within the orthogonal projection area of ​​the vias on the substrate during the formation of the first and second signal lines. This allows the first and second signal lines to connect first and then release static electricity.

[0008] Furthermore, since the via exposes part of the first conductive layer connecting the first signal line and the second signal line, the second conductive layer and the first conductive layer located in the via can be removed simultaneously during the formation of the second conductive layer, thereby disconnecting the first signal line and the second signal line.

[0009] Since the first and second signal lines have undergone electrostatic discharge in advance, the insulation layer is prevented from breaking down due to electrostatic discharge, thereby reducing the possibility of short circuits between signal lines transmitting different signals and improving the reliability of the array substrate.

[0010] In some embodiments, the orthographic projection of the via on the substrate is connected to the orthographic projection of the end of the first signal line near the second signal line on the substrate.

[0011] In some embodiments, the orthographic projection of the via on the substrate does not overlap with the orthographic projection of the first conductive layer on the substrate, nor with the orthographic projection of the second conductive layer on the substrate.

[0012] In some embodiments, the array substrate further includes a passivation layer disposed on the side of the second conductive layer away from the substrate. The passivation layer fills the vias.

[0013] In some embodiments, the array substrate includes a display area and a peripheral area located outside the display area. A first signal line is a gate line extending from the display area to the peripheral area. A second signal line is an electrostatic ring disposed in the peripheral area.

[0014] In some embodiments, the array substrate includes a display area and a peripheral area located outside the display area. A first signal line is a gate line extending from the display area to the peripheral area. A second signal line is a common voltage line disposed in the peripheral area.

[0015] In some embodiments, the array substrate includes a display area and a peripheral area located outside the display area. A first signal line is a gate line extending from the display area to the peripheral area. A second signal line is a gate drive signal line disposed in the peripheral area.

[0016] In some embodiments, the array substrate includes a display area and a peripheral area located outside the display area. A first signal line is a gate line extending from the display area to the peripheral area. A second signal line is a switch signal line disposed in the peripheral area.

[0017] On the other hand, a display panel is also provided, which includes an array substrate and a color filter substrate as described in the above embodiments. The color filter substrate is disposed opposite to the array substrate.

[0018] On the other hand, a display device is also provided, which includes a display panel and a controller as described in the above embodiments. The controller is electrically connected to the display panel.

[0019] The above-described display panel and display device have the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0021] Figure 1 A structural diagram of a display device provided in an embodiment of this application; Figure 2 for Figure 1 A partial sectional view of the display device along section line AA'; Figure 3 A partial cross-sectional view along section line AA' of another display device provided in an embodiment of this application; Figure 4 A top view of an array substrate provided in an embodiment of this application; Figure 5 for Figure 4 A magnified view of the array substrate at point M; Figure 6 for Figure 5 A partial cross-sectional view of the array substrate along section line BB'; Figure 7 A top view of another array substrate provided for embodiments of this application; Figure 8 A top view of another array substrate provided for embodiments of this application; Figure 9 for Figure 8A magnified view of a portion of the film layer at point N on the array substrate; Figure 10 A flowchart illustrating the fabrication method of the array substrate provided in this application; Figures 11-20 Schematic diagrams illustrating the steps of the method for fabricating the array substrate provided in this application; Figure 21 for Figure 10 The flowchart of step S5 in the preparation method is shown below; Figure 22 and Figure 23 for Figure 21 The preparation method shown in the diagram. Detailed Implementation

[0022] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0023] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0024] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0025] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0026] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0027] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0028] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0029] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0030] Electronic paper, or electrophoretic display (EPD) panels, exhibit irreplaceable low-power advantages due to their bistable characteristics, are widely used in products such as price tags, e-readers, and e-notes. As users continuously demand higher product performance, they are placing higher demands on the array substrates driving EPD displays. For example, a-Si thin-film transistor (TFT) array substrates are sufficient for general price tag products. However, for e-readers, e-notes, and especially color display products, the driving capability of a-Si TFT array substrates is insufficient. Because metal-oxide-slim thin-film transistors (Oxide TFTs) have higher mobility, higher on / off ratios, and better voltage withstand capabilities, they can be adapted to more advanced EPD products.

[0031] Due to the high mobility and extremely low off-state current characteristics of oxide semiconductors, oxide TFTs exhibit excellent switching characteristics. However, this also makes oxide TFTs very sensitive to the manufacturing environment. During the manufacturing process, electrostatic discharge (ESD) can easily cause the TFT backplane to burn out. In particular, during the fabrication of the active layer, ESD can easily be generated in the film layer located below the active layer, leading to damage to the aforementioned film layer and reducing product yield and reliability.

[0032] To address the aforementioned problems, in one aspect, embodiments of this application provide a display device. Figure 1 This is a structural diagram of a display device provided in an embodiment of this application.

[0033] See Figure 1 The display device 100 includes a display panel 10 and a controller 20. The controller 20 is electrically connected to the display panel 10. The controller 20 can be located on the non-display side of the display panel 10 and is used to control the display panel 10 to display images.

[0034] The aforementioned display device 100 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether it contains text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0035] On the other hand, embodiments of this application also provide a display panel. Figure 2 for Figure 1 A partial sectional view of the display device along section line AA'.

[0036] See Figure 2 The display panel 10 includes an array substrate 1 and a color filter substrate 2. The color filter substrate 2 is disposed opposite to the array substrate 1. For example, the display panel 10 can be an EPD display panel. For instance, the display panel 10 also includes an electrophoresis structure 30 disposed between the array substrate 1 and the color filter substrate 2, and the electrophoresis structure 30 contains electronic ink. The electronic ink moves under the action of electrodes, thereby realizing the display of the image on the display panel 10.

[0037] Embodiments of this application also provide another display panel. Figure 3 A partial cross-sectional view along section line AA' of another display device provided in an embodiment of this application.

[0038] See Figure 3 The display panel 10 includes an array substrate 1 and a color filter substrate 2. The color filter substrate 2 is disposed opposite to the array substrate 1. For example, the display panel 10 can be a liquid crystal display (LCD). For example, the display panel 10 also includes a liquid crystal layer 40 disposed between the array substrate 1 and the color filter substrate 2. An electric field exists between the color filter substrate 2 and the array substrate 1. The liquid crystal in the liquid crystal layer 40 changes direction under the action of the electric field, thereby regulating the transmittance of light in the liquid crystal layer 40, thereby realizing the display of the image on the display panel 10.

[0039] On the other hand, embodiments of this application also provide an array substrate. Figure 4 A top view of an array substrate provided in an embodiment of this application; Figure 5 for Figure 4 A magnified view of the array substrate at point M; Figure 6 for Figure 5 A partial cross-sectional view of the array substrate along section line BB'.

[0040] For example, such as Figure 4 The array substrate 1 shown can be applied to Figure 2 The EPD display panel shown in the embodiment can also be applied to Figure 3 The LCD display panel shown in the embodiment is an example of this.

[0041] See Figures 4-6 The array substrate 1 includes a substrate 3, a first conductive layer 4, an insulating layer 5, an active layer 6, and a second conductive layer 7. For example, the substrate 3 can be made of glass, and the first conductive layer 4 and the second conductive layer 7 can both be made of conductive metal.

[0042] For example, the first conductive layer 4 can be a gate conductive layer, the second conductive layer 7 can be a source / drain conductive layer, and the insulating layer 5 can be a gate insulating layer (GI).

[0043] A first conductive layer 4 is disposed on the substrate 3. The first conductive layer 4 includes a first signal line 41 and a second signal line 42, with the end 410 of the first signal line 41 close to the second signal line 42. It is understood that the first signal line 41 and the second signal line 42 are disposed on the same layer, and they transmit different signals.

[0044] For example, see Figure 4 The first signal line 41 extends in the X direction, and the second signal line 42 extends in the Y direction. Both ends 410 of the first signal line 41 have portions directly opposite the second signal line 42. If static electricity is present in the first conductive layer 4, it easily accumulates at these opposite portions. If the first signal line 41 and the second signal line 42 are not connected, the static electricity cannot be released at the ends 410, resulting in static electricity accumulation at the ends 410.

[0045] See Figure 5 and Figure 6 An insulating layer 5 is disposed on the side of the first conductive layer 4 away from the substrate 3. The insulating layer 5 includes a through-hole 51, the orthographic projection boundary E of the through-hole 51 on the substrate 3 is connected to the orthographic projection boundary F of the first signal line 41 on the substrate 3, and is connected to the orthographic projection boundary G of the second signal line 42 on the substrate 3.

[0046] For example, the orthographic projection boundary F of the first signal line 41 on the substrate 3 includes the boundary of the end 410 and the remaining boundaries. The orthographic projection boundary E of the via 51 on the substrate 3 can be connected to the boundary of the end 410 or to the remaining boundaries of the boundary F. The orthographic projection boundary G of the second signal line 42 on the substrate 3 includes the boundary near the end 410 and the remaining boundaries. The orthographic projection boundary E of the via 51 on the substrate 3 can be connected to the boundary of the boundary G near the end 410 or to the remaining boundaries of the boundary G.

[0047] Understandably, the insulating layer 5 has a via 51 connecting the first signal line 41 and the second signal line 42 at a position directly opposite to the first signal line 41 and the second signal line 42. Along the Z direction, the substrate 3 is located below the via 51.

[0048] For example, during the formation of the first conductive layer 4, a portion of the first conductive layer 4 may be retained within the orthogonal projection range of the via 51 on the substrate 3, allowing the aforementioned portion of the first conductive layer 4 to connect the first signal line 41 and the second signal line 42. The via 51 exposes this portion of the first conductive layer 4.

[0049] See also Figure 5 and Figure 6 The active layer 6 is disposed on the side of the insulating layer 5 away from the substrate 3, and the material of the active layer 6 includes an oxide semiconductor material. For example, the material of the active layer 6 can be IGZO (indium gallium zinc oxide).

[0050] For example, during the formation of the active layer 6 of the oxide semiconductor material, a portion of the active layer 6 is bombarded with high-energy plasma. Since the glass substrate 3 is non-conductive, and a conductive first conductive layer 4 is disposed on the substrate 3, the plasma passes through the insulating layer 5 and enters the first conductive layer 4, thereby generating static electricity in the first conductive layer 4. When the first signal line 41 and the second signal line 42 are not connected, static electricity accumulates at the end 410, causing the insulating layer 5 above that location to be broken down and burned, thus affecting the yield and reliability of the array substrate 1.

[0051] The second conductive layer 7 is disposed on the side of the active layer 6 away from the substrate 3. For example, the first conductive layer 4 and the second conductive layer 7 can be made of the same conductive metal, that is, the first conductive layer 4 and the second conductive layer 7 can be etched by the same etching solution.

[0052] For example, in the process of forming the second conductive layer 7, it is necessary to first form the entire surface of the second conductive layer 7 material, and then pattern the second conductive layer 7 to form signal lines. During the process of forming the entire surface of the second conductive layer 7 material, the via 51 is covered and filled by the second conductive layer 7. During the process of patterning the second conductive layer 7, the remaining second conductive layer 7 except for the aforementioned signal lines is removed, that is, the second conductive layer 7 within the via 51 is removed, thereby simultaneously removing a portion of the first conductive layer 4 within the via 51.

[0053] The array substrate 1 provided in this application includes a substrate 3, and a first conductive layer 4, an insulating layer 5, an active layer 6, and a second conductive layer 7 sequentially disposed on the substrate 3. The first conductive layer 4 includes a first signal line 41 and a second signal line 42. The end 410 of the first signal line 41 is close to the second signal line 42, meaning the first signal line 41 and the second signal line 42 are not connected and transmit different signals. The insulating layer 5 includes a through-hole 51. The orthographic boundary E of the through-hole 51 on the substrate 3 is connected to the orthographic boundary F of the first signal line 41 on the substrate 3 and to the orthographic boundary G of the second signal line 42 on the substrate 3. The active layer 6 is made of an oxide semiconductor material.

[0054] It is understandable that during the formation of the active layer 6 of the oxide semiconductor material, only the first conductive layer 4 on the substrate 3 is a conductive material. The formation of the active layer 6 will generate static electricity in the first conductive layer 4, and static electricity will accumulate between the end 410 of the first signal line 41 and the second signal line 42. The via 51 of the insulating layer 5 connects the first signal line 41 and the second signal line 42, and the substrate 3 is below the via 51. Therefore, during the formation of the first signal line 41 and the second signal line 42, a portion of the first conductive layer 4 can be retained within the orthogonal projection range of the via 51 on the substrate 3, so that the first signal line 41 and the second signal line 42 can be connected first to release static electricity.

[0055] Furthermore, since the via 51 exposes a portion of the first conductive layer 4 that connects the first signal line 41 and the second signal line 42, the second conductive layer 7 and the first conductive layer 4 located within the via 51 can be removed simultaneously during the formation of the second conductive layer 7, thereby disconnecting the first signal line 41 and the second signal line 42.

[0056] Since the first signal line 41 and the second signal line 42 have undergone electrostatic discharge in advance, the insulation layer 5 is prevented from being broken down by electrostatic discharge, thereby reducing the possibility of short circuit failure between signal lines transmitting different signals, and thus improving the yield and reliability of the array substrate 1.

[0057] In some embodiments, see Figure 5 and Figure 6 The orthographic projection of via 51 on substrate 3 is connected to the orthographic projection of the end 410 of the first signal line 41 near the second signal line 42 on substrate 3.

[0058] It is understood that via 51 connects the end 410 of the first signal line 41 and the second signal line 42. For example, during the formation of the first signal line 41 and the second signal line 42, a portion of the first conductive layer 4 is retained within the orthogonal projection range of the via 51 on the substrate 3, that is, at this time, the aforementioned portion of the first conductive layer 4 connects the end 410 of the first signal line 41 and the second signal line 42.

[0059] Since the static electricity in the first conductive layer 4 is mainly concentrated at the end 410 after the formation of the active layer 6, meaning that the static electricity accumulation at the end 410 is greater, by connecting the end 410 of the first signal line 41 to the second signal line 42, the path of static electricity transmission from the end 410 to the second signal line 42 can be shortened, thus facilitating the release of static electricity at the end 410 of the first signal line 41. Furthermore, the presence of this portion of the first conductive layer 4 increases the area for diluting static electricity in the first conductive layer 4, thereby further reducing the risk of the insulating layer 5 being burned by electrostatic discharge.

[0060] In some embodiments, see Figure 5 and Figure 6 The orthographic projection of via 51 onto substrate 3 does not overlap with the orthographic projection of the first conductive layer 4 onto substrate 3, nor with the orthographic projection of the second conductive layer 7 onto substrate 3. It can be understood that the first conductive layer 4 and the second conductive layer 7 do not exist within via 51.

[0061] For example, since via 51 connects the first signal line 41 and the second signal line 42, the absence of the first conductive layer 4 within via 51 can prevent short circuits between the first signal line 41 and the second signal line 42, which transmit different signals.

[0062] Furthermore, during the process of patterning the second conductive layer 7 to form signal lines, the second conductive layer 7 within the via 51 is removed, exposing a portion of the first conductive layer 4 within the via 51. Thus, during the removal of the second conductive layer 7 within the via 51, a portion of the first conductive layer 4 within the via 51 is simultaneously removed.

[0063] For example, see Figure 5 The distance d between the boundary E of the orthogonal projection of the via 51 on the substrate 3 and the boundary G of the orthogonal projection of the second conductive layer 7 on the substrate 3 is greater than 2 micrometers.

[0064] In some embodiments, see Figure 6 The array substrate 1 also includes a passivation layer 8, which is disposed on the side of the second conductive layer 7 away from the substrate 3. The passivation layer 8 fills the via 51. It is understood that the passivation layer 8 fills the via 51 to prevent the risk of corrosion at the via 51.

[0065] In some embodiments, see Figure 4 The array substrate 1 includes a display area 11 and a peripheral area 12 located outside the display area 11. A first signal line 41 is a gate line extending from the display area 11 to the peripheral area 12. A second signal line 42 is an electrostatic ring disposed in the peripheral area 12.

[0066] For example, see Figure 4 The array substrate 1 also includes a data driver chip 300 and a gate driver chip 400 disposed in the peripheral region 12. The data driver chip 300 is used to transmit data scan signals, and the gate driver chip 400 is used to transmit gate scan signals. For example, the data driver chip 300 can be disposed on the lower side of the peripheral region 12, and the gate driver chip 400 can be disposed on the right side of the peripheral region 12.

[0067] The array substrate 1 includes multiple first signal lines (gate lines) 41. The gate lines are led out from the gate driver chip 400, extend through the display area 11 to the right side of the peripheral area 12, and the right end 410 of the gate line is the "far end" of the gate line. The gate driver chip 400 sequentially transmits gate scan signals to the multiple gate lines.

[0068] For example, see Figure 5 and Figure 6 The insulating layer 5 also includes at least two through first openings 52. At least a portion of the second conductive layer 7 is electrically connected to the first signal line 41 and the second signal line 42 through the first openings 52, respectively. That is, after the complete array substrate 1 is formed, the static electricity at the far end of the gate line can be transferred to the static ring through the second conductive layer 5 and thus released.

[0069] However, if the static electricity at the far end of the gate line is released through an electrostatic ring after the complete array substrate 1 is formed, the insulating layer 5 may have been broken down at this time. In this case, multiple gate lines will be connected in series through the short-circuit ring, which will cause short circuit defects between the gate lines transmitting different signals.

[0070] Since the first signal line 41 and the second signal line 42 in this application have undergone electrostatic discharge before forming the complete array substrate 1, the possibility of the insulating layer 5 being broken down is reduced, thereby reducing the possibility of short circuits between gate lines transmitting different signals, and thus improving the yield and reliability of the array substrate 1.

[0071] Figure 7 A top view of another array substrate provided for an embodiment of this application.

[0072] In some embodiments, see Figure 7 The array substrate 1 includes a display area 11 and a peripheral area 12 located outside the display area 11. A first signal line 41 is a gate line that extends from the display area 11 to the peripheral area 12. A second signal line 42 is a common voltage line that is disposed in the peripheral area 12.

[0073] For example, see Figure 7 The array substrate 1 also includes a data driver chip 300 and a gate driver chip 400 disposed in the peripheral region 12. The data driver chip 300 is used to transmit data scan signals, and the gate driver chip 400 is used to transmit gate scan signals. For example, the data driver chip 300 can be disposed on the lower side of the peripheral region 12, and the gate driver chip 400 can be disposed on the right side of the peripheral region 12.

[0074] The array substrate 1 includes multiple first signal lines (gate lines) 41. The gate lines are led out from the gate driver chip 400, extend through the display area 11 to the right side of the peripheral area 12, and the right end 410 of the gate line is the "far end" of the gate line.

[0075] For example, in the peripheral region 12, the far end of the gate line faces the common voltage line. The common voltage line can lead the common voltage signal on the array substrate 1 to the common electrode through four pin points.

[0076] It is understandable that by setting the parameters in this application... Figure 5 and Figure 6 The structure of the corresponding embodiment can release static electricity between the far end of the gate line and the common voltage line in advance, thereby improving the structural reliability here and improving the yield and reliability of the array substrate 1.

[0077] Figure 8 A top view of another array substrate provided for embodiments of this application; Figure 9 for Figure 8A magnified view of a portion of the film layer at point N on the array substrate.

[0078] In some embodiments, see Figure 8 and Figure 9 The array substrate 1 includes a display area 11 and a peripheral area 12 located outside the display area 11. A first signal line 41 is a gate line extending from the display area 11 to the peripheral area 12. A second signal line 42 is a gate drive signal line disposed in the peripheral area 12.

[0079] For example, see Figure 8 The gate drive signal lines can be located within the array substrate row drive (GOA) cells in the peripheral region 12. For example, the GOA cells can be located on the left and right sides of the peripheral region 12. The gate drive signal lines are used to transmit gate scan signals.

[0080] For example, see Figure 8 The gate line extends from the left side of the peripheral area 12, through the display area 11, to the right side of the peripheral area 12. The left and right ends 410 of the gate line are both "far ends" of the gate line. The far ends of the gate line are directly opposite the gate drive signal line, and the two transmit different signals.

[0081] See Figure 9 At the point where the first signal line 41 and the second signal line 42 are directly opposite each other, that is, where the far end of the gate line is directly opposite the gate drive signal line, the orthogonal projection of the via 51 of the insulating layer 5 on the substrate 3 is connected to the orthogonal projection of the end 410 of the first signal line 41 on the substrate 3, and is also connected to the orthogonal projection of the second signal line 42 on the substrate 3.

[0082] Understandably, by setting such Figure 9 The structure shown can release static electricity between the far end of the gate line and the gate drive signal line in advance, thereby improving the structural reliability and the yield of the array substrate 1.

[0083] In some embodiments, see Figure 8 and Figure 9 The array substrate 1 includes a display area 11 and a peripheral area 12 located outside the display area 11. A first signal line 41 is a gate line extending from the display area 11 to the peripheral area 12. A second signal line 42 is a switch signal line disposed in the peripheral area 12. The switch signal line can be used to transmit switch signals to sub-pixels.

[0084] For example, see Figure 8 The grid line extends from the left side of the peripheral area 12, through the display area 11, to the right side of the peripheral area 12. The left and right ends 410 of the grid line are both "far ends" of the grid line. The far ends of the grid line are directly opposite the switch signal line, and the two transmit different signals.

[0085] See Figure 9 At the point where the first signal line 41 and the second signal line 42 are directly opposite each other, that is, where the far end of the gate line is directly opposite the switch signal line, the orthogonal projection of the via 51 of the insulating layer 5 on the substrate 3 is connected to the orthogonal projection of the end 410 of the first signal line 41 on the substrate 3, and is also connected to the orthogonal projection of the second signal line 42 on the substrate 3.

[0086] Understandably, by setting such Figure 9 The structure shown can release static electricity between the far end of the gate line and the switch signal line in advance, thereby improving the structural reliability and the yield of the array substrate 1.

[0087] On the other hand, a method for fabricating the array substrate 1 is also provided. Figure 10 A flowchart illustrating the fabrication method of the array substrate provided in this application; Figures 11-20 The diagram illustrates the steps of the fabrication method for the array substrate provided in this application. Among them, Figure 12 , Figure 14 , Figure 16 , Figure 18 and Figure 20 They are respectively Figure 11 , Figure 13 , Figure 15 , Figure 17 and Figure 19 A partial sectional view of the structure along section line BB'.

[0088] See Figure 10 The preparation method includes the following steps S1 to S5: Step S1: See Figure 11 and Figure 12 A first conductive layer 4 is formed on the substrate 3. The first conductive layer 4 includes a first signal line 41, a second signal line 42 and a connecting line 43. The end 410 of the first signal line 41 is close to the second signal line 42, and the first signal line 41 is connected to the second signal line 42 through the connecting line 43.

[0089] For example, along direction X, connecting line 43 includes left and right ends. The left end of connecting line 43 may be connected to end 410 of the first signal line 41, or to the boundary of the first signal line 41 at other locations. The right end of the first signal line 41 may be connected to the end of the second signal line 42 closest to the first signal line 41, or to the boundary of the second signal line 42 at other locations.

[0090] For example, along the Y direction, the first signal line 41 includes upper and lower sides. The connecting line 43 may be provided only on the upper side of the first signal line 41, or only on the lower side of the first signal line 41, or on both the upper and lower sides of the first signal line 41, or between the first signal line 41 and the second signal line 42.

[0091] For example, the shape of the orthographic projection of the connecting line 43 on the substrate 3 can be convex, arc-shaped, or any other arbitrary shape. This application does not limit the shape of the orthographic projection of the connecting line 43 on the substrate 3.

[0092] For example, see Figure 11 and Figure 12 In this embodiment of the application, the left end of the connecting line 43 is connected to the end 410 of the first signal line 41, the right end of the connecting line 43 is connected to the end of the second signal line 42 near the first signal line 41, and the connecting line 43 is disposed on the upper side of the first signal line 41.

[0093] It is understandable that the first signal line 41 and the second signal line 42 are arranged in the same layer and transmit different signals respectively. The end 410 of the first signal line 41 is the "far end", and static electricity is prone to accumulate between the far end and the second signal line 42 during subsequent fabrication processes. Connecting the end 410 of the first signal line 41 to the second signal line 42 through the connecting line 43 can make the direct alignment between the far end of the first signal line 41 and the second signal line 42 "disappear". Furthermore, the connecting line 43 can increase the area of ​​the first conductive layer 4 retained in step S1, which helps to reduce the density of static electricity per unit area on the first conductive layer 4 in subsequent processes.

[0094] Step S2: See Figure 13 and Figure 14 An insulating layer 5 is formed on the side of the first conductive layer 4 away from the substrate 3. The insulating layer 5 includes a through-hole 51 that exposes the connection line 43. The orthogonal projection boundary E of the through-hole 51 on the substrate 3 is connected to the orthogonal projection boundary F of the first signal line 41 on the substrate 3, and the boundary E is connected to the orthogonal projection boundary G of the second signal line 42 on the substrate 3.

[0095] For example, the orthographic projection boundary F of the first signal line 41 on the substrate 3 includes the boundary of the end 410 and the remaining boundaries. The orthographic projection boundary G of the second signal line 42 on the substrate 3 includes the boundary near the end 410 and the remaining boundaries.

[0096] For example, if the left end of connecting line 43 is connected to end 410 of the first signal line 41, then boundary E is connected to the boundary of end 410, and boundary E is also connected to the boundary of boundary G near end 410. If the left end of connecting line 43 is connected to the boundary of the first signal line 41 at other locations, then boundary E is connected to the boundary of boundary F at other locations. If the right end of connecting line 43 is connected to the boundary of the second signal line 42 at other locations, then boundary E is connected to the remaining boundaries of boundary G.

[0097] Understandably, the via 51 of the insulating layer 5 exposes the connecting line 43 so that the connecting line 43 can be removed later to separate the first signal line 41 from the second signal line 42, thereby avoiding a short circuit between the first signal line 41 and the second signal line 42 that transmit different signals.

[0098] For example, the insulating layer 5 further includes at least two through-holes 52, the first openings 52 exposing at least a portion of the first signal line 41 and at least a portion of the second signal line 42. For instance, in embodiments of this application, the insulating layer 5 includes four first openings 52, two of which are located above the first signal line 41 and two of which are located above the second signal line 42.

[0099] In some embodiments, see Figure 13 and Figure 14 The orthographic projection of via 51 on substrate 3 is connected to the orthographic projection of the end 410 of the first signal line 41 near the second signal line 42 on substrate 3. It can be understood that via 51 connects the end 410 of the first signal line 41 and the second signal line 42, that is, the connecting line 43 connects the end 410 and the second signal line 42.

[0100] By connecting the end 410 of the first signal line 41 to the second signal line 42, the path of static electricity transmission from the end 410 to the second signal line 42 can be shortened, thus facilitating the static electricity release at the end 410 of the first signal line 41. Furthermore, the presence of the aforementioned portion of the first conductive layer 4 increases the area for diluting static electricity in the first conductive layer 4, thereby further reducing the risk of the insulating layer 5 being burned by electrostatic discharge.

[0101] Step S3: See Figure 15 and Figure 16 An active layer 6 is formed on the side of the insulating layer 5 away from the substrate 3. The active layer 6 is made of an oxide semiconductor material. For example, the active layer 6 can be made of IGZO (indium gallium zinc oxide).

[0102] For example, during the formation of the active layer 6 of the oxide semiconductor material, a portion of the active layer 6 is bombarded with high-energy plasma. Since the substrate 3 is non-conductive and a first conductive layer 4 is disposed on the substrate 3 at this time, the plasma will pass through the insulating layer 5 and enter the first conductive layer 4, thereby generating static electricity in the first conductive layer 4.

[0103] Since the first signal line 41 and the second signal line 42 are connected by the connecting line 43 in step S1, the ends 410 of the first signal line 41 and the second signal line 42 are no longer directly opposite each other. This prevents static electricity from accumulating at the ends 410, instead distributing it evenly within the first conductive layer 4, thus reducing the likelihood of the insulating layer 5 being broken down. Furthermore, the presence of the connecting line 43 increases the area of ​​the first conductive layer 4, reducing the density of static electricity per unit area on the first conductive layer 4, thereby diluting the static electricity.

[0104] Step S4: See Figure 17 and Figure 18 A second conductive layer 7 is formed on the side of the active layer 6 away from the substrate 3, and at least a portion of the second conductive layer 7 is located within the via 51.

[0105] For example, the second conductive layer 7 is formed by deposition over the entire surface. After step S4, a portion of the first conductive layer 4 and a portion of the second conductive layer 7 are present in the via 51.

[0106] For example, at least a portion of the second conductive layer 7 is electrically connected to the first signal line 41 and the second signal line 42 through the first opening 52, respectively. That is, after the complete array substrate is formed, the static electricity at the distal end of the first signal line 41 can be transferred to the second signal line 42 through the second conductive layer 5 and thus released.

[0107] Step S5: See Figure 19 and Figure 20 Remove the portion of the second conductive layer 7 located within the via 51, and simultaneously remove the connecting wire 43.

[0108] For example, after forming the entire surface of the second conductive layer 7 material, the second conductive layer 7 needs to be patterned. During the patterning of the second conductive layer 7, the second conductive layer 7 within the via 51 is removed, thereby simultaneously removing a portion of the first conductive layer 4 within the via 51.

[0109] In the fabrication method provided in this application, a first conductive layer 4 is formed on a substrate 3. The first conductive layer 4 includes a first signal line 41, a second signal line 42, and a connecting line 43. The end 410 of the first signal line 41 is close to the second signal line 42, and the first signal line 41 is connected to the second signal line 42 through the connecting line 43. An insulating layer 5 is formed on the side of the first conductive layer 4 away from the substrate 3. The insulating layer 5 includes a through-hole 51 that exposes the connecting line 43. The orthographic boundary E of the through-hole 51 on the substrate 3 is connected to the orthographic boundary F of the first signal line 41 on the substrate 3, and boundary E is connected to the orthographic boundary G of the second signal line 42 on the substrate 3. An active layer 6 is formed on the side of the insulating layer 5 away from the substrate 3. The active layer 6 is made of an oxide semiconductor material. A second conductive layer 7 is formed on the side of the active layer 6 away from the substrate 3. At least a portion of the second conductive layer 7 is located within the through-hole 51. The portion of the second conductive layer 7 located within the through-hole 51 is removed, and the connecting line 43 is removed simultaneously to form an array substrate 1.

[0110] Understandably, the first signal line 41 and the second signal line 42 transmit different signals, with end 410 being the "far end" of the first signal line 41. Connecting end 410 of the first signal line 41 to the second signal line 42 via connecting line 43 eliminates the direct alignment between the far end of the first signal line 41 and the second signal line 42, and increases the area of ​​the retained first conductive layer 4. The via 51 of the insulating layer 5 exposes the connecting line 43 for subsequent removal.

[0111] During the formation of the active layer 6, only the first conductive layer 4 on the substrate 3 is a conductive material. This process generates static electricity in the first conductive layer 4, leading to static accumulation between the end 410 of the first signal line 41 and the second signal line 42. Since the first signal line 41 and the second signal line 42 are connected by the connecting line 43, there is no longer a direct alignment between the end 410 of the first signal line 41 and the second signal line 42. This prevents static electricity from accumulating at the end 410, instead distributing it evenly within the first conductive layer 4. This reduces the likelihood of the insulating layer 5 being damaged, thereby reducing the possibility of short circuits between signal lines transmitting different signals, and ultimately improving the yield and reliability of the array substrate 1.

[0112] Figure 21 for Figure 10 The flowchart of step S5 in the preparation method is shown below; Figure 22 and Figure 23 for Figure 21 The preparation method is illustrated in the diagram. Among them, Figure 23 for Figure 22 A partial sectional view of the structure along section line BB'.

[0113] In some embodiments, see Figure 21 The removal of the portion of the second conductive layer 7 located within the via 51 in step S5 above, and the simultaneous removal of the connecting line 43, specifically includes the following steps S501 and S502: Step S501: See Figure 22 and Figure 23 The second conductive layer 7 is etched using a mask layer 9 to remove the portion of the second conductive layer 7 located within the via 51, thereby exposing the connection line 43. The orthogonal projection of the mask layer 9 onto the substrate 3 does not overlap with the orthogonal projection of the via 51 onto the substrate 3. It can be understood that a through second opening 90 is provided on the mask layer 9, which exposes the via 51.

[0114] For example, a wet etching process can be used to etch away the second conductive layer 7 located in the via 51 through the second opening 90, thereby exposing the connection line 43.

[0115] Step S502: See Figure 19 and Figure 20 The connecting line 43 is etched and removed through the hole 51. It is understood that removing the connecting line 43 through the second opening 90 and the via 5 separates the first signal line 41 from the second signal line 42, thereby avoiding a short circuit between the first signal line 41 and the second signal line 42 that transmit different signals.

[0116] In some embodiments, see Figure 19 and Figure 20 The second conductive layer 7 and the connecting line 43 are etched using a wet etching process and the same etching solution. It is understood that the fabrication method provided in this application does not require the addition of a new mask and does not change the original process route, is compatible with the original process route, is simple to fabricate, and does not increase costs.

[0117] For example, the first conductive layer 4 and the second conductive layer 7 can be made of the same conductive metal, meaning that the connecting line 43 and the second conductive layer 7 can be etched by the same etching solution. After etching away the second conductive layer 7 within the via 51, there is no need to add a new mask or new process steps; the connecting line 43 can be directly etched through the mask layer 9 to separate the first signal line 41 from the second signal line 42.

[0118] In some embodiments, see Figure 5 and Figure 6 After removing the connecting line 43, the above preparation method further includes: A passivation layer 8 is formed on the side of the second conductive layer 7 away from the substrate 3, and the passivation layer 8 fills the via 51. It is understood that by filling the via 51 with the passivation layer 8, the risk of corrosion at the via 51 can be prevented, thereby improving the reliability of the array substrate 1.

[0119] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; A first conductive layer is disposed on the substrate; the first conductive layer includes a first signal line and a second signal line, with the end of the first signal line close to the second signal line. An insulating layer is disposed on the side of the first conductive layer away from the substrate; the insulating layer includes a through via, the orthographic projection boundary of the via on the substrate being connected to the orthographic projection boundary of the first signal line on the substrate, and also connected to the orthographic projection boundary of the second signal line on the substrate; An active layer is disposed on the side of the insulating layer away from the substrate, and the material of the active layer includes an oxide semiconductor material; A second conductive layer is disposed on the side of the active layer away from the substrate.

2. The array substrate according to claim 1, characterized in that, The orthographic projection of the via on the substrate is connected to the orthographic projection of the end of the first signal line near the second signal line on the substrate.

3. The array substrate according to claim 1 or 2, characterized in that, The orthographic projection of the via on the substrate does not overlap with the orthographic projection of the first conductive layer on the substrate, nor with the orthographic projection of the second conductive layer on the substrate.

4. The array substrate according to claim 1, characterized in that, The array substrate further includes a passivation layer, which is disposed on the side of the second conductive layer away from the substrate; The passivation layer fills the via.

5. The array substrate according to claim 1, characterized in that, The array substrate includes a display area and a peripheral area located outside the display area; The first signal line is a gate line that extends from the display area to the peripheral area; the second signal line is an electrostatic ring that is disposed in the peripheral area.

6. The array substrate according to claim 1, characterized in that, The array substrate includes a display area and a peripheral area located outside the display area; The first signal line is a gate line that extends from the display area to the peripheral area; the second signal line is a common voltage line that is located in the peripheral area.

7. The array substrate according to claim 1, characterized in that, The array substrate includes a display area and a peripheral area located outside the display area; The first signal line is a gate line that extends from the display area to the peripheral area; the second signal line is a gate drive signal line that is disposed in the peripheral area.

8. The array substrate according to claim 1, characterized in that, The array substrate includes a display area and a peripheral area located outside the display area; The first signal line is a gate line that extends from the display area to the peripheral area; the second signal line is a switch signal line that is located in the peripheral area.

9. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 8; A color filter substrate is disposed opposite to the array substrate.

10. A display device, characterized in that, include: The display panel as described in claim 9; The controller is electrically connected to the display panel.

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